Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20166

1

T1

3

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3378

1

T1

2

T11

3

T12

64

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17926

1

T1

5

T6

34

T7

20

auto[1]

5618

1

T2

13

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T275	7		T197	13		T354	15
values[0]	90	1			T145	19		T307	23		T288	5
values[1]	520	1			T143	13		T42	7		T192	18
values[2]	607	1			T11	3		T53	3		T28	14
values[3]	625	1			T12	27		T195	1		T56	12
values[4]	450	1			T12	15		T14	23		T52	3
values[5]	2722	1			T2	13		T3	2		T4	1
values[6]	725	1			T55	12		T70	26		T149	14
values[7]	813	1			T1	2		T54	15		T70	24
values[8]	668	1			T55	35		T56	18		T31	14
values[9]	1371	1			T12	22		T16	14		T49	25
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	733	1			T28	14		T31	17		T143	13
values[1]	704	1			T11	3		T12	27		T53	3
values[2]	430	1			T195	1		T56	12		T60	22
values[3]	2829	1			T2	13		T3	2		T4	1
values[4]	516	1			T16	13		T55	12		T31	7
values[5]	721	1			T70	26		T186	16		T169	15
values[6]	682	1			T1	2		T54	15		T55	35
values[7]	770	1			T53	12		T54	24		T31	14
values[8]	1091	1			T12	22		T16	14		T49	25
values[9]	141	1			T28	15		T99	1		T164	14
minimum	14927	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T31	8		T143	13		T42	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T28	1		T192	9		T145	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T53	3		T265	15		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	3		T12	16		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T195	1		T256	1		T146	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T56	12		T60	10		T61	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T2	1		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	8		T14	11		T52	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T55	7		T271	12		T272	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T16	1		T31	4		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T169	1		T204	1		T269	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T70	15		T186	15		T265	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T54	8		T56	10		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T55	16		T70	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T53	1		T54	12		T31	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T189	11		T179	26		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T53	15		T255	1		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T12	11		T16	1		T49	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T28	1		T229	5		T355	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T99	1		T164	1		T226	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T332	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T31	9		T42	2		T58	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	13		T192	9		T145	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T146	1		T158	7		T165	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T12	11		T188	8		T193	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T146	3		T194	14		T284	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T60	12		T254	10		T101	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T2	12		T13	8		T15	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	7		T14	12		T188	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T55	5		T272	8		T146	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T16	12		T31	3		T267	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T169	14		T269	11		T96	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T70	11		T186	1		T282	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T54	7		T56	8		T163	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T55	19		T70	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T53	11		T54	12		T31	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T189	9		T283	9		T122	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T53	16		T255	10		T192	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T12	11		T16	13		T49	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T28	14		T229	6		T355	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T164	13		T274	9		T315	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T332	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T354	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T275	1		T197	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T307	12		T288	5		T302	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T145	8		T321	1		T356	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T143	13		T42	5		T58	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T192	9		T95	2		T98	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T53	3		T31	8		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	3		T28	1		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T195	1		T256	1		T265	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	16		T56	12		T60	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T33	8		T179	15		T146	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T12	8		T14	11		T52	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T2	1		T3	2		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	1		T31	4		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T55	7		T169	1		T271	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T70	15		T149	14		T186	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T54	8		T150	1		T163	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T1	1		T70	13		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T56	10		T31	11		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T55	16		T179	26		T96	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T53	16		T54	12		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	465	1			T12	11		T16	1		T49	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T354	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T275	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T307	11		T302	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T145	11		T321	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T42	2		T58	7		T193	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T192	9		T95	14		T98	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T31	9		T146	1		T158	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T28	13		T188	8		T193	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T194	14		T284	7		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T12	11		T60	12		T193	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	3		T357	14		T358	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T12	7		T14	12		T188	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T2	12		T13	8		T15	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T16	12		T31	3		T161	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T55	5		T169	14		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T70	11		T186	1		T154	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T54	7		T163	8		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	1		T70	11		T192	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T56	8		T31	3		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T55	19		T283	9		T258	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T53	27		T54	12		T255	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T12	11		T16	13		T49	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T31	10		T143	1		T42	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T28	14		T192	10		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T53	1		T265	1		T146	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	3		T12	12		T188	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T195	1		T256	1		T146	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T56	1		T60	13		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T2	13		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	8		T14	13		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T55	6		T271	1		T272	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T16	13		T31	4		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T169	15		T204	1		T269	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T70	12		T186	2		T265	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T54	8		T56	9		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	2		T55	20		T70	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T53	12		T54	13		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T189	10		T179	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T53	17		T255	11		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T12	12		T16	14		T49	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T28	15		T229	7		T355	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T99	1		T164	14		T226	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T332	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T31	7		T143	12		T42	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T192	8		T145	7		T98	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T53	2		T265	14		T158	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	15		T152	12		T180	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T146	11		T194	9		T154	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T56	11		T60	9		T61	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T57	10		T32	13		T33	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	7		T14	10		T52	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T55	6		T271	11		T272	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T31	3		T267	16		T306	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T96	8		T280	9		T113	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T70	14		T186	14		T265	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T54	7		T56	9		T163	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T55	15		T70	12		T149	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T54	11		T31	10		T58	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T189	10		T179	25		T96	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T53	14		T192	10		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T12	10		T49	13		T56	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T229	4		T299	2		T202	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T226	7		T274	8		T197	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T332	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T354	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T275	7		T197	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T307	12		T288	1		T302	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T145	12		T321	5		T356	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T143	1		T42	5		T58	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T192	10		T95	16		T98	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T53	1		T31	10		T146	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	3		T28	14		T188	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T195	1		T256	1		T265	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	12		T56	1		T60	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T33	1		T179	1		T146	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T12	8		T14	13		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T2	13		T3	2		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T16	13		T31	4		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T55	6		T169	15		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T70	12		T149	1		T186	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T54	8		T150	1		T163	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T1	2		T70	12		T192	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T56	9		T31	4		T222	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T55	20		T179	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T53	29		T54	13		T255	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	431	1			T12	12		T16	14		T49	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T354	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T197	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T307	11		T288	4		T302	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T145	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T143	12		T42	2		T61	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T192	8		T98	13		T101	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T53	2		T31	7		T158	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T152	12		T50	1		T155	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T265	14		T194	9		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	15		T56	11		T60	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T33	7		T179	14		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T12	7		T14	10		T52	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T57	10		T32	13		T35	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T31	3		T159	15		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T55	6		T271	11		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T70	14		T149	13		T186	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T54	7		T163	4		T96	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T70	12		T265	10		T282	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T56	9		T31	10		T191	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	15		T179	25		T96	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T53	14		T54	11		T192	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T12	10		T49	13		T56	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13