Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20192

1

T1

3

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3352

1

T1

2

T11

3

T12

64

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18018

1

T1

5

T6

34

T7

20

auto[1]

5526

1

T2

13

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	250	1			T28	15		T192	21		T163	22
values[0]	43	1			T288	5		T356	1		T302	19
values[1]	588	1			T143	13		T42	7		T192	18
values[2]	609	1			T11	3		T53	3		T28	14
values[3]	589	1			T12	27		T195	1		T56	12
values[4]	467	1			T12	15		T14	23		T52	3
values[5]	2723	1			T2	13		T3	2		T4	1
values[6]	780	1			T55	12		T70	26		T186	16
values[7]	770	1			T1	2		T54	15		T70	24
values[8]	654	1			T53	12		T55	35		T56	18
values[9]	1153	1			T12	22		T16	14		T49	25
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	544	1			T28	14		T31	17		T143	13
values[1]	661	1			T11	3		T12	27		T53	3
values[2]	461	1			T195	1		T56	12		T60	22
values[3]	2798	1			T2	13		T3	2		T4	1
values[4]	528	1			T16	13		T55	12		T31	7
values[5]	756	1			T54	15		T70	26		T169	15
values[6]	763	1			T1	2		T55	35		T56	18
values[7]	705	1			T53	12		T31	14		T222	3
values[8]	1065	1			T12	22		T16	14		T49	25
values[9]	115	1			T28	15		T192	21		T99	1
minimum	15148	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T31	8		T143	13		T42	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T28	1		T278	1		T61	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T53	3		T265	15		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	3		T12	16		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T195	1		T56	12		T146	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T60	10		T256	1		T61	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T2	1		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	8		T14	11		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T55	7		T36	1		T271	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T16	1		T31	4		T186	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T54	8		T169	1		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T70	15		T265	11		T282	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T55	16		T56	10		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	1		T70	13		T149	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T53	1		T31	11		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T189	11		T179	26		T96	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T53	15		T54	12		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T12	11		T16	1		T49	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T28	1		T192	11		T229	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T99	1		T320	7		T226	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14871	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T95	1		T98	14		T337	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T31	9		T42	2		T192	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T28	13		T145	11		T95	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T146	1		T165	5		T291	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	11		T188	8		T158	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T146	3		T101	1		T194	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T60	12		T254	10		T284	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T2	12		T13	8		T15	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	7		T14	12		T188	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T55	5		T272	8		T146	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T16	12		T31	3		T186	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T54	7		T169	14		T269	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T70	11		T282	10		T153	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T55	19		T56	8		T163	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T70	11		T192	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T53	11		T31	3		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T189	9		T283	9		T258	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T53	16		T54	12		T163	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T12	11		T16	13		T49	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T28	14		T192	10		T229	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T274	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	1		T52	1		T60	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T95	13		T98	11		T166	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T28	1		T192	11		T163	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T99	1		T102	14		T320	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T288	5		T359	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T356	1		T302	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T143	13		T42	5		T192	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T61	5		T145	8		T95	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T53	3		T31	8		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	3		T28	1		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T195	1		T56	12		T265	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	16		T60	10		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T52	3		T33	8		T179	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	8		T14	11		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T2	1		T3	2		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T16	1		T31	4		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T55	7		T169	1		T271	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T70	15		T186	15		T265	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T54	8		T58	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T1	1		T70	13		T149	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T53	1		T55	16		T56	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T179	26		T159	18		T96	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T53	15		T54	12		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T12	11		T16	1		T49	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T28	14		T192	10		T163	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T102	9		T224	12		T260	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T359	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T302	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T42	2		T192	9		T58	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T145	11		T95	14		T98	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T31	9		T146	1		T165	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T28	13		T188	8		T158	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T101	1		T194	14		T284	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	11		T60	12		T193	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	3		T357	14		T111	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T12	7		T14	12		T188	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T2	12		T13	8		T15	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T16	12		T31	3		T267	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T55	5		T169	14		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T70	11		T186	1		T113	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T54	7		T163	8		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	1		T70	11		T192	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T53	11		T55	19		T56	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T283	9		T258	3		T165	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T53	16		T54	12		T58	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T12	11		T16	13		T49	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T31	10		T143	1		T42	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T28	14		T278	1		T61	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T53	1		T265	1		T146	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	3		T12	12		T188	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T195	1		T56	1		T146	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T60	13		T256	1		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T2	13		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	8		T14	13		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	6		T36	1		T271	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T16	13		T31	4		T186	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T54	8		T169	15		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T70	12		T265	1		T282	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T55	20		T56	9		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	2		T70	12		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T53	12		T31	4		T222	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T189	10		T179	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T53	17		T54	13		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T12	12		T16	14		T49	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T28	15		T192	11		T229	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T99	1		T320	1		T226	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14988	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T95	14		T98	12		T337	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T31	7		T143	12		T42	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T61	4		T145	7		T101	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T53	2		T265	14		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	15		T158	1		T152	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T56	11		T146	11		T101	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T60	9		T61	7		T147	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T52	2		T57	10		T32	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	7		T14	10		T159	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T55	6		T271	11		T272	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T31	3		T186	14		T159	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T54	7		T160	2		T96	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T70	14		T265	10		T282	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T55	15		T56	9		T163	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T70	12		T149	13		T159	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T31	10		T58	10		T191	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T189	10		T179	25		T96	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T53	14		T54	11		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T12	10		T49	13		T56	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T192	10		T229	4		T299	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T320	6		T226	7		T274	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T282	2		T307	11		T315	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T98	13		T331	1		T302	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T28	15		T192	11		T163	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T99	1		T102	10		T320	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T288	1		T359	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T356	1		T302	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T143	1		T42	5		T192	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T61	1		T145	12		T95	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T53	1		T31	10		T146	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	3		T28	14		T188	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T195	1		T56	1		T265	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	12		T60	13		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T52	1		T33	1		T179	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	8		T14	13		T188	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T2	13		T3	2		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	13		T31	4		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T55	6		T169	15		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T70	12		T186	2		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T54	8		T58	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T1	2		T70	12		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T53	12		T55	20		T56	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T179	1		T159	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T53	17		T54	13		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T12	12		T16	14		T49	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T192	10		T163	10		T309	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T102	13		T320	6		T260	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T288	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T302	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T143	12		T42	2		T192	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T61	4		T145	7		T98	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T53	2		T31	7		T148	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T158	1		T152	12		T50	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T56	11		T265	14		T101	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	15		T60	9		T61	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T52	2		T33	7		T179	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T12	7		T14	10		T159	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1133	1			T57	10		T32	13		T35	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T31	3		T159	15		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T55	6		T271	11		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T70	14		T186	14		T265	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T54	7		T163	4		T147	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T70	12		T149	13		T282	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T55	15		T56	9		T31	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T179	25		T159	17		T96	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T53	14		T54	11		T58	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T12	10		T49	13		T56	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13