Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20632

1

T1

3

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

2912

1

T1

2

T12

37

T14

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18033

1

T1

5

T6

34

T7

20

auto[1]

5511

1

T2

13

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	116	1			T146	17		T147	2		T159	18
values[0]	73	1			T56	21		T254	28		T210	24
values[1]	758	1			T12	22		T195	1		T54	15
values[2]	742	1			T1	2		T49	25		T55	35
values[3]	478	1			T16	13		T53	12		T54	24
values[4]	2865	1			T2	13		T3	2		T4	1
values[5]	487	1			T53	31		T189	20		T256	1
values[6]	544	1			T11	3		T36	1		T58	8
values[7]	745	1			T52	3		T255	11		T55	12
values[8]	819	1			T12	27		T53	3		T70	50
values[9]	999	1			T16	14		T55	1		T56	18
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T12	22		T36	1		T222	3
values[1]	679	1			T1	2		T49	25		T55	35
values[2]	516	1			T12	15		T16	13		T53	12
values[3]	2941	1			T2	13		T3	2		T4	1
values[4]	431	1			T150	1		T189	20		T256	1
values[5]	612	1			T11	3		T52	3		T29	31
values[6]	771	1			T255	11		T55	12		T42	7
values[7]	733	1			T12	27		T53	3		T55	1
values[8]	937	1			T16	14		T56	18		T28	14
values[9]	37	1			T147	2		T257	1		T159	18
minimum	15214	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T36	1		T222	1		T186	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	11		T150	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	14		T55	16		T193	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	1		T31	11		T179	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	1		T53	1		T54	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	8		T31	8		T33	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T2	1		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	11		T31	4		T143	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T256	1		T45	1		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T150	1		T189	11		T159	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	3		T52	3		T58	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T29	16		T36	1		T271	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T55	7		T42	5		T58	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T255	1		T192	20		T163	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	16		T55	1		T70	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T53	3		T70	15		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T16	1		T28	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T56	10		T149	14		T163	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T147	2		T257	1		T159	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T65	1		T258	3		T327	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14930	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T195	1		T54	8		T56	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T222	2		T186	1		T146	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T12	11		T169	12		T95	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	11		T55	19		T193	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	1		T31	3		T193	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T16	12		T53	11		T54	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T12	7		T31	9		T144	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T2	12		T13	8		T15	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	12		T31	3		T60	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T102	5		T259	2		T164	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T189	9		T101	1		T360	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T58	7		T158	3		T96	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T29	15		T158	10		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T55	5		T42	2		T58	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T255	10		T192	19		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	11		T70	11		T162	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T70	11		T192	11		T269	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T16	13		T28	13		T188	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T56	8		T163	8		T146	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T111	3		T261	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T258	3		T327	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	1		T52	1		T60	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T54	7		T56	4		T28	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T146	12		T147	2		T159	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T146	1		T194	10		T267	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T210	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T56	17		T254	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T56	12		T36	1		T186	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	11		T195	1		T54	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	14		T55	16		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	1		T31	11		T179	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	1		T53	1		T54	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T31	8		T33	8		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T2	1		T3	2		T4	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	8		T14	11		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T53	15		T256	1		T61	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T189	11		T265	9		T158	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	3		T58	1		T158	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T36	1		T150	1		T158	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T52	3		T55	7		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T255	1		T29	16		T192	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	16		T70	13		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T53	3		T70	15		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T16	1		T55	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T56	10		T149	14		T163	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T146	3		T111	3		T295	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T146	1		T194	14		T267	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T210	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T56	4		T254	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T186	1		T102	9		T154	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	11		T54	7		T28	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	11		T55	19		T222	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	1		T31	3		T193	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	12		T53	11		T54	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T31	9		T144	1		T59	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T2	12		T13	8		T15	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	7		T14	12		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T53	16		T102	5		T259	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T189	9		T158	7		T101	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T58	7		T158	3		T96	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T158	10		T223	4		T284	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T55	5		T42	2		T58	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T255	10		T29	15		T192	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	11		T70	11		T162	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T70	11		T192	11		T163	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T16	13		T28	13		T188	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T56	8		T163	8		T282	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T36	1		T222	3		T186	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	12		T150	1		T169	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T49	12		T55	20		T193	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	2		T31	4		T179	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	13		T53	12		T54	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	8		T31	10		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T2	13		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	13		T31	4		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T256	1		T45	1		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T150	1		T189	10		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	3		T52	1		T58	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T29	16		T36	1		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T55	6		T42	5		T58	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T255	11		T192	21		T163	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T12	12		T55	1		T70	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T53	1		T70	12		T192	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T16	14		T28	14		T188	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T56	9		T149	1		T163	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T147	1		T257	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T65	1		T258	4		T327	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14983	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T195	1		T54	8		T56	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T186	14		T146	17		T279	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T12	10		T265	10		T19	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T49	13		T55	15		T193	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T31	10		T179	25		T96	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T54	11		T223	12		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	7		T31	7		T33	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T53	14		T57	10		T32	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	10		T31	3		T143	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T102	4		T270	13		T268	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T189	10		T159	15		T101	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T52	2		T158	7		T147	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T29	15		T271	11		T158	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T55	6		T42	2		T58	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T192	18		T163	10		T21	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	15		T70	12		T98	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T53	2		T70	14		T147	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T191	9		T272	10		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T56	9		T149	13		T163	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T147	1		T159	17		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T258	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T56	11		T179	1		T102	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T54	7		T56	16		T254	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T146	4		T147	1		T159	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T146	2		T194	15		T267	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T210	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T56	5		T254	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T56	1		T36	1		T186	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	12		T195	1		T54	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T49	12		T55	20		T222	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	2		T31	4		T179	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T16	13		T53	12		T54	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T31	10		T33	1		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T2	13		T3	2		T4	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	8		T14	13		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T53	17		T256	1		T61	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T189	10		T265	1		T158	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	3		T58	8		T158	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T36	1		T150	1		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T52	1		T55	6		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T255	11		T29	16		T192	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T12	12		T70	12		T162	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T53	1		T70	12		T192	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T16	14		T55	1		T28	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T56	9		T149	1		T163	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T146	11		T147	1		T159	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T194	9		T267	9		T258	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T210	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T56	16		T254	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T56	11		T186	14		T179	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	10		T54	7		T265	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	13		T55	15		T146	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T31	10		T179	25		T96	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T54	11		T223	12		T111	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T31	7		T33	7		T59	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T57	10		T32	13		T35	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	7		T14	10		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T53	14		T61	7		T102	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T189	10		T265	8		T158	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T158	7		T96	8		T154	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T158	8		T159	15		T223	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	2		T55	6		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T29	15		T192	18		T271	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	15		T70	12		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T53	2		T70	14		T163	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T191	9		T272	10		T180	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T56	9		T149	13		T163	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13