Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T11	3		T12	12		T31	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T53	17		T28	15		T58	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	1		T169	10		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T255	11		T56	5		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T179	2		T146	6		T193	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T56	9		T70	12		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T2	13		T3	2		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T60	13		T278	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	2		T12	12		T60	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T49	12		T53	1		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T56	1		T149	1		T189	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T52	1		T33	1		T163	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T192	10		T44	4		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T55	20		T70	12		T58	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T16	14		T28	14		T278	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T162	8		T169	15		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	13		T29	16		T31	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T16	13		T53	12		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T158	8		T277	1		T279	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T188	9		T159	1		T280	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	15		T31	7		T192	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	14		T58	10		T163	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T271	11		T270	6		T289	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T56	16		T282	18		T147	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T179	26		T146	11		T193	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	9		T70	12		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T12	7		T54	18		T55	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T60	9		T61	7		T145	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	10		T101	4		T152	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T49	13		T53	2		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T56	11		T149	13		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T52	2		T33	7		T163	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T192	8		T223	2		T258	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T55	15		T70	14		T179	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T153	12		T165	5		T290	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T148	9		T165	7		T291	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	10		T29	15		T31	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T186	14		T148	12		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T158	1		T279	10		T38	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T159	17		T280	9		T288	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T104	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T276	18		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T274	10		T275	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	12		T192	23		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T53	17		T58	13		T188	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	3		T31	10		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T255	11		T28	15		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T55	1		T179	2		T146	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	14		T143	1		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T54	21		T272	9		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T70	12		T31	4		T42	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T2	13		T3	2		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T53	1		T278	1		T146	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	2		T149	1		T189	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	12		T52	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T56	1		T192	10		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T55	20		T70	12		T163	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T16	14		T28	14		T278	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	12		T58	8		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T14	13		T29	16		T31	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T16	13		T195	1		T222	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T104	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T276	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T274	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	15		T192	10		T191	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T53	14		T58	10		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T31	7		T146	11		T102	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T282	9		T147	20		T96	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T179	26		T193	2		T101	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T56	25		T143	12		T265	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T54	18		T272	10		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T70	12		T31	10		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T12	17		T55	6		T57	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T53	2		T146	17		T147	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T149	13		T189	10		T284	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T49	13		T52	2		T33	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T56	11		T192	8		T265	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T55	15		T70	14		T163	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T223	2		T153	12		T165	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T179	14		T158	7		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	10		T29	15		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T186	14		T148	12		T159	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13