Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19910

1

T1

5

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3634

1

T12

64

T16

13

T49

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17794

1

T1

5

T6

34

T7

20

auto[1]

5750

1

T2

13

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T102	23		T292	2		T293	1
values[0]	52	1			T294	1		T295	7		T296	16
values[1]	652	1			T12	15		T188	8		T150	1
values[2]	602	1			T49	25		T55	12		T31	14
values[3]	786	1			T53	3		T54	15		T28	14
values[4]	547	1			T12	27		T53	43		T70	24
values[5]	576	1			T55	35		T29	31		T31	7
values[6]	784	1			T11	3		T12	22		T52	3
values[7]	670	1			T1	2		T54	24		T55	1
values[8]	2884	1			T2	13		T3	2		T4	1
values[9]	1047	1			T14	23		T16	27		T255	11
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	888	1			T12	15		T49	25		T55	12
values[1]	566	1			T31	14		T192	18		T278	1
values[2]	685	1			T53	34		T54	15		T28	14
values[3]	608	1			T12	27		T53	12		T70	24
values[4]	700	1			T11	3		T55	35		T56	12
values[5]	808	1			T12	22		T52	3		T55	1
values[6]	2809	1			T2	13		T3	2		T4	1
values[7]	589	1			T1	2		T14	23		T54	24
values[8]	796	1			T16	27		T56	21		T150	1
values[9]	177	1			T192	12		T278	1		T43	3
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T55	7		T150	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	8		T49	14		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T278	1		T271	12		T59	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T31	11		T192	9		T265	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T53	15		T54	8		T163	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T53	3		T28	1		T33	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T36	2		T150	1		T285	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	16		T53	1		T70	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	3		T192	11		T189	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T55	16		T56	12		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T55	1		T70	15		T58	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	11		T52	3		T56	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T2	1		T3	2		T4	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T58	11		T145	8		T272	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	1		T14	11		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T54	12		T222	1		T60	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	1		T56	17		T163	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T16	1		T150	1		T146	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T43	3		T147	21		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T192	1		T278	1		T297	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T55	5		T162	7		T169	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	7		T49	11		T188	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T59	10		T193	2		T280	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T31	3		T192	9		T158	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T53	16		T54	7		T163	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T28	13		T188	8		T158	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T285	14		T19	1		T283	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	11		T53	11		T70	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T192	10		T189	9		T144	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T55	19		T28	14		T29	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T70	11		T285	11		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	11		T56	8		T58	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T2	12		T13	8		T15	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T58	12		T145	11		T272	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T1	1		T14	12		T255	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T54	12		T222	2		T60	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	13		T56	4		T163	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T16	12		T146	4		T254	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T259	2		T111	11		T166	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T192	11		T292	1		T298	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T293	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T102	14		T292	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T295	1		T299	3		T300	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T294	1		T296	1		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T150	1		T162	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	8		T188	1		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T55	7		T44	4		T193	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T49	14		T31	11		T192	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T54	8		T278	1		T271	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T53	3		T28	1		T31	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T53	15		T36	2		T189	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	16		T53	1		T70	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T192	11		T150	1		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T55	16		T29	16		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	3		T70	15		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	11		T52	3		T56	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	1		T55	1		T179	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T54	12		T272	11		T65	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T2	1		T3	2		T4	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T222	1		T58	11		T60	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	11		T16	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T16	1		T192	1		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T102	9		T292	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T295	6		T299	6		T300	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T296	15		T301	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T162	7		T169	9		T95	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	7		T188	7		T95	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T55	5		T193	2		T257	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T49	11		T31	3		T192	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T54	7		T59	10		T101	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T28	13		T31	9		T158	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T53	16		T189	9		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	11		T53	11		T70	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T192	10		T60	9		T284	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T55	19		T29	15		T31	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T70	11		T144	1		T193	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	11		T56	8		T28	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T285	11		T96	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T54	12		T272	8		T104	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T2	12		T13	8		T15	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T222	2		T58	12		T60	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T14	12		T16	13		T255	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T16	12		T192	11		T146	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T55	6		T150	1		T162	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T12	8		T49	12		T188	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T278	1		T271	1		T59	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T31	4		T192	10		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T53	17		T54	8		T163	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T53	1		T28	14		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T36	2		T150	1		T285	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	12		T53	12		T70	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	3		T192	11		T189	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T55	20		T56	1		T28	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T55	1		T70	12		T58	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	12		T52	1		T56	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T2	13		T3	2		T4	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T58	13		T145	12		T272	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	2		T14	13		T255	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T54	13		T222	3		T60	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T16	14		T56	5		T163	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T16	13		T150	1		T146	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T43	3		T147	1		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T192	12		T278	1		T297	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T55	6		T265	8		T159	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	7		T49	13		T101	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T271	11		T59	9		T265	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T31	10		T192	8		T265	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T53	14		T54	7		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T53	2		T33	7		T179	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T160	2		T19	1		T229	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	15		T70	12		T31	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T192	10		T189	10		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T55	15		T56	11		T29	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T70	14		T179	1		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	10		T52	2		T56	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T57	10		T32	13		T35	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T58	10		T145	7		T272	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	10		T186	14		T179	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T54	11		T60	9		T282	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T56	16		T163	4		T61	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T146	11		T148	12		T254	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T147	20		T111	11		T302	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T298	13		T303	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T293	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T102	10		T292	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T295	7		T299	7		T300	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T294	1		T296	16		T301	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T150	1		T162	8		T169	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	8		T188	8		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T55	6		T44	4		T193	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T49	12		T31	4		T192	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T54	8		T278	1		T271	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T53	1		T28	14		T31	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T53	17		T36	2		T189	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	12		T53	12		T70	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T192	11		T150	1		T60	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T55	20		T29	16		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	3		T70	12		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	12		T52	1		T56	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	2		T55	1		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T54	13		T272	9		T65	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T2	13		T3	2		T4	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T222	3		T58	13		T60	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T14	13		T16	14		T255	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T16	13		T192	12		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T102	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T299	2		T300	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T265	8		T159	17		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	7		T101	9		T180	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T55	6		T159	15		T280	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T49	13		T31	10		T192	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T54	7		T271	11		T59	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T53	2		T31	7		T33	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T53	14		T189	10		T163	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	15		T70	12		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T192	10		T160	2		T284	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	15		T29	15		T31	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T70	14		T161	5		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	10		T52	2		T56	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T179	1		T282	2		T96	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T54	11		T272	10		T104	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T57	10		T32	13		T35	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T58	10		T60	9		T145	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	10		T56	16		T163	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T146	11		T148	12		T254	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13