Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19974

1

T1

5

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3570

1

T12

27

T14

23

T16

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17962

1

T1

5

T6

34

T7

20

auto[1]

5582

1

T2

13

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T225	12		T318	19		-	-
values[0]	51	1			T253	2		T107	1		T287	6
values[1]	585	1			T55	12		T70	26		T149	14
values[2]	2910	1			T2	13		T3	2		T4	1
values[3]	695	1			T12	15		T14	23		T49	25
values[4]	524	1			T11	3		T28	14		T31	14
values[5]	563	1			T16	14		T55	1		T70	24
values[6]	675	1			T12	27		T53	3		T56	18
values[7]	520	1			T54	15		T189	20		T278	1
values[8]	660	1			T53	12		T54	24		T56	12
values[9]	1412	1			T1	2		T52	3		T53	31
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	798	1			T55	12		T70	26		T28	15
values[1]	2955	1			T2	13		T3	2		T4	1
values[2]	577	1			T14	23		T49	25		T55	35
values[3]	664	1			T11	3		T70	24		T28	14
values[4]	463	1			T16	14		T29	31		T188	9
values[5]	720	1			T12	27		T53	3		T54	15
values[6]	433	1			T54	24		T145	19		T44	4
values[7]	649	1			T53	12		T56	33		T31	7
values[8]	1131	1			T1	2		T52	3		T53	31
values[9]	224	1			T265	9		T148	10		T101	6
minimum	14930	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T149	14		T58	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T55	7		T70	15		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1520	1			T2	1		T3	2		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T195	1		T255	1		T58	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T55	16		T31	8		T265	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	11		T49	14		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	3		T31	11		T186	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T70	13		T28	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T280	10		T161	6		T258	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T16	1		T29	16		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T53	3		T54	8		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	16		T192	9		T191	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T145	8		T44	4		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T54	12		T223	13		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T56	29		T31	4		T179	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T53	1		T192	1		T265	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T1	1		T169	1		T60	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T52	3		T53	15		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T265	9		T148	10		T101	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T251	1		T182	3		T319	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14844	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T119	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T58	7		T60	9		T285	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T55	5		T70	11		T28	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T2	12		T12	18		T13	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T255	10		T58	12		T144	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T55	19		T31	9		T257	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	12		T49	11		T188	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T31	3		T186	1		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T70	11		T28	13		T169	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T280	4		T161	8		T258	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T16	13		T29	15		T188	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T54	7		T56	8		T189	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	11		T192	9		T191	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T145	11		T164	3		T268	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T54	12		T223	10		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T56	4		T31	3		T59	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T53	11		T192	11		T282	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	1		T169	12		T60	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T53	16		T42	2		T192	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T101	1		T102	5		T301	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T182	9		T320	11		T225	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T318	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T225	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T253	2		T107	1		T221	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T287	1		T321	1		T25	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T149	14		T58	1		T60	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T55	7		T70	15		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T2	1		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T195	1		T255	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	8		T55	16		T31	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	11		T49	14		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	3		T31	11		T186	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T28	1		T36	1		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T55	1		T280	10		T51	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T16	1		T70	13		T29	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T53	3		T56	10		T282	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T12	16		T192	9		T188	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T54	8		T189	11		T278	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T45	1		T282	10		T223	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T56	12		T31	4		T179	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T53	1		T54	12		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	412	1			T1	1		T56	17		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	416	1			T52	3		T53	15		T42	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T318	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T225	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T300	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T287	5		T321	14		T322	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T58	7		T60	9		T285	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T55	5		T70	11		T162	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T2	12		T12	11		T13	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T255	10		T28	14		T58	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	7		T55	19		T31	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	12		T49	11		T95	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T31	3		T186	1		T158	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T28	13		T169	9		T291	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T280	4		T51	2		T309	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	13		T70	11		T29	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T56	8		T101	4		T323	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	11		T192	9		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T54	7		T189	9		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T282	10		T223	10		T267	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T31	3		T59	10		T95	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T53	11		T54	12		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T1	1		T56	4		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T53	16		T42	2		T192	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T149	1		T58	8		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T55	6		T70	12		T28	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T2	13		T3	2		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T195	1		T255	11		T58	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T55	20		T31	10		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	13		T49	12		T188	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	3		T31	4		T186	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T70	12		T28	14		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T280	5		T161	9		T258	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	14		T29	16		T188	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T53	1		T54	8		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	12		T192	10		T191	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T145	12		T44	4		T164	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T54	13		T223	11		T164	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T56	6		T31	4		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T53	12		T192	12		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T1	2		T169	13		T60	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T52	1		T53	17		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T265	1		T148	1		T101	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T251	1		T182	10		T319	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14919	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T119	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T149	13		T61	7		T147	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	6		T70	14		T282	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T12	17		T57	10		T32	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T58	10		T159	17		T153	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T55	15		T31	7		T265	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	10		T49	13		T179	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T31	10		T186	14		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T70	12		T61	4		T148	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T280	9		T161	5		T258	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	15		T179	1		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T53	2		T54	7		T56	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	15		T192	8		T191	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T145	7		T324	6		T268	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T54	11		T223	12		T267	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T56	27		T31	3		T179	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T265	14		T282	9		T153	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T60	9		T146	28		T152	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T52	2		T53	14		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T265	8		T148	9		T101	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T182	2		T320	4		T325	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T326	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T318	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T225	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T253	2		T107	1		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T287	6		T321	15		T25	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T149	1		T58	8		T60	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T55	6		T70	12		T162	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T2	13		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T195	1		T255	11		T28	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	8		T55	20		T31	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	13		T49	12		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	3		T31	4		T186	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T28	14		T36	1		T169	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T55	1		T280	5		T51	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T16	14		T70	12		T29	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T53	1		T56	9		T282	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	12		T192	10		T188	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T54	8		T189	10		T278	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	1		T282	11		T223	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T56	1		T31	4		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T53	12		T54	13		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T1	2		T56	5		T169	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T52	1		T53	17		T42	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T318	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T221	2		T300	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T149	13		T61	7		T147	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T55	6		T70	14		T282	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T12	10		T57	10		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T58	10		T179	25		T153	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	7		T55	15		T31	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	10		T49	13		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T31	10		T186	14		T265	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T159	17		T291	6		T307	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T280	9		T270	11		T309	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T70	12		T29	15		T179	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T53	2		T56	9		T282	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	15		T192	8		T191	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T54	7		T189	10		T145	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T282	9		T223	12		T96	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T56	11		T31	3		T179	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T54	11		T153	12		T113	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T56	16		T60	9		T265	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T52	2		T53	14		T42	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13