Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20295

1

T1

3

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3249

1

T1

2

T11

3

T12

64

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17588

1

T6

34

T7

20

T8

10

auto[1]

5956

1

T1

5

T2

13

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	304	1			T1	3		T11	2		T18	1
values[0]	69	1			T31	14		T260	17		T327	26
values[1]	529	1			T16	14		T53	12		T29	31
values[2]	2929	1			T2	13		T3	2		T4	1
values[3]	488	1			T16	13		T255	11		T222	3
values[4]	718	1			T53	31		T55	1		T31	17
values[5]	732	1			T11	3		T12	22		T28	15
values[6]	533	1			T54	24		T56	39		T149	14
values[7]	676	1			T1	2		T53	3		T192	33
values[8]	860	1			T54	15		T70	26		T143	13
values[9]	1079	1			T49	25		T195	1		T55	12
minimum	14627	1			T6	34		T7	20		T8	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	750	1			T16	14		T53	12		T55	35
values[1]	2868	1			T2	13		T3	2		T4	1
values[2]	556	1			T16	13		T53	31		T255	11
values[3]	708	1			T55	1		T31	17		T33	8
values[4]	681	1			T11	3		T12	22		T56	21
values[5]	599	1			T53	3		T54	24		T56	18
values[6]	668	1			T1	2		T70	26		T143	13
values[7]	825	1			T49	25		T54	15		T56	12
values[8]	796	1			T55	12		T36	1		T58	1
values[9]	142	1			T195	1		T70	24		T163	13
minimum	14951	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T55	16		T28	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	1		T53	1		T31	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T2	1		T3	2		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	24		T14	11		T52	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	1		T163	11		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T53	15		T255	1		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T55	1		T31	8		T33	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T59	10		T147	21		T161	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T31	4		T149	14		T189	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	3		T12	11		T56	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T54	12		T192	11		T279	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T53	3		T56	10		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T58	12		T150	2		T179	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	1		T70	15		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T49	14		T56	12		T186	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T54	8		T42	5		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T36	1		T60	10		T272	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T55	7		T58	1		T223	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T163	5		T208	1		T101	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T195	1		T70	13		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14846	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T199	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T55	19		T28	13		T162	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T16	13		T53	11		T31	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T2	12		T13	8		T15	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	18		T14	12		T169	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T16	12		T163	11		T158	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T53	16		T255	10		T222	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T31	9		T282	7		T285	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T59	10		T161	11		T152	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T31	3		T189	9		T96	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	11		T56	4		T28	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T54	12		T192	10		T165	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T56	8		T153	12		T111	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T58	19		T169	12		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	1		T70	11		T192	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	11		T186	1		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T54	7		T42	2		T144	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T60	12		T272	8		T158	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T55	5		T223	10		T98	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T163	8		T101	1		T328	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T70	11		T282	10		T259	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T6	1		T52	1		T60	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T1	3		T11	2		T18	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T329	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T327	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T31	11		T260	9		T330	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T29	16		T162	1		T285	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T16	1		T53	1		T192	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T2	1		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	24		T14	11		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	1		T163	11		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T255	1		T222	1		T278	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T55	1		T31	8		T33	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T53	15		T61	8		T59	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T31	4		T148	10		T285	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	3		T12	11		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T54	12		T149	14		T189	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T56	27		T150	1		T254	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T192	11		T58	12		T188	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T53	3		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T186	15		T169	1		T146	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T54	8		T70	15		T143	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T49	14		T56	12		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T195	1		T55	7		T70	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14542	1			T6	33		T7	20		T8	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T331	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T327	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T31	3		T260	8		T332	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T29	15		T162	7		T285	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T16	13		T53	11		T192	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T2	12		T13	8		T15	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	18		T14	12		T169	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T16	12		T163	11		T158	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T255	10		T222	2		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T31	9		T282	7		T102	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T53	16		T59	10		T102	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T31	3		T285	11		T96	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	11		T28	14		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T54	12		T189	9		T122	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T56	12		T254	10		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T192	10		T58	19		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T192	11		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T186	1		T169	12		T146	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T54	7		T70	11		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	11		T163	8		T60	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T55	5		T70	11		T282	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T55	20		T28	14		T162	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T16	14		T53	12		T31	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	13		T3	2		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	20		T14	13		T52	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T16	13		T163	12		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T53	17		T255	11		T222	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T55	1		T31	10		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T59	11		T147	1		T161	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T31	4		T149	1		T189	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	3		T12	12		T56	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T54	13		T192	11		T279	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T53	1		T56	9		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T58	21		T150	2		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	2		T70	12		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T49	12		T56	1		T186	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T54	8		T42	5		T144	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T36	1		T60	13		T272	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T55	6		T58	1		T223	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T163	9		T208	1		T101	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T195	1		T70	12		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14930	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T199	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T55	15		T61	4		T165	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T31	10		T192	8		T265	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T57	10		T29	15		T32	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	22		T14	10		T52	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T163	10		T158	7		T159	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T53	14		T61	7		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T31	7		T33	7		T282	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T59	9		T147	20		T161	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T31	3		T149	13		T189	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	10		T56	16		T282	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T54	11		T192	10		T279	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T53	2		T56	9		T153	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T58	10		T179	14		T265	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T70	14		T143	12		T271	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T49	13		T56	11		T186	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T54	7		T42	2		T147	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T60	9		T272	10		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T55	6		T223	12		T98	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T163	4		T101	4		T23	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T70	12		T282	9		T155	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T210	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T199	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T1	3		T11	2		T18	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T329	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T327	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T31	4		T260	9		T330	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T29	16		T162	8		T285	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T16	14		T53	12		T192	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T2	13		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	20		T14	13		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	13		T163	12		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T255	11		T222	3		T278	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T55	1		T31	10		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T53	17		T61	1		T59	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T31	4		T148	1		T285	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	3		T12	12		T28	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T54	13		T149	1		T189	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T56	14		T150	1		T254	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T192	11		T58	21		T188	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	2		T53	1		T192	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T186	2		T169	13		T146	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T54	8		T70	12		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T49	12		T56	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T195	1		T55	6		T70	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14627	1			T6	34		T7	20		T8	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T331	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T327	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T31	10		T260	8		T199	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T29	15		T165	7		T320	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T192	8		T265	10		T113	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T55	15		T57	10		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	22		T14	10		T52	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T163	10		T158	7		T258	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T265	8		T46	1		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T31	7		T33	7		T282	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T53	14		T61	7		T59	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T31	3		T148	9		T96	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	10		T282	2		T147	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T54	11		T149	13		T189	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T56	25		T254	17		T153	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T192	10		T58	10		T179	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	2		T145	7		T96	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T186	14		T146	17		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T54	7		T70	14		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T49	13		T56	11		T163	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T55	6		T70	12		T282	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13