Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19948

1

T1

5

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3596

1

T12

27

T14

23

T16

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17927

1

T1

5

T6

34

T7

20

auto[1]

5617

1

T2

13

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	313	1			T42	7		T222	3		T169	15
values[0]	8	1			T322	4		T333	3		T334	1
values[1]	583	1			T55	12		T149	14		T58	8
values[2]	2922	1			T2	13		T3	2		T4	1
values[3]	697	1			T12	15		T14	23		T49	25
values[4]	516	1			T11	3		T28	14		T31	14
values[5]	595	1			T70	24		T29	31		T150	1
values[6]	721	1			T12	27		T16	14		T53	3
values[7]	428	1			T54	15		T189	20		T191	18
values[8]	629	1			T53	12		T54	24		T56	12
values[9]	1214	1			T1	2		T52	3		T53	31
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	607	1			T55	12		T28	15		T150	1
values[1]	2950	1			T2	13		T3	2		T4	1
values[2]	596	1			T14	23		T49	25		T55	35
values[3]	544	1			T11	3		T70	24		T28	14
values[4]	569	1			T16	14		T29	31		T188	9
values[5]	698	1			T12	27		T53	3		T55	1
values[6]	440	1			T54	39		T191	18		T145	19
values[7]	698	1			T53	12		T56	33		T31	7
values[8]	1170	1			T1	2		T52	3		T53	31
values[9]	144	1			T222	3		T265	9		T101	6
minimum	15128	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T150	1		T61	8		T193	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T55	7		T28	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T2	1		T3	2		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T195	1		T255	1		T70	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T55	16		T31	8		T265	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	11		T49	14		T179	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	3		T31	11		T186	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T70	13		T28	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T280	10		T161	6		T258	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T16	1		T29	16		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	3		T55	1		T56	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	16		T192	9		T254	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T54	8		T145	8		T44	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T54	12		T191	10		T282	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T56	29		T31	4		T179	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T53	1		T36	1		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T1	1		T169	1		T60	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T52	3		T53	15		T42	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T265	9		T101	5		T102	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T222	1		T251	1		T182	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14919	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T278	1		T282	10		T176	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T193	3		T285	14		T95	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T55	5		T28	14		T162	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T2	12		T12	18		T13	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T255	10		T70	11		T58	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T55	19		T31	9		T257	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	12		T49	11		T95	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T31	3		T186	1		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T70	11		T28	13		T169	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T280	4		T161	8		T258	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	13		T29	15		T188	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T56	8		T189	9		T272	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	11		T192	9		T254	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T54	7		T145	11		T164	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T54	12		T191	8		T282	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T56	4		T31	3		T59	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T53	11		T192	11		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T1	1		T169	12		T60	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T53	16		T42	2		T192	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T101	1		T102	5		T320	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T222	2		T182	9		T320	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	1		T52	1		T58	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T282	7		T335	11		T322	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T146	12		T101	5		T152	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T42	5		T222	1		T169	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T333	2		T334	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T322	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T149	14		T58	1		T60	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T55	7		T162	1		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T2	1		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T195	1		T255	1		T70	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	8		T55	16		T31	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	11		T49	14		T188	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	3		T31	11		T186	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	1		T36	1		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T280	10		T51	5		T154	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T70	13		T29	16		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T53	3		T55	1		T56	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T12	16		T16	1		T192	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T54	8		T189	11		T145	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T191	10		T96	6		T267	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T56	12		T31	4		T179	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T53	1		T54	12		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T1	1		T56	17		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T52	3		T53	15		T192	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T146	3		T101	1		T152	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T42	2		T222	2		T169	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T333	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T322	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T58	7		T60	9		T193	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T55	5		T162	7		T282	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T2	12		T12	11		T13	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T255	10		T70	11		T28	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	7		T55	19		T31	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	12		T49	11		T188	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T31	3		T186	1		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T28	13		T169	9		T95	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T280	4		T51	2		T154	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T70	11		T29	15		T158	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T56	8		T272	8		T101	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	11		T16	13		T192	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T54	7		T189	9		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T191	8		T267	9		T111	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T31	3		T59	10		T95	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T53	11		T54	12		T282	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T1	1		T56	4		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T53	16		T192	21		T163	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T150	1		T61	1		T193	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T55	6		T28	15		T162	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	13		T3	2		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T195	1		T255	11		T70	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T55	20		T31	10		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	13		T49	12		T179	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	3		T31	4		T186	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T70	12		T28	14		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T280	5		T161	9		T258	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T16	14		T29	16		T188	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T53	1		T55	1		T56	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	12		T192	10		T254	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T54	8		T145	12		T44	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T54	13		T191	9		T282	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T56	6		T31	4		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T53	12		T36	1		T192	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T1	2		T169	13		T60	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T52	1		T53	17		T42	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T265	1		T101	2		T102	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T222	3		T251	1		T182	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14986	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T278	1		T282	8		T176	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T61	7		T193	2		T160	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T55	6		T147	1		T159	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T12	17		T57	10		T32	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T70	14		T58	10		T153	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T55	15		T31	7		T265	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	10		T49	13		T179	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T31	10		T186	14		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T70	12		T61	4		T291	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T280	9		T161	5		T258	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T29	15		T179	1		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T53	2		T56	9		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	15		T192	8		T254	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T54	7		T145	7		T324	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T54	11		T191	9		T282	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T56	27		T31	3		T179	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T265	14		T153	12		T113	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T60	9		T146	28		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T52	2		T53	14		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T265	8		T101	4		T102	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T182	2		T320	4		T325	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T149	13		T147	20		T194	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T282	9		T181	6		T326	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T146	4		T101	2		T152	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T42	5		T222	3		T169	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T333	3		T334	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T322	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T149	1		T58	8		T60	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T55	6		T162	8		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T2	13		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T195	1		T255	11		T70	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	8		T55	20		T31	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	13		T49	12		T188	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	3		T31	4		T186	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T28	14		T36	1		T169	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T280	5		T51	7		T154	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T70	12		T29	16		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T53	1		T55	1		T56	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	12		T16	14		T192	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T54	8		T189	10		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T191	9		T96	1		T267	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T56	1		T31	4		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T53	12		T54	13		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T1	2		T56	5		T169	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T52	1		T53	17		T192	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T146	11		T101	4		T152	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T42	2		T336	1		T320	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T149	13		T61	7		T193	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T55	6		T282	9		T147	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T12	10		T57	10		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T70	14		T58	10		T159	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	7		T55	15		T31	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	10		T49	13		T179	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T31	10		T186	14		T265	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T61	4		T159	17		T307	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T280	9		T154	13		T270	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T70	12		T29	15		T179	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T53	2		T56	9		T272	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	15		T192	8		T254	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T54	7		T189	10		T145	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T191	9		T96	5		T267	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T56	11		T31	3		T179	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T54	11		T282	9		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T56	16		T60	9		T265	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T52	2		T53	14		T192	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13