Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T1

5

T2

13

T3

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18008

1

T1

3

T6

34

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

5536

1

T1

2

T2

13

T3

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17926

1

T1

3

T6

34

T7

20

auto[1]

5618

1

T1

2

T2

13

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19796

1

T1

4

T2

1

T3

2

auto[1]

3748

1

T1

1

T2

12

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	210	1			T31	17		T58	8		T179	2
values[0]	11	1			T294	1		T307	10		-	-
values[1]	735	1			T14	23		T53	43		T255	11
values[2]	683	1			T54	24		T33	8		T186	16
values[3]	658	1			T192	18		T256	1		T265	15
values[4]	637	1			T11	3		T12	15		T16	14
values[5]	597	1			T28	14		T31	7		T58	23
values[6]	600	1			T52	3		T54	15		T55	13
values[7]	606	1			T12	22		T49	25		T70	26
values[8]	692	1			T53	3		T55	35		T56	18
values[9]	3197	1			T1	2		T2	13		T3	2
minimum	14918	1			T1	3		T6	34		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	695	1			T14	23		T53	31		T54	24
values[1]	2794	1			T2	13		T3	2		T4	1
values[2]	782	1			T12	15		T195	1		T56	21
values[3]	459	1			T11	3		T16	14		T28	15
values[4]	699	1			T52	3		T54	15		T55	12
values[5]	626	1			T55	1		T56	12		T29	31
values[6]	527	1			T12	22		T49	25		T56	18
values[7]	745	1			T12	27		T16	13		T53	3
values[8]	886	1			T1	2		T143	13		T58	8
values[9]	143	1			T31	17		T192	21		T291	12
minimum	15188	1			T1	3		T6	34		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

3979

1

T12

32

T14

10

T49

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T14	11		T179	26		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T53	15		T54	12		T150	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T45	1		T193	4		T160	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1532	1			T2	1		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	8		T56	17		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T195	1		T192	9		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T11	3		T16	1		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T28	1		T31	11		T169	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T52	3		T54	8		T55	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T28	1		T191	10		T278	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T55	1		T56	12		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T29	16		T150	1		T145	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	11		T49	14		T56	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T70	15		T222	1		T188	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T53	3		T55	16		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	16		T16	1		T70	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T188	1		T144	1		T60	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	1		T143	13		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T111	1		T306	6		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T31	8		T192	11		T291	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14873	1			T1	3		T6	33		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T255	1		T285	1		T223	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	12		T162	7		T282	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T53	16		T54	12		T146	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T193	5		T284	7		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1004	1			T2	12		T13	8		T15	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	7		T56	4		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T192	9		T146	3		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T16	13		T193	10		T259	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T28	14		T31	3		T169	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T54	7		T55	5		T31	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T28	13		T191	8		T101	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T163	11		T96	8		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T29	15		T145	11		T158	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	11		T49	11		T56	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T70	11		T222	2		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T55	19		T42	2		T192	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	11		T16	12		T70	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T188	7		T144	1		T60	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	1		T58	7		T272	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T111	3		T306	2		T224	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T31	9		T192	10		T291	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T52	1		T53	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T255	10		T285	11		T223	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T148	10		T337	1		T111	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T31	8		T58	1		T179	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T307	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T294	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	11		T53	1		T179	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T53	15		T255	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	1		T160	3		T96	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	12		T33	8		T186	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T193	4		T257	1		T46	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T192	9		T256	1		T265	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	3		T12	8		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T195	1		T28	1		T31	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T31	4		T58	11		T146	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T28	1		T278	2		T271	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T52	3		T54	8		T55	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T150	1		T191	10		T145	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	11		T49	14		T149	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T70	15		T29	16		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T53	3		T55	16		T56	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T189	11		T282	3		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T188	1		T144	1		T60	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1638	1			T1	1		T2	1		T3	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14833	1			T1	3		T6	33		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T111	3		T306	2		T224	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T31	9		T58	7		T98	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T307	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	12		T53	11		T162	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T53	16		T255	10		T146	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T102	5		T154	10		T258	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T54	12		T186	1		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T193	5		T257	2		T284	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T192	9		T146	3		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	7		T16	13		T56	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T28	14		T31	3		T169	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T31	3		T58	12		T146	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T28	13		T101	4		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T54	7		T55	5		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T191	8		T145	11		T338	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	11		T49	11		T163	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T70	11		T29	15		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T55	19		T56	8		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T189	9		T102	9		T309	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T188	7		T144	1		T60	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1080	1			T1	1		T2	12		T12	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	1		T52	1		T60	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	13		T179	1		T162	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T53	17		T54	13		T150	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T45	1		T193	7		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1324	1			T2	13		T3	2		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	8		T56	5		T169	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T195	1		T192	10		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	3		T16	14		T193	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T28	15		T31	4		T169	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T52	1		T54	8		T55	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T28	14		T191	9		T278	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T55	1		T56	1		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T29	16		T150	1		T145	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	12		T49	12		T56	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T70	12		T222	3		T188	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T53	1		T55	20		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	12		T16	13		T70	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T188	8		T144	2		T60	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	2		T143	1		T58	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T111	4		T306	3		T224	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T31	10		T192	11		T291	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14994	1			T1	3		T6	34		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T255	11		T285	12		T223	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	10		T179	25		T282	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T53	14		T54	11		T311	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T193	2		T160	2		T96	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1212	1			T57	10		T32	13		T33	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	7		T56	16		T46	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T192	8		T265	14		T146	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T288	15		T210	8		T22	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T31	10		T153	12		T267	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T52	2		T54	7		T55	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T191	9		T271	11		T265	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T56	11		T163	10		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T29	15		T145	7		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	10		T49	13		T56	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T70	14		T282	2		T159	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T53	2		T55	15		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	15		T70	12		T189	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T60	9		T158	8		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T143	12		T179	15		T61	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T306	5		T339	2		T273	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T31	7		T192	10		T291	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T282	9		T194	9		T229	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T223	2		T153	12		T340	19

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T148	1		T337	1		T111	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T31	10		T58	8		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T307	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T294	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	13		T53	12		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T53	17		T255	11		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	1		T160	1		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T54	13		T33	1		T186	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T193	7		T257	3		T46	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T192	10		T256	1		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	3		T12	8		T16	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T195	1		T28	15		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T31	4		T58	13		T146	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T28	14		T278	2		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T52	1		T54	8		T55	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T150	1		T191	9		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	12		T49	12		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T70	12		T29	16		T222	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T53	1		T55	20		T56	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T189	10		T282	1		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T188	8		T144	2		T60	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1424	1			T1	2		T2	13		T3	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14918	1			T1	3		T6	34		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T148	9		T306	5		T310	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T31	7		T179	1		T61	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T307	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	10		T179	25		T282	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T53	14		T223	2		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T160	2		T96	5		T102	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T54	11		T33	7		T186	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T193	2		T46	1		T324	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T192	8		T265	14		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	7		T56	16		T161	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T31	10		T153	12		T267	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T31	3		T58	10		T146	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T271	11		T265	10		T101	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T52	2		T54	7		T55	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T191	9		T145	7		T180	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	10		T49	13		T149	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T70	14		T29	15		T158	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T53	2		T55	15		T56	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T189	10		T282	2		T102	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T60	9		T158	8		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1294	1			T12	15		T57	10		T70	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19565

1

T1

5

T2

13

T3

2

auto[1]

auto[0]

3979

1

T12

32

T14

10

T49

13