Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.54


Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T795 /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3855814363 Aug 13 06:03:09 PM PDT 24 Aug 13 06:03:23 PM PDT 24 4340857652 ps
T796 /workspace/coverage/default/27.adc_ctrl_filters_wakeup.765717032 Aug 13 06:04:24 PM PDT 24 Aug 13 06:11:38 PM PDT 24 189239494959 ps
T797 /workspace/coverage/default/12.adc_ctrl_alert_test.3697178482 Aug 13 06:02:06 PM PDT 24 Aug 13 06:02:07 PM PDT 24 309794336 ps
T798 /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1194325366 Aug 13 06:00:44 PM PDT 24 Aug 13 06:00:50 PM PDT 24 6585532017 ps
T123 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.17354977 Aug 13 05:54:26 PM PDT 24 Aug 13 05:54:28 PM PDT 24 479103452 ps
T799 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.262297024 Aug 13 05:54:46 PM PDT 24 Aug 13 05:54:47 PM PDT 24 324356394 ps
T74 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3142403469 Aug 13 05:54:19 PM PDT 24 Aug 13 05:54:21 PM PDT 24 330725116 ps
T800 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4230197785 Aug 13 05:54:05 PM PDT 24 Aug 13 05:54:06 PM PDT 24 474959399 ps
T124 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1885954162 Aug 13 05:54:08 PM PDT 24 Aug 13 05:54:10 PM PDT 24 502542918 ps
T801 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.4074118587 Aug 13 05:55:00 PM PDT 24 Aug 13 05:55:02 PM PDT 24 465907035 ps
T75 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.184031137 Aug 13 05:54:39 PM PDT 24 Aug 13 05:54:42 PM PDT 24 613472311 ps
T76 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2036865586 Aug 13 05:54:24 PM PDT 24 Aug 13 05:54:26 PM PDT 24 602588439 ps
T802 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2893516502 Aug 13 05:54:55 PM PDT 24 Aug 13 05:54:56 PM PDT 24 298190257 ps
T803 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4178896735 Aug 13 05:54:26 PM PDT 24 Aug 13 05:54:27 PM PDT 24 475617664 ps
T88 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2548353995 Aug 13 05:54:36 PM PDT 24 Aug 13 05:54:37 PM PDT 24 733640956 ps
T141 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2378478781 Aug 13 05:54:12 PM PDT 24 Aug 13 05:54:17 PM PDT 24 1359713125 ps
T804 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.910529085 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:29 PM PDT 24 511637424 ps
T805 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3772069740 Aug 13 05:54:56 PM PDT 24 Aug 13 05:54:57 PM PDT 24 496626825 ps
T806 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3062897331 Aug 13 05:54:45 PM PDT 24 Aug 13 05:54:46 PM PDT 24 513621232 ps
T67 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.622977829 Aug 13 05:54:47 PM PDT 24 Aug 13 05:55:08 PM PDT 24 5235915464 ps
T93 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3040671563 Aug 13 05:54:30 PM PDT 24 Aug 13 05:54:31 PM PDT 24 456281546 ps
T80 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.956190645 Aug 13 05:54:10 PM PDT 24 Aug 13 05:54:14 PM PDT 24 566262542 ps
T68 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.909871847 Aug 13 05:54:19 PM PDT 24 Aug 13 05:55:46 PM PDT 24 26346945214 ps
T807 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2837288448 Aug 13 05:54:45 PM PDT 24 Aug 13 05:54:46 PM PDT 24 430537299 ps
T125 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1838127966 Aug 13 05:54:19 PM PDT 24 Aug 13 05:54:20 PM PDT 24 593049427 ps
T71 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2396026420 Aug 13 05:54:21 PM PDT 24 Aug 13 05:54:32 PM PDT 24 4131246852 ps
T94 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2698138204 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:29 PM PDT 24 559595953 ps
T808 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.923356437 Aug 13 05:54:44 PM PDT 24 Aug 13 05:54:45 PM PDT 24 535169079 ps
T809 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1613518546 Aug 13 05:54:45 PM PDT 24 Aug 13 05:54:46 PM PDT 24 452524142 ps
T810 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2203516121 Aug 13 05:54:42 PM PDT 24 Aug 13 05:54:43 PM PDT 24 528113720 ps
T87 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.480354385 Aug 13 05:54:29 PM PDT 24 Aug 13 05:54:31 PM PDT 24 514274479 ps
T126 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.843088042 Aug 13 05:54:34 PM PDT 24 Aug 13 05:54:36 PM PDT 24 328117459 ps
T72 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1538065443 Aug 13 05:54:16 PM PDT 24 Aug 13 05:54:35 PM PDT 24 8008835917 ps
T81 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2528593368 Aug 13 05:54:21 PM PDT 24 Aug 13 05:54:23 PM PDT 24 460691281 ps
T811 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2495623024 Aug 13 05:54:57 PM PDT 24 Aug 13 05:54:58 PM PDT 24 397566566 ps
T812 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3529884077 Aug 13 05:54:54 PM PDT 24 Aug 13 05:54:55 PM PDT 24 467224768 ps
T85 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3467640181 Aug 13 05:54:06 PM PDT 24 Aug 13 05:54:07 PM PDT 24 604764890 ps
T84 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1470210701 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:30 PM PDT 24 430251314 ps
T73 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4270859325 Aug 13 05:54:27 PM PDT 24 Aug 13 05:54:31 PM PDT 24 4018381463 ps
T813 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.966321956 Aug 13 05:54:21 PM PDT 24 Aug 13 05:54:22 PM PDT 24 288893998 ps
T127 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2149776317 Aug 13 05:54:30 PM PDT 24 Aug 13 05:54:32 PM PDT 24 501438252 ps
T142 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.193694692 Aug 13 05:54:16 PM PDT 24 Aug 13 05:54:18 PM PDT 24 842428199 ps
T814 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1720311467 Aug 13 05:54:15 PM PDT 24 Aug 13 05:54:17 PM PDT 24 304099365 ps
T362 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3628712206 Aug 13 05:54:06 PM PDT 24 Aug 13 05:54:17 PM PDT 24 4545658603 ps
T815 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2459035325 Aug 13 05:54:46 PM PDT 24 Aug 13 05:54:47 PM PDT 24 453105985 ps
T816 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4194931557 Aug 13 05:54:10 PM PDT 24 Aug 13 05:54:12 PM PDT 24 667595266 ps
T77 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3288218861 Aug 13 05:54:09 PM PDT 24 Aug 13 05:54:20 PM PDT 24 4282684714 ps
T69 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2318102556 Aug 13 05:54:11 PM PDT 24 Aug 13 05:54:16 PM PDT 24 2461134394 ps
T86 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3789392535 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:31 PM PDT 24 782222843 ps
T817 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.346526724 Aug 13 05:54:48 PM PDT 24 Aug 13 05:54:49 PM PDT 24 652403801 ps
T818 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2738130523 Aug 13 05:54:56 PM PDT 24 Aug 13 05:54:58 PM PDT 24 451232569 ps
T128 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.373774505 Aug 13 05:54:29 PM PDT 24 Aug 13 05:54:30 PM PDT 24 552220360 ps
T138 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2664236753 Aug 13 05:54:08 PM PDT 24 Aug 13 05:54:13 PM PDT 24 5034064840 ps
T819 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2273441491 Aug 13 05:54:11 PM PDT 24 Aug 13 05:54:42 PM PDT 24 26443935079 ps
T820 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.54749835 Aug 13 05:54:26 PM PDT 24 Aug 13 05:54:27 PM PDT 24 341589207 ps
T821 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3000046517 Aug 13 05:54:27 PM PDT 24 Aug 13 05:54:28 PM PDT 24 444877869 ps
T822 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1182566430 Aug 13 05:54:54 PM PDT 24 Aug 13 05:54:55 PM PDT 24 575398369 ps
T823 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.487431938 Aug 13 05:54:27 PM PDT 24 Aug 13 05:54:29 PM PDT 24 333784400 ps
T129 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.294586678 Aug 13 05:54:13 PM PDT 24 Aug 13 05:54:18 PM PDT 24 986492777 ps
T139 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1693730406 Aug 13 05:54:03 PM PDT 24 Aug 13 05:54:05 PM PDT 24 427714292 ps
T824 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.904020082 Aug 13 05:54:34 PM PDT 24 Aug 13 05:54:37 PM PDT 24 934089915 ps
T361 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4072637767 Aug 13 05:54:36 PM PDT 24 Aug 13 05:54:40 PM PDT 24 4861446660 ps
T825 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3371275475 Aug 13 05:54:07 PM PDT 24 Aug 13 05:54:09 PM PDT 24 755827038 ps
T140 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1230952788 Aug 13 05:54:10 PM PDT 24 Aug 13 05:54:11 PM PDT 24 427593541 ps
T826 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3946499961 Aug 13 05:54:07 PM PDT 24 Aug 13 05:54:53 PM PDT 24 27191285168 ps
T827 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1342987368 Aug 13 05:54:38 PM PDT 24 Aug 13 05:54:39 PM PDT 24 390441989 ps
T130 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3690713649 Aug 13 05:54:26 PM PDT 24 Aug 13 05:54:27 PM PDT 24 344024481 ps
T828 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1756013541 Aug 13 05:54:38 PM PDT 24 Aug 13 05:54:43 PM PDT 24 2089893016 ps
T829 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3239179728 Aug 13 05:54:11 PM PDT 24 Aug 13 05:54:12 PM PDT 24 456313477 ps
T830 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4166088907 Aug 13 05:54:10 PM PDT 24 Aug 13 05:54:11 PM PDT 24 411165799 ps
T831 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.357564082 Aug 13 05:54:38 PM PDT 24 Aug 13 05:54:46 PM PDT 24 3845138339 ps
T832 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2191571897 Aug 13 05:54:56 PM PDT 24 Aug 13 05:54:57 PM PDT 24 308902764 ps
T833 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2794953227 Aug 13 05:54:19 PM PDT 24 Aug 13 05:54:21 PM PDT 24 460330569 ps
T363 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2404998450 Aug 13 05:54:11 PM PDT 24 Aug 13 05:54:15 PM PDT 24 9980018086 ps
T834 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4190584531 Aug 13 05:54:48 PM PDT 24 Aug 13 05:54:49 PM PDT 24 516690854 ps
T835 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.991341351 Aug 13 05:54:20 PM PDT 24 Aug 13 05:54:37 PM PDT 24 8546865220 ps
T836 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4110795477 Aug 13 05:54:20 PM PDT 24 Aug 13 05:54:24 PM PDT 24 484831686 ps
T837 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3194585518 Aug 13 05:54:20 PM PDT 24 Aug 13 05:54:21 PM PDT 24 396918219 ps
T838 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.333616481 Aug 13 05:54:19 PM PDT 24 Aug 13 05:54:30 PM PDT 24 2930549099 ps
T839 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2067719825 Aug 13 05:54:46 PM PDT 24 Aug 13 05:54:48 PM PDT 24 496121509 ps
T840 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3500420758 Aug 13 05:54:25 PM PDT 24 Aug 13 05:54:41 PM PDT 24 4607024567 ps
T841 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.680120664 Aug 13 05:54:37 PM PDT 24 Aug 13 05:54:38 PM PDT 24 531662511 ps
T842 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2854945896 Aug 13 05:54:46 PM PDT 24 Aug 13 05:54:47 PM PDT 24 547540466 ps
T843 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3611446180 Aug 13 05:54:25 PM PDT 24 Aug 13 05:54:27 PM PDT 24 373276475 ps
T131 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2354885819 Aug 13 05:54:29 PM PDT 24 Aug 13 05:54:30 PM PDT 24 409943603 ps
T844 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4081961143 Aug 13 05:54:55 PM PDT 24 Aug 13 05:54:57 PM PDT 24 311257648 ps
T845 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.719458029 Aug 13 05:54:46 PM PDT 24 Aug 13 05:54:47 PM PDT 24 381785733 ps
T846 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.617760067 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:31 PM PDT 24 576741069 ps
T847 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.448413882 Aug 13 05:54:45 PM PDT 24 Aug 13 05:54:46 PM PDT 24 458086339 ps
T848 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3944281802 Aug 13 05:54:27 PM PDT 24 Aug 13 05:54:34 PM PDT 24 4365138305 ps
T849 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2995869132 Aug 13 05:54:29 PM PDT 24 Aug 13 05:54:31 PM PDT 24 529371338 ps
T850 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1934362068 Aug 13 05:54:47 PM PDT 24 Aug 13 05:54:48 PM PDT 24 393753722 ps
T364 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3237137545 Aug 13 05:54:09 PM PDT 24 Aug 13 05:54:13 PM PDT 24 4126350942 ps
T132 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1054596088 Aug 13 05:54:19 PM PDT 24 Aug 13 05:54:21 PM PDT 24 375976237 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.781746004 Aug 13 05:54:22 PM PDT 24 Aug 13 05:54:25 PM PDT 24 1022048272 ps
T852 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3498729316 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:31 PM PDT 24 2443098415 ps
T853 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3945922421 Aug 13 05:54:29 PM PDT 24 Aug 13 05:54:30 PM PDT 24 515717356 ps
T854 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.274776099 Aug 13 05:54:30 PM PDT 24 Aug 13 05:54:31 PM PDT 24 627707414 ps
T855 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1876077540 Aug 13 05:54:29 PM PDT 24 Aug 13 05:54:41 PM PDT 24 4440628487 ps
T856 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3353852976 Aug 13 05:54:56 PM PDT 24 Aug 13 05:54:57 PM PDT 24 398689463 ps
T857 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3555084330 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:35 PM PDT 24 8403624970 ps
T858 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1190800077 Aug 13 05:54:37 PM PDT 24 Aug 13 05:54:39 PM PDT 24 405729677 ps
T859 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3672181963 Aug 13 05:54:13 PM PDT 24 Aug 13 05:54:15 PM PDT 24 834196862 ps
T860 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.4038658625 Aug 13 05:54:38 PM PDT 24 Aug 13 05:55:00 PM PDT 24 8351882937 ps
T861 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1858107800 Aug 13 05:54:18 PM PDT 24 Aug 13 05:54:19 PM PDT 24 491863694 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1709224386 Aug 13 05:54:09 PM PDT 24 Aug 13 05:54:10 PM PDT 24 491608926 ps
T863 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3164817384 Aug 13 05:54:10 PM PDT 24 Aug 13 05:54:12 PM PDT 24 600807490 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.766504458 Aug 13 05:54:38 PM PDT 24 Aug 13 05:54:47 PM PDT 24 4534754293 ps
T865 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2045922047 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:30 PM PDT 24 628207558 ps
T866 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.433849442 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:49 PM PDT 24 8447978181 ps
T867 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1405130031 Aug 13 05:54:26 PM PDT 24 Aug 13 05:54:29 PM PDT 24 427121803 ps
T868 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2080825045 Aug 13 05:54:26 PM PDT 24 Aug 13 05:54:33 PM PDT 24 8554016913 ps
T869 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3648610298 Aug 13 05:54:07 PM PDT 24 Aug 13 05:54:08 PM PDT 24 489871072 ps
T133 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.504548996 Aug 13 05:54:13 PM PDT 24 Aug 13 05:54:14 PM PDT 24 1214651103 ps
T870 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.691089245 Aug 13 05:54:29 PM PDT 24 Aug 13 05:54:31 PM PDT 24 520929071 ps
T134 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.413805621 Aug 13 05:54:11 PM PDT 24 Aug 13 05:54:57 PM PDT 24 47917187469 ps
T871 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4077752628 Aug 13 05:54:09 PM PDT 24 Aug 13 05:54:10 PM PDT 24 464334102 ps
T872 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.253609854 Aug 13 05:54:30 PM PDT 24 Aug 13 05:54:32 PM PDT 24 295424845 ps
T873 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1850873584 Aug 13 05:54:19 PM PDT 24 Aug 13 05:54:23 PM PDT 24 5085000568 ps
T135 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.541417934 Aug 13 05:54:08 PM PDT 24 Aug 13 05:54:12 PM PDT 24 2302033114 ps
T874 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2176480187 Aug 13 05:54:26 PM PDT 24 Aug 13 05:54:32 PM PDT 24 9166565301 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1898170450 Aug 13 05:54:02 PM PDT 24 Aug 13 05:54:05 PM PDT 24 346485294 ps
T876 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.842154872 Aug 13 05:54:19 PM PDT 24 Aug 13 05:54:21 PM PDT 24 586715331 ps
T877 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2132130848 Aug 13 05:54:54 PM PDT 24 Aug 13 05:54:55 PM PDT 24 648422666 ps
T878 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2682664758 Aug 13 05:54:21 PM PDT 24 Aug 13 05:54:22 PM PDT 24 321806579 ps
T879 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3121328298 Aug 13 05:54:40 PM PDT 24 Aug 13 05:54:41 PM PDT 24 450318669 ps
T880 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3634392204 Aug 13 05:54:20 PM PDT 24 Aug 13 05:54:27 PM PDT 24 4068222620 ps
T881 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4170181409 Aug 13 05:54:35 PM PDT 24 Aug 13 05:54:37 PM PDT 24 449555538 ps
T882 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.726974565 Aug 13 05:54:36 PM PDT 24 Aug 13 05:54:38 PM PDT 24 442387144 ps
T883 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3407537856 Aug 13 05:54:48 PM PDT 24 Aug 13 05:54:50 PM PDT 24 374004926 ps
T884 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.136753710 Aug 13 05:54:43 PM PDT 24 Aug 13 05:54:45 PM PDT 24 522146279 ps
T885 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1516954229 Aug 13 05:54:16 PM PDT 24 Aug 13 05:54:17 PM PDT 24 761857058 ps
T886 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2499616981 Aug 13 05:54:27 PM PDT 24 Aug 13 05:54:35 PM PDT 24 2388104512 ps
T887 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.928577158 Aug 13 05:54:11 PM PDT 24 Aug 13 05:54:15 PM PDT 24 1017720326 ps
T136 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.47788840 Aug 13 05:54:38 PM PDT 24 Aug 13 05:54:40 PM PDT 24 407881742 ps
T888 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2697718436 Aug 13 05:54:39 PM PDT 24 Aug 13 05:54:48 PM PDT 24 8775465819 ps
T889 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1561445507 Aug 13 05:54:54 PM PDT 24 Aug 13 05:54:55 PM PDT 24 508842788 ps
T890 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.702591984 Aug 13 05:54:20 PM PDT 24 Aug 13 05:54:22 PM PDT 24 568711445 ps
T891 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2065677477 Aug 13 05:54:36 PM PDT 24 Aug 13 05:54:46 PM PDT 24 4948847360 ps
T892 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3620515161 Aug 13 05:54:20 PM PDT 24 Aug 13 05:54:22 PM PDT 24 481362784 ps
T137 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1377460746 Aug 13 05:54:13 PM PDT 24 Aug 13 05:54:16 PM PDT 24 488927166 ps
T893 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1177146663 Aug 13 05:54:09 PM PDT 24 Aug 13 05:54:18 PM PDT 24 4292229786 ps
T894 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3254727113 Aug 13 05:54:27 PM PDT 24 Aug 13 05:54:30 PM PDT 24 535240445 ps
T895 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2230871503 Aug 13 05:54:39 PM PDT 24 Aug 13 05:54:40 PM PDT 24 375382281 ps
T896 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1525299272 Aug 13 05:54:45 PM PDT 24 Aug 13 05:54:46 PM PDT 24 510768490 ps
T897 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1464605379 Aug 13 05:54:37 PM PDT 24 Aug 13 05:54:40 PM PDT 24 530375299 ps
T898 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1448763280 Aug 13 05:54:38 PM PDT 24 Aug 13 05:54:40 PM PDT 24 608291087 ps
T899 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.413495291 Aug 13 05:54:29 PM PDT 24 Aug 13 05:54:38 PM PDT 24 2527935145 ps
T900 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.189752979 Aug 13 05:54:20 PM PDT 24 Aug 13 05:54:22 PM PDT 24 858942758 ps
T901 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.188493454 Aug 13 05:54:06 PM PDT 24 Aug 13 05:54:08 PM PDT 24 1013386117 ps
T902 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1261858044 Aug 13 05:54:39 PM PDT 24 Aug 13 05:54:43 PM PDT 24 1992893797 ps
T903 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4043723868 Aug 13 05:54:27 PM PDT 24 Aug 13 05:54:30 PM PDT 24 4487129669 ps
T904 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1347964006 Aug 13 05:54:56 PM PDT 24 Aug 13 05:54:58 PM PDT 24 307464121 ps
T905 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3012961380 Aug 13 05:54:20 PM PDT 24 Aug 13 05:54:21 PM PDT 24 401299549 ps
T906 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3510524685 Aug 13 05:54:27 PM PDT 24 Aug 13 05:54:38 PM PDT 24 4471379861 ps
T907 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1254856011 Aug 13 05:54:19 PM PDT 24 Aug 13 05:54:30 PM PDT 24 3883447257 ps
T908 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3940623347 Aug 13 05:54:57 PM PDT 24 Aug 13 05:54:59 PM PDT 24 527258817 ps
T909 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.888360777 Aug 13 05:54:16 PM PDT 24 Aug 13 05:54:22 PM PDT 24 2209033968 ps
T910 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.31864095 Aug 13 05:54:39 PM PDT 24 Aug 13 05:54:42 PM PDT 24 440499051 ps
T911 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2401651474 Aug 13 05:54:30 PM PDT 24 Aug 13 05:54:47 PM PDT 24 4791439968 ps
T912 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2773229647 Aug 13 05:54:46 PM PDT 24 Aug 13 05:54:47 PM PDT 24 499258245 ps
T913 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1952425641 Aug 13 05:54:28 PM PDT 24 Aug 13 05:54:29 PM PDT 24 334469511 ps
T914 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2964706078 Aug 13 05:54:38 PM PDT 24 Aug 13 05:54:40 PM PDT 24 438411499 ps
T915 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4227091313 Aug 13 05:54:16 PM PDT 24 Aug 13 05:54:17 PM PDT 24 464246909 ps
T89 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3366041113 Aug 13 05:54:27 PM PDT 24 Aug 13 05:54:40 PM PDT 24 8302138327 ps
T916 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2850679553 Aug 13 05:54:20 PM PDT 24 Aug 13 05:54:37 PM PDT 24 4329238662 ps
T917 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1743149958 Aug 13 05:54:10 PM PDT 24 Aug 13 05:54:12 PM PDT 24 540961588 ps
T918 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1337326619 Aug 13 05:54:38 PM PDT 24 Aug 13 05:54:39 PM PDT 24 455838821 ps
T919 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1739631880 Aug 13 05:54:30 PM PDT 24 Aug 13 05:54:31 PM PDT 24 613644266 ps

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2183702464
Short name T1
Test name
Test status
Simulation time 6488396325 ps
CPU time 10.02 seconds
Started Aug 13 06:04:33 PM PDT 24
Finished Aug 13 06:04:43 PM PDT 24
Peak memory 210716 kb
Host smart-840f89ec-7cf2-4dee-bb5e-3ff0ded014d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183702464 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2183702464
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.459227051
Short name T53
Test name
Test status
Simulation time 517285066191 ps
CPU time 1096.21 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:19:00 PM PDT 24
Peak memory 202156 kb
Host smart-1393511b-2a2e-450e-a6b1-c8cab9ac672a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459227051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.459227051
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1619135969
Short name T58
Test name
Test status
Simulation time 576833141788 ps
CPU time 1312.81 seconds
Started Aug 13 06:07:57 PM PDT 24
Finished Aug 13 06:29:50 PM PDT 24
Peak memory 202340 kb
Host smart-da7466a3-54d1-4706-bd22-9861c292ed53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619135969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1619135969
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2627522760
Short name T12
Test name
Test status
Simulation time 500594133759 ps
CPU time 574.11 seconds
Started Aug 13 06:05:54 PM PDT 24
Finished Aug 13 06:15:28 PM PDT 24
Peak memory 202164 kb
Host smart-c1d30c09-be6d-4934-821f-50756bdc3672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627522760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2627522760
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3904974054
Short name T284
Test name
Test status
Simulation time 465835375781 ps
CPU time 1338.04 seconds
Started Aug 13 06:01:44 PM PDT 24
Finished Aug 13 06:24:02 PM PDT 24
Peak memory 210580 kb
Host smart-c96cccf2-6f72-4b93-a3c9-4de7eed8f5a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904974054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3904974054
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3809100772
Short name T31
Test name
Test status
Simulation time 486873518962 ps
CPU time 908.72 seconds
Started Aug 13 06:05:37 PM PDT 24
Finished Aug 13 06:20:46 PM PDT 24
Peak memory 202132 kb
Host smart-c168777d-553c-4bbc-b0d3-2d7ebd370496
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809100772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3809100772
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3762725484
Short name T146
Test name
Test status
Simulation time 612881311886 ps
CPU time 145.81 seconds
Started Aug 13 06:06:13 PM PDT 24
Finished Aug 13 06:08:39 PM PDT 24
Peak memory 202100 kb
Host smart-bee49ca0-464b-4c32-a858-f3cf1ab48339
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762725484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3762725484
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.4287314441
Short name T19
Test name
Test status
Simulation time 6204390907 ps
CPU time 8.21 seconds
Started Aug 13 06:03:37 PM PDT 24
Finished Aug 13 06:03:45 PM PDT 24
Peak memory 210504 kb
Host smart-7a147558-5c11-41d2-bb56-624bcb546f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287314441 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.4287314441
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1092967616
Short name T65
Test name
Test status
Simulation time 691486817586 ps
CPU time 1043.52 seconds
Started Aug 13 06:01:14 PM PDT 24
Finished Aug 13 06:18:38 PM PDT 24
Peak memory 210580 kb
Host smart-3d8d9abc-73c1-423b-97c6-381fd866c6de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092967616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1092967616
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2915927052
Short name T4
Test name
Test status
Simulation time 161835974981 ps
CPU time 98.96 seconds
Started Aug 13 06:03:55 PM PDT 24
Finished Aug 13 06:05:34 PM PDT 24
Peak memory 202088 kb
Host smart-6b7f33d5-bfc1-4ab9-b8c2-ee47514ed231
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915927052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2915927052
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1147022151
Short name T282
Test name
Test status
Simulation time 513522643778 ps
CPU time 987.27 seconds
Started Aug 13 06:05:06 PM PDT 24
Finished Aug 13 06:21:33 PM PDT 24
Peak memory 202092 kb
Host smart-ff921bb6-b723-4b74-a014-efbe585e2719
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147022151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1147022151
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.184031137
Short name T75
Test name
Test status
Simulation time 613472311 ps
CPU time 3.03 seconds
Started Aug 13 05:54:39 PM PDT 24
Finished Aug 13 05:54:42 PM PDT 24
Peak memory 209320 kb
Host smart-856c0bd5-8145-478e-8642-61b91e971a37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184031137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.184031137
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2666456355
Short name T158
Test name
Test status
Simulation time 550298592476 ps
CPU time 1228.04 seconds
Started Aug 13 06:05:38 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 202156 kb
Host smart-afc3bdb8-ec65-49fa-a816-93c669e05606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666456355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2666456355
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3474860713
Short name T54
Test name
Test status
Simulation time 350949770915 ps
CPU time 394.5 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:07:50 PM PDT 24
Peak memory 202168 kb
Host smart-dde2c910-68d2-4dd3-8623-be1d68852041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474860713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3474860713
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1171285050
Short name T17
Test name
Test status
Simulation time 8206293436 ps
CPU time 16.73 seconds
Started Aug 13 06:00:45 PM PDT 24
Finished Aug 13 06:01:02 PM PDT 24
Peak memory 218472 kb
Host smart-ec14bd66-46f9-42c6-b7f1-fc470294f6d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171285050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1171285050
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.673296586
Short name T153
Test name
Test status
Simulation time 731875577857 ps
CPU time 817.96 seconds
Started Aug 13 06:06:04 PM PDT 24
Finished Aug 13 06:19:43 PM PDT 24
Peak memory 202116 kb
Host smart-7750d6d6-a530-4f4c-a070-c6a72b86b63f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673296586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
673296586
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2631216729
Short name T102
Test name
Test status
Simulation time 630810415110 ps
CPU time 1004.41 seconds
Started Aug 13 06:02:31 PM PDT 24
Finished Aug 13 06:19:16 PM PDT 24
Peak memory 202140 kb
Host smart-7c05bda6-d1e4-40fb-933b-d8ba1f3d6562
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631216729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2631216729
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.831865873
Short name T159
Test name
Test status
Simulation time 535876690887 ps
CPU time 1164.76 seconds
Started Aug 13 06:02:44 PM PDT 24
Finished Aug 13 06:22:09 PM PDT 24
Peak memory 202108 kb
Host smart-901e45fe-420c-4a21-9a06-456d9c23be30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831865873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.831865873
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3285333941
Short name T192
Test name
Test status
Simulation time 483086959475 ps
CPU time 278.8 seconds
Started Aug 13 06:03:38 PM PDT 24
Finished Aug 13 06:08:17 PM PDT 24
Peak memory 202064 kb
Host smart-c445743a-907b-4823-a0ca-66a72dda429e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285333941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3285333941
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.909871847
Short name T68
Test name
Test status
Simulation time 26346945214 ps
CPU time 86.76 seconds
Started Aug 13 05:54:19 PM PDT 24
Finished Aug 13 05:55:46 PM PDT 24
Peak memory 200344 kb
Host smart-2f53358e-aa93-4104-9e7d-ec0a0c0c8650
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909871847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.909871847
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1396215446
Short name T165
Test name
Test status
Simulation time 585414986792 ps
CPU time 380.18 seconds
Started Aug 13 06:03:55 PM PDT 24
Finished Aug 13 06:10:15 PM PDT 24
Peak memory 202064 kb
Host smart-4bff1af1-bba5-4af4-a2c5-0fe4210c76a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396215446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1396215446
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.912329021
Short name T61
Test name
Test status
Simulation time 406580767411 ps
CPU time 463.17 seconds
Started Aug 13 06:04:45 PM PDT 24
Finished Aug 13 06:12:28 PM PDT 24
Peak memory 202172 kb
Host smart-f68b47a6-c12f-455a-92cf-39fc1a66c2ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912329021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.912329021
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.732571739
Short name T111
Test name
Test status
Simulation time 430246794933 ps
CPU time 779.23 seconds
Started Aug 13 06:03:52 PM PDT 24
Finished Aug 13 06:16:51 PM PDT 24
Peak memory 202380 kb
Host smart-5684a82d-7c5f-4914-919e-082df7b8b6de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732571739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
732571739
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2862841438
Short name T307
Test name
Test status
Simulation time 492719832727 ps
CPU time 911.18 seconds
Started Aug 13 06:03:01 PM PDT 24
Finished Aug 13 06:18:12 PM PDT 24
Peak memory 202120 kb
Host smart-15c98192-c279-40fa-ab6f-321f262774c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862841438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2862841438
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4207632202
Short name T188
Test name
Test status
Simulation time 324592876910 ps
CPU time 163.66 seconds
Started Aug 13 06:05:22 PM PDT 24
Finished Aug 13 06:08:06 PM PDT 24
Peak memory 200460 kb
Host smart-b93fdba3-5962-46f6-981f-016326546bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207632202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4207632202
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.421925960
Short name T299
Test name
Test status
Simulation time 326583835531 ps
CPU time 206.38 seconds
Started Aug 13 06:05:05 PM PDT 24
Finished Aug 13 06:08:32 PM PDT 24
Peak memory 202156 kb
Host smart-f66bc4ed-4616-4c33-8676-8d761d4cb0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421925960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.421925960
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.843499133
Short name T55
Test name
Test status
Simulation time 501685386447 ps
CPU time 414.08 seconds
Started Aug 13 06:01:26 PM PDT 24
Finished Aug 13 06:08:20 PM PDT 24
Peak memory 202032 kb
Host smart-64ce32c5-541b-435f-81db-e1fb8a745669
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843499133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.843499133
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3543295972
Short name T225
Test name
Test status
Simulation time 490325405616 ps
CPU time 140.21 seconds
Started Aug 13 06:07:25 PM PDT 24
Finished Aug 13 06:09:46 PM PDT 24
Peak memory 202200 kb
Host smart-aa4b0d46-ea7a-403a-b384-20ae123c549e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543295972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3543295972
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.756346940
Short name T56
Test name
Test status
Simulation time 538239393756 ps
CPU time 570.27 seconds
Started Aug 13 06:03:53 PM PDT 24
Finished Aug 13 06:13:23 PM PDT 24
Peak memory 202160 kb
Host smart-f24e5ede-1c6b-427a-9906-d9a96f83d446
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756346940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.756346940
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3071615588
Short name T11
Test name
Test status
Simulation time 8681010337 ps
CPU time 14.38 seconds
Started Aug 13 06:04:40 PM PDT 24
Finished Aug 13 06:04:54 PM PDT 24
Peak memory 210736 kb
Host smart-8b47ff53-be06-4583-9c56-1342f75cbdd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071615588 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3071615588
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1369937525
Short name T83
Test name
Test status
Simulation time 381711081 ps
CPU time 1.49 seconds
Started Aug 13 06:03:03 PM PDT 24
Finished Aug 13 06:03:04 PM PDT 24
Peak memory 201976 kb
Host smart-d7b49b45-6cad-4bfc-a0cf-9ccf969d3a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369937525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1369937525
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3951582424
Short name T280
Test name
Test status
Simulation time 159971699888 ps
CPU time 97.43 seconds
Started Aug 13 06:05:28 PM PDT 24
Finished Aug 13 06:07:05 PM PDT 24
Peak memory 202096 kb
Host smart-75b1fa1e-cb56-424f-a076-14e4ee569131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951582424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3951582424
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2396026420
Short name T71
Test name
Test status
Simulation time 4131246852 ps
CPU time 10.98 seconds
Started Aug 13 05:54:21 PM PDT 24
Finished Aug 13 05:54:32 PM PDT 24
Peak memory 201228 kb
Host smart-a0280634-dc9d-4d17-84de-535a2fe90c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396026420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2396026420
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.698992515
Short name T145
Test name
Test status
Simulation time 175063727718 ps
CPU time 400.19 seconds
Started Aug 13 06:06:38 PM PDT 24
Finished Aug 13 06:13:18 PM PDT 24
Peak memory 202160 kb
Host smart-d3f3f14c-d9be-40b1-b6f2-12b4a9109714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698992515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.698992515
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.620200205
Short name T186
Test name
Test status
Simulation time 176341681342 ps
CPU time 395.54 seconds
Started Aug 13 06:07:10 PM PDT 24
Finished Aug 13 06:13:45 PM PDT 24
Peak memory 202128 kb
Host smart-e11aba62-1ebe-4a09-8af6-5035daf42bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620200205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.620200205
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1419713003
Short name T197
Test name
Test status
Simulation time 356418706556 ps
CPU time 810.87 seconds
Started Aug 13 06:07:38 PM PDT 24
Finished Aug 13 06:21:09 PM PDT 24
Peak memory 202140 kb
Host smart-2ef59524-2933-4b7c-89c8-6583e1a652b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419713003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1419713003
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2077984045
Short name T229
Test name
Test status
Simulation time 340654012099 ps
CPU time 1164.26 seconds
Started Aug 13 06:05:46 PM PDT 24
Finished Aug 13 06:25:10 PM PDT 24
Peak memory 210440 kb
Host smart-4018f680-7b64-4ed2-ae7d-5d7745ce0576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077984045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2077984045
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2902301349
Short name T265
Test name
Test status
Simulation time 523930241937 ps
CPU time 1277.1 seconds
Started Aug 13 06:01:04 PM PDT 24
Finished Aug 13 06:22:22 PM PDT 24
Peak memory 202160 kb
Host smart-b60b4fe4-b648-454c-8e05-49caada6815f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902301349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2902301349
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1867736157
Short name T266
Test name
Test status
Simulation time 558324472162 ps
CPU time 1283.73 seconds
Started Aug 13 06:04:12 PM PDT 24
Finished Aug 13 06:25:36 PM PDT 24
Peak memory 202172 kb
Host smart-7bdf5dc0-d617-4e44-a990-004dadec120a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867736157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1867736157
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.116774953
Short name T325
Test name
Test status
Simulation time 160580603684 ps
CPU time 36.99 seconds
Started Aug 13 06:04:47 PM PDT 24
Finished Aug 13 06:05:24 PM PDT 24
Peak memory 202060 kb
Host smart-b2f08e96-6e85-46ee-ba65-5336fef7b993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116774953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.116774953
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2323781941
Short name T95
Test name
Test status
Simulation time 490345170834 ps
CPU time 274.06 seconds
Started Aug 13 06:01:47 PM PDT 24
Finished Aug 13 06:06:21 PM PDT 24
Peak memory 202168 kb
Host smart-998c9e68-2ee4-4544-8852-0ff199e8f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323781941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2323781941
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.300209173
Short name T334
Test name
Test status
Simulation time 486262880538 ps
CPU time 483.46 seconds
Started Aug 13 06:03:06 PM PDT 24
Finished Aug 13 06:11:09 PM PDT 24
Peak memory 202036 kb
Host smart-42e17eb5-13ab-4de3-987c-343d850d01fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300209173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.300209173
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.404871887
Short name T275
Test name
Test status
Simulation time 493130868797 ps
CPU time 553 seconds
Started Aug 13 06:00:54 PM PDT 24
Finished Aug 13 06:10:07 PM PDT 24
Peak memory 202148 kb
Host smart-6e3a2376-3a23-436b-8f02-6b9f20f6ca14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404871887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.404871887
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.397096820
Short name T258
Test name
Test status
Simulation time 354295836263 ps
CPU time 823.96 seconds
Started Aug 13 06:07:35 PM PDT 24
Finished Aug 13 06:21:19 PM PDT 24
Peak memory 202284 kb
Host smart-1e127901-cc9a-494a-9778-d4cd5046785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397096820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.397096820
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3598008899
Short name T210
Test name
Test status
Simulation time 374460290046 ps
CPU time 831.07 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:14:35 PM PDT 24
Peak memory 202156 kb
Host smart-9b8f0a78-ddf0-4b2c-8653-ddfaea123d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598008899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3598008899
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4163194225
Short name T371
Test name
Test status
Simulation time 170108216181 ps
CPU time 96.93 seconds
Started Aug 13 06:01:45 PM PDT 24
Finished Aug 13 06:03:22 PM PDT 24
Peak memory 202024 kb
Host smart-42f5dbbe-ad46-44b1-942c-9fc376ef054f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163194225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.4163194225
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.155513279
Short name T199
Test name
Test status
Simulation time 509382865234 ps
CPU time 328.85 seconds
Started Aug 13 06:04:22 PM PDT 24
Finished Aug 13 06:09:51 PM PDT 24
Peak memory 202156 kb
Host smart-63659696-8a79-4e8b-979c-554a75991417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155513279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.155513279
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1451832835
Short name T315
Test name
Test status
Simulation time 454544209172 ps
CPU time 456.49 seconds
Started Aug 13 06:01:34 PM PDT 24
Finished Aug 13 06:09:11 PM PDT 24
Peak memory 210584 kb
Host smart-137c3521-c0d8-44c5-b25d-416c1b5a149d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451832835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1451832835
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1693730406
Short name T139
Test name
Test status
Simulation time 427714292 ps
CPU time 1.79 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:54:05 PM PDT 24
Peak memory 200880 kb
Host smart-2d1c475c-badb-4e8b-9f14-f261d6dbebce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693730406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1693730406
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3104535747
Short name T104
Test name
Test status
Simulation time 8400286883 ps
CPU time 14.21 seconds
Started Aug 13 06:01:55 PM PDT 24
Finished Aug 13 06:02:09 PM PDT 24
Peak memory 210800 kb
Host smart-8a4f367e-6f3c-48da-983f-e84402d142dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104535747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3104535747
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1824104292
Short name T302
Test name
Test status
Simulation time 330754957585 ps
CPU time 83.45 seconds
Started Aug 13 06:02:05 PM PDT 24
Finished Aug 13 06:03:29 PM PDT 24
Peak memory 202132 kb
Host smart-ecdfdb9d-a8a6-4e7e-9ac4-4a2179e7148b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824104292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1824104292
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1124710050
Short name T294
Test name
Test status
Simulation time 496346414652 ps
CPU time 175.21 seconds
Started Aug 13 06:03:07 PM PDT 24
Finished Aug 13 06:06:02 PM PDT 24
Peak memory 202152 kb
Host smart-7e38ca4d-5914-4af9-8cd0-996e462ca5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124710050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1124710050
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2141034061
Short name T32
Test name
Test status
Simulation time 200459671727 ps
CPU time 105.09 seconds
Started Aug 13 06:00:54 PM PDT 24
Finished Aug 13 06:02:39 PM PDT 24
Peak memory 202140 kb
Host smart-a72f65bf-6085-434a-81ec-9e494ac663e7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141034061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2141034061
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2840337946
Short name T322
Test name
Test status
Simulation time 331210673986 ps
CPU time 762.3 seconds
Started Aug 13 06:03:53 PM PDT 24
Finished Aug 13 06:16:36 PM PDT 24
Peak memory 202132 kb
Host smart-4ce41487-8ee2-484b-843c-00d07f53acf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840337946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2840337946
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1115243452
Short name T327
Test name
Test status
Simulation time 493181573099 ps
CPU time 643.06 seconds
Started Aug 13 06:01:07 PM PDT 24
Finished Aug 13 06:11:50 PM PDT 24
Peak memory 202196 kb
Host smart-3d1fde71-7f3e-4719-9d0a-bfc8c98ca071
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115243452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1115243452
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.4038658625
Short name T860
Test name
Test status
Simulation time 8351882937 ps
CPU time 21.42 seconds
Started Aug 13 05:54:38 PM PDT 24
Finished Aug 13 05:55:00 PM PDT 24
Peak memory 201164 kb
Host smart-c08686bb-d769-43e2-9770-4112ffc2bc5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038658625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.4038658625
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2286623426
Short name T223
Test name
Test status
Simulation time 387726118099 ps
CPU time 902.21 seconds
Started Aug 13 06:01:47 PM PDT 24
Finished Aug 13 06:16:49 PM PDT 24
Peak memory 202152 kb
Host smart-ff8be0f5-ca7b-4392-a42f-dc6aeb3e3f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286623426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2286623426
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1740518035
Short name T276
Test name
Test status
Simulation time 370367487969 ps
CPU time 179.98 seconds
Started Aug 13 06:07:19 PM PDT 24
Finished Aug 13 06:10:19 PM PDT 24
Peak memory 202112 kb
Host smart-65492388-ea7f-4a56-bf07-44394c56a3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740518035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1740518035
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3898839942
Short name T332
Test name
Test status
Simulation time 357186516988 ps
CPU time 394.61 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:07:19 PM PDT 24
Peak memory 202136 kb
Host smart-d0340122-2235-4e8e-b6f2-16483e9aca24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898839942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3898839942
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.4191005692
Short name T354
Test name
Test status
Simulation time 160343060468 ps
CPU time 335.68 seconds
Started Aug 13 06:03:36 PM PDT 24
Finished Aug 13 06:09:12 PM PDT 24
Peak memory 202160 kb
Host smart-dcab8133-553d-4af3-ba53-d2731ac1fa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191005692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4191005692
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.296058710
Short name T101
Test name
Test status
Simulation time 371642860064 ps
CPU time 744.25 seconds
Started Aug 13 06:04:31 PM PDT 24
Finished Aug 13 06:16:55 PM PDT 24
Peak memory 202136 kb
Host smart-3ab8bc42-2f5c-45a4-93cb-94121b3bf593
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296058710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.296058710
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4285165
Short name T318
Test name
Test status
Simulation time 332777275788 ps
CPU time 706.21 seconds
Started Aug 13 06:04:59 PM PDT 24
Finished Aug 13 06:16:46 PM PDT 24
Peak memory 202184 kb
Host smart-ecac584f-5a62-40cd-aeab-8c643225e3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4285165
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3858747583
Short name T301
Test name
Test status
Simulation time 543998491171 ps
CPU time 301.59 seconds
Started Aug 13 06:05:55 PM PDT 24
Finished Aug 13 06:10:57 PM PDT 24
Peak memory 202176 kb
Host smart-7774ef40-77d1-4069-aeda-0236383f9d6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858747583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3858747583
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2322221396
Short name T273
Test name
Test status
Simulation time 374178038525 ps
CPU time 447.21 seconds
Started Aug 13 06:01:06 PM PDT 24
Finished Aug 13 06:08:33 PM PDT 24
Peak memory 202140 kb
Host smart-a4059e4e-106d-4525-8b47-40586fc4a50c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322221396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2322221396
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1870325135
Short name T304
Test name
Test status
Simulation time 166040523330 ps
CPU time 408.11 seconds
Started Aug 13 06:07:40 PM PDT 24
Finished Aug 13 06:14:28 PM PDT 24
Peak memory 202168 kb
Host smart-25a2a4e6-6937-4c32-8500-e4f5226f548d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870325135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1870325135
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.820762170
Short name T288
Test name
Test status
Simulation time 529520225799 ps
CPU time 1208.05 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:21:23 PM PDT 24
Peak memory 202200 kb
Host smart-95337919-8908-4727-8697-776dfe51b675
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820762170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.820762170
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2994999986
Short name T240
Test name
Test status
Simulation time 114596773629 ps
CPU time 385.65 seconds
Started Aug 13 06:01:24 PM PDT 24
Finished Aug 13 06:07:50 PM PDT 24
Peak memory 202428 kb
Host smart-38aea973-8a43-4d42-8b9e-22c60bff3119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994999986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2994999986
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.4214400804
Short name T308
Test name
Test status
Simulation time 360952827376 ps
CPU time 90.79 seconds
Started Aug 13 06:08:31 PM PDT 24
Finished Aug 13 06:10:02 PM PDT 24
Peak memory 202120 kb
Host smart-efe472c7-064d-47a6-97a5-b7a856f34744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214400804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.4214400804
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1431786628
Short name T238
Test name
Test status
Simulation time 109285059003 ps
CPU time 460.15 seconds
Started Aug 13 06:01:47 PM PDT 24
Finished Aug 13 06:09:28 PM PDT 24
Peak memory 202376 kb
Host smart-e2b99738-7f8c-4145-9cdb-6f89294a0eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431786628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1431786628
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3163090513
Short name T353
Test name
Test status
Simulation time 16181345485 ps
CPU time 10.91 seconds
Started Aug 13 06:01:47 PM PDT 24
Finished Aug 13 06:01:58 PM PDT 24
Peak memory 210724 kb
Host smart-29040f72-7fc5-48ae-82a1-aa1c8db27e6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163090513 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3163090513
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1557041319
Short name T298
Test name
Test status
Simulation time 332268181246 ps
CPU time 308.57 seconds
Started Aug 13 06:02:05 PM PDT 24
Finished Aug 13 06:07:14 PM PDT 24
Peak memory 202136 kb
Host smart-867cf9f9-1aa3-41f9-a9ae-a9240cee7bd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557041319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1557041319
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4117215840
Short name T731
Test name
Test status
Simulation time 91826477936 ps
CPU time 340.98 seconds
Started Aug 13 06:02:17 PM PDT 24
Finished Aug 13 06:07:58 PM PDT 24
Peak memory 202324 kb
Host smart-e7d1c88a-c9c7-4ae7-80a3-db1f8ae8401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117215840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4117215840
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.141278017
Short name T274
Test name
Test status
Simulation time 335811612869 ps
CPU time 220.27 seconds
Started Aug 13 06:02:23 PM PDT 24
Finished Aug 13 06:06:04 PM PDT 24
Peak memory 202064 kb
Host smart-53bfd38a-0a21-4e7f-bcec-ce98ef3e0e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141278017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.141278017
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.4218146049
Short name T119
Test name
Test status
Simulation time 329865386582 ps
CPU time 449.55 seconds
Started Aug 13 06:03:38 PM PDT 24
Finished Aug 13 06:11:07 PM PDT 24
Peak memory 202088 kb
Host smart-857cc6dd-f4cc-467b-adb2-f2a29bc8f32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218146049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.4218146049
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1220937133
Short name T329
Test name
Test status
Simulation time 3130846526 ps
CPU time 4.13 seconds
Started Aug 13 06:04:10 PM PDT 24
Finished Aug 13 06:04:14 PM PDT 24
Peak memory 202296 kb
Host smart-bc5c7f6d-35c5-42b0-9ea0-45f535e5fcb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220937133 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1220937133
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1321189861
Short name T293
Test name
Test status
Simulation time 486038358112 ps
CPU time 1111.58 seconds
Started Aug 13 06:04:56 PM PDT 24
Finished Aug 13 06:23:28 PM PDT 24
Peak memory 202012 kb
Host smart-b35318f4-ceee-4f86-9234-67ecbe87b879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321189861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1321189861
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.364910362
Short name T331
Test name
Test status
Simulation time 334703757713 ps
CPU time 157.83 seconds
Started Aug 13 06:07:36 PM PDT 24
Finished Aug 13 06:10:13 PM PDT 24
Peak memory 202156 kb
Host smart-81e7eeba-2187-40ad-b4ee-2b221397f1fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364910362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.364910362
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.205791846
Short name T300
Test name
Test status
Simulation time 377820754475 ps
CPU time 118.08 seconds
Started Aug 13 06:08:07 PM PDT 24
Finished Aug 13 06:10:06 PM PDT 24
Peak memory 202096 kb
Host smart-330e67c7-4e84-47c6-b02d-fbab9ce05f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205791846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
205791846
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1898170450
Short name T875
Test name
Test status
Simulation time 346485294 ps
CPU time 2.36 seconds
Started Aug 13 05:54:02 PM PDT 24
Finished Aug 13 05:54:05 PM PDT 24
Peak memory 201156 kb
Host smart-f634602c-7b3d-4750-aef1-c9fd491988f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898170450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1898170450
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3288218861
Short name T77
Test name
Test status
Simulation time 4282684714 ps
CPU time 11.17 seconds
Started Aug 13 05:54:09 PM PDT 24
Finished Aug 13 05:54:20 PM PDT 24
Peak memory 201124 kb
Host smart-8074d8f5-2463-448d-92e3-a2e86d316c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288218861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3288218861
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.91494764
Short name T281
Test name
Test status
Simulation time 331147148254 ps
CPU time 677.78 seconds
Started Aug 13 06:02:09 PM PDT 24
Finished Aug 13 06:13:27 PM PDT 24
Peak memory 201992 kb
Host smart-71fb973b-6dd2-409e-bbc3-beebdc2508e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91494764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.91494764
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1981718614
Short name T333
Test name
Test status
Simulation time 12893177679 ps
CPU time 9.01 seconds
Started Aug 13 06:02:13 PM PDT 24
Finished Aug 13 06:02:22 PM PDT 24
Peak memory 202296 kb
Host smart-e75ee250-f89b-415f-87db-0bac38827804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981718614 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1981718614
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.4140364324
Short name T243
Test name
Test status
Simulation time 103634450306 ps
CPU time 551.45 seconds
Started Aug 13 06:02:45 PM PDT 24
Finished Aug 13 06:11:56 PM PDT 24
Peak memory 202568 kb
Host smart-15493eaf-11ea-461b-bc5b-0538861e6c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140364324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.4140364324
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1098601896
Short name T267
Test name
Test status
Simulation time 489254921287 ps
CPU time 597.49 seconds
Started Aug 13 06:03:11 PM PDT 24
Finished Aug 13 06:13:08 PM PDT 24
Peak memory 202132 kb
Host smart-85431331-d6db-4a5f-a0cb-ca39059f634d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098601896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1098601896
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3898048315
Short name T232
Test name
Test status
Simulation time 98286121953 ps
CPU time 503.63 seconds
Started Aug 13 06:03:17 PM PDT 24
Finished Aug 13 06:11:41 PM PDT 24
Peak memory 202396 kb
Host smart-ebec0d74-e52e-43d4-9882-937af8aea4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898048315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3898048315
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2872850875
Short name T317
Test name
Test status
Simulation time 378073396915 ps
CPU time 255.41 seconds
Started Aug 13 06:03:18 PM PDT 24
Finished Aug 13 06:07:34 PM PDT 24
Peak memory 202064 kb
Host smart-0a090cd1-b198-435e-b93d-214104068bb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872850875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2872850875
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1960031040
Short name T326
Test name
Test status
Simulation time 530908131998 ps
CPU time 298.7 seconds
Started Aug 13 06:05:06 PM PDT 24
Finished Aug 13 06:10:05 PM PDT 24
Peak memory 202144 kb
Host smart-47a024a7-1532-4728-8b1b-12656b3f5a24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960031040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1960031040
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3942568027
Short name T359
Test name
Test status
Simulation time 497433586269 ps
CPU time 590.16 seconds
Started Aug 13 06:06:15 PM PDT 24
Finished Aug 13 06:16:06 PM PDT 24
Peak memory 202152 kb
Host smart-60aee23e-b30e-4a4b-8b5b-2ee5818093c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942568027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3942568027
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.866009066
Short name T342
Test name
Test status
Simulation time 532952774994 ps
CPU time 120.84 seconds
Started Aug 13 06:07:10 PM PDT 24
Finished Aug 13 06:09:11 PM PDT 24
Peak memory 202196 kb
Host smart-96cf69b0-66d0-41a4-bf01-8138c7411258
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866009066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.866009066
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3134715178
Short name T26
Test name
Test status
Simulation time 15542712805 ps
CPU time 12.94 seconds
Started Aug 13 06:08:25 PM PDT 24
Finished Aug 13 06:08:38 PM PDT 24
Peak memory 210464 kb
Host smart-0fd787fb-21ce-4d88-acc9-40aef162fde5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134715178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3134715178
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1885954162
Short name T124
Test name
Test status
Simulation time 502542918 ps
CPU time 2.21 seconds
Started Aug 13 05:54:08 PM PDT 24
Finished Aug 13 05:54:10 PM PDT 24
Peak memory 201176 kb
Host smart-e2abf5a2-eff9-40e7-bd44-e600d61dcee9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885954162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1885954162
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3946499961
Short name T826
Test name
Test status
Simulation time 27191285168 ps
CPU time 45.69 seconds
Started Aug 13 05:54:07 PM PDT 24
Finished Aug 13 05:54:53 PM PDT 24
Peak memory 201160 kb
Host smart-67c5d3ad-8c96-43d8-8d85-438fa6782fc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946499961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3946499961
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.188493454
Short name T901
Test name
Test status
Simulation time 1013386117 ps
CPU time 1.33 seconds
Started Aug 13 05:54:06 PM PDT 24
Finished Aug 13 05:54:08 PM PDT 24
Peak memory 200928 kb
Host smart-c3eadfa5-9bce-4f10-a591-216ae0bf8b6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188493454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.188493454
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4194931557
Short name T816
Test name
Test status
Simulation time 667595266 ps
CPU time 1.43 seconds
Started Aug 13 05:54:10 PM PDT 24
Finished Aug 13 05:54:12 PM PDT 24
Peak memory 201012 kb
Host smart-3dfe2b5d-23bb-47f2-ae46-f765fb2a90cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194931557 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.4194931557
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4230197785
Short name T800
Test name
Test status
Simulation time 474959399 ps
CPU time 0.96 seconds
Started Aug 13 05:54:05 PM PDT 24
Finished Aug 13 05:54:06 PM PDT 24
Peak memory 200908 kb
Host smart-d39ca814-1e23-4839-b832-625ac963dd3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230197785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4230197785
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2664236753
Short name T138
Test name
Test status
Simulation time 5034064840 ps
CPU time 4.12 seconds
Started Aug 13 05:54:08 PM PDT 24
Finished Aug 13 05:54:13 PM PDT 24
Peak memory 201236 kb
Host smart-7dd80cff-e22f-4e4c-9f6b-f874b40fc772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664236753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2664236753
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3628712206
Short name T362
Test name
Test status
Simulation time 4545658603 ps
CPU time 11.37 seconds
Started Aug 13 05:54:06 PM PDT 24
Finished Aug 13 05:54:17 PM PDT 24
Peak memory 201172 kb
Host smart-37da2fe0-5708-482f-ab58-9b440ce6eac7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628712206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3628712206
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2378478781
Short name T141
Test name
Test status
Simulation time 1359713125 ps
CPU time 5.26 seconds
Started Aug 13 05:54:12 PM PDT 24
Finished Aug 13 05:54:17 PM PDT 24
Peak memory 201172 kb
Host smart-05987f3e-c0b8-4add-aa3a-4b521ca4d852
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378478781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2378478781
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2273441491
Short name T819
Test name
Test status
Simulation time 26443935079 ps
CPU time 31.28 seconds
Started Aug 13 05:54:11 PM PDT 24
Finished Aug 13 05:54:42 PM PDT 24
Peak memory 201200 kb
Host smart-59d32340-5120-48d4-a4c4-73657ee395d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273441491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2273441491
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3371275475
Short name T825
Test name
Test status
Simulation time 755827038 ps
CPU time 1.43 seconds
Started Aug 13 05:54:07 PM PDT 24
Finished Aug 13 05:54:09 PM PDT 24
Peak memory 200984 kb
Host smart-bffb0dfd-edbd-4d7f-8c14-94a6e653520b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371275475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3371275475
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3467640181
Short name T85
Test name
Test status
Simulation time 604764890 ps
CPU time 1.28 seconds
Started Aug 13 05:54:06 PM PDT 24
Finished Aug 13 05:54:07 PM PDT 24
Peak memory 201064 kb
Host smart-341f1267-aa66-401e-96a8-5471c3a65e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467640181 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3467640181
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1709224386
Short name T862
Test name
Test status
Simulation time 491608926 ps
CPU time 1.08 seconds
Started Aug 13 05:54:09 PM PDT 24
Finished Aug 13 05:54:10 PM PDT 24
Peak memory 200960 kb
Host smart-3d0436ee-ff69-4755-b3b2-4c2e8d2a7a5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709224386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1709224386
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4077752628
Short name T871
Test name
Test status
Simulation time 464334102 ps
CPU time 1.01 seconds
Started Aug 13 05:54:09 PM PDT 24
Finished Aug 13 05:54:10 PM PDT 24
Peak memory 200912 kb
Host smart-e801d7bc-7517-4b04-b0db-7ef1c0364998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077752628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.4077752628
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2318102556
Short name T69
Test name
Test status
Simulation time 2461134394 ps
CPU time 4.83 seconds
Started Aug 13 05:54:11 PM PDT 24
Finished Aug 13 05:54:16 PM PDT 24
Peak memory 201028 kb
Host smart-db374689-3b9a-4bdf-9048-bcc91fa78cc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318102556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2318102556
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3164817384
Short name T863
Test name
Test status
Simulation time 600807490 ps
CPU time 2.27 seconds
Started Aug 13 05:54:10 PM PDT 24
Finished Aug 13 05:54:12 PM PDT 24
Peak memory 209332 kb
Host smart-552ad120-1777-445e-85c3-696fa6cb7a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164817384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3164817384
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3237137545
Short name T364
Test name
Test status
Simulation time 4126350942 ps
CPU time 3.85 seconds
Started Aug 13 05:54:09 PM PDT 24
Finished Aug 13 05:54:13 PM PDT 24
Peak memory 201204 kb
Host smart-ae4cc1cb-93cb-4f70-b168-d023dfa0896e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237137545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3237137545
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2036865586
Short name T76
Test name
Test status
Simulation time 602588439 ps
CPU time 2.28 seconds
Started Aug 13 05:54:24 PM PDT 24
Finished Aug 13 05:54:26 PM PDT 24
Peak memory 201044 kb
Host smart-5993ef1b-e176-4546-a985-b3b7db571fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036865586 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2036865586
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3690713649
Short name T130
Test name
Test status
Simulation time 344024481 ps
CPU time 1.46 seconds
Started Aug 13 05:54:26 PM PDT 24
Finished Aug 13 05:54:27 PM PDT 24
Peak memory 200952 kb
Host smart-018d41d2-4253-4cdc-819e-53afb3cf5d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690713649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3690713649
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4178896735
Short name T803
Test name
Test status
Simulation time 475617664 ps
CPU time 0.9 seconds
Started Aug 13 05:54:26 PM PDT 24
Finished Aug 13 05:54:27 PM PDT 24
Peak memory 200788 kb
Host smart-dccbb8bb-042a-4782-a6cf-bb6430032adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178896735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4178896735
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3500420758
Short name T840
Test name
Test status
Simulation time 4607024567 ps
CPU time 15.38 seconds
Started Aug 13 05:54:25 PM PDT 24
Finished Aug 13 05:54:41 PM PDT 24
Peak memory 201160 kb
Host smart-30f3ec17-63e8-4bcc-a73c-b2b42b8e6ece
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500420758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3500420758
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.617760067
Short name T846
Test name
Test status
Simulation time 576741069 ps
CPU time 2.65 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 210448 kb
Host smart-63bcd1b6-2183-4a60-bbc3-d8feb5a93790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617760067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.617760067
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3944281802
Short name T848
Test name
Test status
Simulation time 4365138305 ps
CPU time 6.53 seconds
Started Aug 13 05:54:27 PM PDT 24
Finished Aug 13 05:54:34 PM PDT 24
Peak memory 201184 kb
Host smart-e77b4a06-0538-4113-93d7-9c7a845f1fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944281802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3944281802
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.480354385
Short name T87
Test name
Test status
Simulation time 514274479 ps
CPU time 2.27 seconds
Started Aug 13 05:54:29 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 200944 kb
Host smart-86f959a7-bbdb-46b1-868d-7a3508e7d292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480354385 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.480354385
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2149776317
Short name T127
Test name
Test status
Simulation time 501438252 ps
CPU time 1.43 seconds
Started Aug 13 05:54:30 PM PDT 24
Finished Aug 13 05:54:32 PM PDT 24
Peak memory 200908 kb
Host smart-420e176b-384f-484a-9f26-e51044c57cd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149776317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2149776317
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.253609854
Short name T872
Test name
Test status
Simulation time 295424845 ps
CPU time 1.25 seconds
Started Aug 13 05:54:30 PM PDT 24
Finished Aug 13 05:54:32 PM PDT 24
Peak memory 200808 kb
Host smart-86bc5076-e421-4c2a-a38c-10c2256a7bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253609854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.253609854
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3498729316
Short name T852
Test name
Test status
Simulation time 2443098415 ps
CPU time 2.37 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 201016 kb
Host smart-ab7778ed-2712-4eae-8b68-558799376447
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498729316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3498729316
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1470210701
Short name T84
Test name
Test status
Simulation time 430251314 ps
CPU time 1.78 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:30 PM PDT 24
Peak memory 201196 kb
Host smart-6d8cef70-ffc9-475c-b5b7-afba1a78feea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470210701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1470210701
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3366041113
Short name T89
Test name
Test status
Simulation time 8302138327 ps
CPU time 12.19 seconds
Started Aug 13 05:54:27 PM PDT 24
Finished Aug 13 05:54:40 PM PDT 24
Peak memory 201224 kb
Host smart-bf41bab8-3550-4d6f-b718-dd8953a72fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366041113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3366041113
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2045922047
Short name T865
Test name
Test status
Simulation time 628207558 ps
CPU time 1.69 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:30 PM PDT 24
Peak memory 209448 kb
Host smart-263792fe-6a67-423b-bb66-45f82ccac966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045922047 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2045922047
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.691089245
Short name T870
Test name
Test status
Simulation time 520929071 ps
CPU time 2.02 seconds
Started Aug 13 05:54:29 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 200992 kb
Host smart-0128d884-ee67-4f5e-9ed5-53a55b6115e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691089245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.691089245
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2995869132
Short name T849
Test name
Test status
Simulation time 529371338 ps
CPU time 1.87 seconds
Started Aug 13 05:54:29 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 200916 kb
Host smart-455022f0-6d24-482d-bd13-40bb51782350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995869132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2995869132
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2499616981
Short name T886
Test name
Test status
Simulation time 2388104512 ps
CPU time 7.82 seconds
Started Aug 13 05:54:27 PM PDT 24
Finished Aug 13 05:54:35 PM PDT 24
Peak memory 200984 kb
Host smart-7d5fadec-08fd-4d56-a447-8656600fe1e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499616981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2499616981
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3254727113
Short name T894
Test name
Test status
Simulation time 535240445 ps
CPU time 3.37 seconds
Started Aug 13 05:54:27 PM PDT 24
Finished Aug 13 05:54:30 PM PDT 24
Peak memory 201140 kb
Host smart-b2dbc6ca-16d8-4f83-9d4c-e0fab77e5e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254727113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3254727113
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2176480187
Short name T874
Test name
Test status
Simulation time 9166565301 ps
CPU time 6.18 seconds
Started Aug 13 05:54:26 PM PDT 24
Finished Aug 13 05:54:32 PM PDT 24
Peak memory 201240 kb
Host smart-f732b5af-08c6-44a3-8ac9-29a8121619fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176480187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2176480187
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3040671563
Short name T93
Test name
Test status
Simulation time 456281546 ps
CPU time 1.28 seconds
Started Aug 13 05:54:30 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 200996 kb
Host smart-d9406092-424f-4d2b-82ae-3ff9fe9ff739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040671563 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3040671563
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.17354977
Short name T123
Test name
Test status
Simulation time 479103452 ps
CPU time 1.67 seconds
Started Aug 13 05:54:26 PM PDT 24
Finished Aug 13 05:54:28 PM PDT 24
Peak memory 200932 kb
Host smart-65c0e31b-5ac5-4f84-9779-718b2f2f9aa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17354977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.17354977
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.54749835
Short name T820
Test name
Test status
Simulation time 341589207 ps
CPU time 1.38 seconds
Started Aug 13 05:54:26 PM PDT 24
Finished Aug 13 05:54:27 PM PDT 24
Peak memory 200896 kb
Host smart-721ed363-b5f1-4e1e-b409-f51e29434b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54749835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.54749835
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.413495291
Short name T899
Test name
Test status
Simulation time 2527935145 ps
CPU time 8.76 seconds
Started Aug 13 05:54:29 PM PDT 24
Finished Aug 13 05:54:38 PM PDT 24
Peak memory 201044 kb
Host smart-be186dfd-0f40-4bdf-be71-4c7486eac9ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413495291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.413495291
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.487431938
Short name T823
Test name
Test status
Simulation time 333784400 ps
CPU time 2.03 seconds
Started Aug 13 05:54:27 PM PDT 24
Finished Aug 13 05:54:29 PM PDT 24
Peak memory 201236 kb
Host smart-8b86da58-81f0-4ab7-9fd3-1d1c8d4f512e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487431938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.487431938
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2080825045
Short name T868
Test name
Test status
Simulation time 8554016913 ps
CPU time 7.17 seconds
Started Aug 13 05:54:26 PM PDT 24
Finished Aug 13 05:54:33 PM PDT 24
Peak memory 201120 kb
Host smart-ae9c1d3b-f73e-4859-a427-c42d38c1a84e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080825045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2080825045
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2698138204
Short name T94
Test name
Test status
Simulation time 559595953 ps
CPU time 1.42 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:29 PM PDT 24
Peak memory 201048 kb
Host smart-16ef7616-ee9d-42da-bb44-38b0711901a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698138204 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2698138204
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2354885819
Short name T131
Test name
Test status
Simulation time 409943603 ps
CPU time 1.3 seconds
Started Aug 13 05:54:29 PM PDT 24
Finished Aug 13 05:54:30 PM PDT 24
Peak memory 200916 kb
Host smart-e0762c24-cc34-4fe5-af32-146aacd2e59c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354885819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2354885819
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1952425641
Short name T913
Test name
Test status
Simulation time 334469511 ps
CPU time 0.82 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:29 PM PDT 24
Peak memory 200908 kb
Host smart-26272b47-cbac-4e03-84cd-77305044ab92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952425641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1952425641
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2401651474
Short name T911
Test name
Test status
Simulation time 4791439968 ps
CPU time 17.09 seconds
Started Aug 13 05:54:30 PM PDT 24
Finished Aug 13 05:54:47 PM PDT 24
Peak memory 201188 kb
Host smart-c4d509ec-6a28-4dbc-b5d1-e2af6b773ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401651474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2401651474
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1405130031
Short name T867
Test name
Test status
Simulation time 427121803 ps
CPU time 2.04 seconds
Started Aug 13 05:54:26 PM PDT 24
Finished Aug 13 05:54:29 PM PDT 24
Peak memory 217540 kb
Host smart-5043dbcd-f2d1-4fde-81d1-6becf72ad0a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405130031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1405130031
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1876077540
Short name T855
Test name
Test status
Simulation time 4440628487 ps
CPU time 11.79 seconds
Started Aug 13 05:54:29 PM PDT 24
Finished Aug 13 05:54:41 PM PDT 24
Peak memory 201244 kb
Host smart-3ec8af04-1d13-4f9d-afa5-7449ae1da966
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876077540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1876077540
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2548353995
Short name T88
Test name
Test status
Simulation time 733640956 ps
CPU time 1.19 seconds
Started Aug 13 05:54:36 PM PDT 24
Finished Aug 13 05:54:37 PM PDT 24
Peak memory 201048 kb
Host smart-b2a86d51-9395-4095-ac28-4ef47654c647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548353995 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2548353995
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.47788840
Short name T136
Test name
Test status
Simulation time 407881742 ps
CPU time 1.83 seconds
Started Aug 13 05:54:38 PM PDT 24
Finished Aug 13 05:54:40 PM PDT 24
Peak memory 200964 kb
Host smart-3213cc37-bbad-4270-817e-ff6166f6ea72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47788840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.47788840
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.726974565
Short name T882
Test name
Test status
Simulation time 442387144 ps
CPU time 1.65 seconds
Started Aug 13 05:54:36 PM PDT 24
Finished Aug 13 05:54:38 PM PDT 24
Peak memory 200896 kb
Host smart-6e89bace-1a02-4a7f-a19c-9eab4caf8fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726974565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.726974565
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.357564082
Short name T831
Test name
Test status
Simulation time 3845138339 ps
CPU time 7.78 seconds
Started Aug 13 05:54:38 PM PDT 24
Finished Aug 13 05:54:46 PM PDT 24
Peak memory 201184 kb
Host smart-af2b8e6f-a34a-4011-a74d-5959f3357014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357564082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.357564082
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3611446180
Short name T843
Test name
Test status
Simulation time 373276475 ps
CPU time 2.63 seconds
Started Aug 13 05:54:25 PM PDT 24
Finished Aug 13 05:54:27 PM PDT 24
Peak memory 201320 kb
Host smart-174de1a9-2f15-4b0f-b381-5e5b9dc9c6a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611446180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3611446180
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4270859325
Short name T73
Test name
Test status
Simulation time 4018381463 ps
CPU time 4.08 seconds
Started Aug 13 05:54:27 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 201188 kb
Host smart-d4728281-19a5-49d7-a864-a265d8af3ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270859325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4270859325
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.680120664
Short name T841
Test name
Test status
Simulation time 531662511 ps
CPU time 1.25 seconds
Started Aug 13 05:54:37 PM PDT 24
Finished Aug 13 05:54:38 PM PDT 24
Peak memory 201004 kb
Host smart-beaee76e-e582-4eea-9498-806f82416d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680120664 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.680120664
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.843088042
Short name T126
Test name
Test status
Simulation time 328117459 ps
CPU time 1.49 seconds
Started Aug 13 05:54:34 PM PDT 24
Finished Aug 13 05:54:36 PM PDT 24
Peak memory 201096 kb
Host smart-59efa501-417c-40f7-b75e-5827b465d9cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843088042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.843088042
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2230871503
Short name T895
Test name
Test status
Simulation time 375382281 ps
CPU time 1.59 seconds
Started Aug 13 05:54:39 PM PDT 24
Finished Aug 13 05:54:40 PM PDT 24
Peak memory 200856 kb
Host smart-0d6bcf80-adf0-447e-b5dc-bd463e9ba37c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230871503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2230871503
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2065677477
Short name T891
Test name
Test status
Simulation time 4948847360 ps
CPU time 9.69 seconds
Started Aug 13 05:54:36 PM PDT 24
Finished Aug 13 05:54:46 PM PDT 24
Peak memory 201232 kb
Host smart-aaf06ca6-9d0b-42bc-8264-aa876e43542d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065677477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2065677477
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.904020082
Short name T824
Test name
Test status
Simulation time 934089915 ps
CPU time 2.88 seconds
Started Aug 13 05:54:34 PM PDT 24
Finished Aug 13 05:54:37 PM PDT 24
Peak memory 217096 kb
Host smart-75a9641f-af56-45ca-82a1-727eeea36f71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904020082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.904020082
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4072637767
Short name T361
Test name
Test status
Simulation time 4861446660 ps
CPU time 4.08 seconds
Started Aug 13 05:54:36 PM PDT 24
Finished Aug 13 05:54:40 PM PDT 24
Peak memory 201236 kb
Host smart-a6562f67-1990-4a2e-991e-737324192d44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072637767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.4072637767
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1337326619
Short name T918
Test name
Test status
Simulation time 455838821 ps
CPU time 1.41 seconds
Started Aug 13 05:54:38 PM PDT 24
Finished Aug 13 05:54:39 PM PDT 24
Peak memory 201064 kb
Host smart-3ff24ae3-25ba-41ad-b9e4-5ec2e38dfde3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337326619 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1337326619
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1464605379
Short name T897
Test name
Test status
Simulation time 530375299 ps
CPU time 1.99 seconds
Started Aug 13 05:54:37 PM PDT 24
Finished Aug 13 05:54:40 PM PDT 24
Peak memory 200912 kb
Host smart-aa89226d-1e5f-441d-9352-41d3cc07ab4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464605379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1464605379
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4170181409
Short name T881
Test name
Test status
Simulation time 449555538 ps
CPU time 1.61 seconds
Started Aug 13 05:54:35 PM PDT 24
Finished Aug 13 05:54:37 PM PDT 24
Peak memory 200912 kb
Host smart-ce2c6638-d17d-4bbb-944e-7c2ad19ec4ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170181409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4170181409
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1756013541
Short name T828
Test name
Test status
Simulation time 2089893016 ps
CPU time 4.26 seconds
Started Aug 13 05:54:38 PM PDT 24
Finished Aug 13 05:54:43 PM PDT 24
Peak memory 200972 kb
Host smart-df73ed4a-05d5-45be-a9cb-f17bf95058b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756013541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1756013541
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1190800077
Short name T858
Test name
Test status
Simulation time 405729677 ps
CPU time 1.97 seconds
Started Aug 13 05:54:37 PM PDT 24
Finished Aug 13 05:54:39 PM PDT 24
Peak memory 201152 kb
Host smart-215c484d-566d-423e-8c3c-4041672fa8bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190800077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1190800077
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2697718436
Short name T888
Test name
Test status
Simulation time 8775465819 ps
CPU time 8.62 seconds
Started Aug 13 05:54:39 PM PDT 24
Finished Aug 13 05:54:48 PM PDT 24
Peak memory 201144 kb
Host smart-37c36f84-4011-4254-9365-85d54784620e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697718436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2697718436
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1448763280
Short name T898
Test name
Test status
Simulation time 608291087 ps
CPU time 1.41 seconds
Started Aug 13 05:54:38 PM PDT 24
Finished Aug 13 05:54:40 PM PDT 24
Peak memory 201040 kb
Host smart-5bb5cf73-28f3-4b77-ad4b-2722f4389d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448763280 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1448763280
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2964706078
Short name T914
Test name
Test status
Simulation time 438411499 ps
CPU time 1.81 seconds
Started Aug 13 05:54:38 PM PDT 24
Finished Aug 13 05:54:40 PM PDT 24
Peak memory 200956 kb
Host smart-12fb7782-0c7c-4860-93e2-8e4c2d618b8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964706078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2964706078
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1342987368
Short name T827
Test name
Test status
Simulation time 390441989 ps
CPU time 0.94 seconds
Started Aug 13 05:54:38 PM PDT 24
Finished Aug 13 05:54:39 PM PDT 24
Peak memory 200888 kb
Host smart-273aa092-0a5b-449f-be1b-98b1f5a63f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342987368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1342987368
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1261858044
Short name T902
Test name
Test status
Simulation time 1992893797 ps
CPU time 3.16 seconds
Started Aug 13 05:54:39 PM PDT 24
Finished Aug 13 05:54:43 PM PDT 24
Peak memory 200900 kb
Host smart-442a704b-907d-4894-a698-318f0bb6d3c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261858044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1261858044
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.31864095
Short name T910
Test name
Test status
Simulation time 440499051 ps
CPU time 2.39 seconds
Started Aug 13 05:54:39 PM PDT 24
Finished Aug 13 05:54:42 PM PDT 24
Peak memory 201140 kb
Host smart-e6141f8d-753e-4234-8cd6-f2b9ade33848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31864095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.31864095
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2459035325
Short name T815
Test name
Test status
Simulation time 453105985 ps
CPU time 1.22 seconds
Started Aug 13 05:54:46 PM PDT 24
Finished Aug 13 05:54:47 PM PDT 24
Peak memory 201016 kb
Host smart-f6e5478e-c89e-4d31-811f-12cec5a61a8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459035325 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2459035325
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.719458029
Short name T845
Test name
Test status
Simulation time 381785733 ps
CPU time 1.09 seconds
Started Aug 13 05:54:46 PM PDT 24
Finished Aug 13 05:54:47 PM PDT 24
Peak memory 200896 kb
Host smart-82fe4489-9e35-45ab-bfef-da4b7ae4dc5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719458029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.719458029
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3121328298
Short name T879
Test name
Test status
Simulation time 450318669 ps
CPU time 1.11 seconds
Started Aug 13 05:54:40 PM PDT 24
Finished Aug 13 05:54:41 PM PDT 24
Peak memory 200852 kb
Host smart-66ed4e46-7488-424c-ac56-ca916ae6d17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121328298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3121328298
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.622977829
Short name T67
Test name
Test status
Simulation time 5235915464 ps
CPU time 21.02 seconds
Started Aug 13 05:54:47 PM PDT 24
Finished Aug 13 05:55:08 PM PDT 24
Peak memory 201176 kb
Host smart-35de1361-7994-46dd-9c47-d286503be68c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622977829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.622977829
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.766504458
Short name T864
Test name
Test status
Simulation time 4534754293 ps
CPU time 9.04 seconds
Started Aug 13 05:54:38 PM PDT 24
Finished Aug 13 05:54:47 PM PDT 24
Peak memory 201132 kb
Host smart-4217fa44-41de-4193-9f98-558553eaa0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766504458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.766504458
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.294586678
Short name T129
Test name
Test status
Simulation time 986492777 ps
CPU time 4.77 seconds
Started Aug 13 05:54:13 PM PDT 24
Finished Aug 13 05:54:18 PM PDT 24
Peak memory 201044 kb
Host smart-fe48db94-841a-42b8-957e-c46bd5f2e946
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294586678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.294586678
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.541417934
Short name T135
Test name
Test status
Simulation time 2302033114 ps
CPU time 4.24 seconds
Started Aug 13 05:54:08 PM PDT 24
Finished Aug 13 05:54:12 PM PDT 24
Peak memory 201148 kb
Host smart-5ff6d02d-154d-4d4d-bb5a-396fbe72f1ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541417934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.541417934
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3672181963
Short name T859
Test name
Test status
Simulation time 834196862 ps
CPU time 1.13 seconds
Started Aug 13 05:54:13 PM PDT 24
Finished Aug 13 05:54:15 PM PDT 24
Peak memory 200880 kb
Host smart-eceba040-8f4d-4d0f-b39c-a638fe2e4228
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672181963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3672181963
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1516954229
Short name T885
Test name
Test status
Simulation time 761857058 ps
CPU time 1.4 seconds
Started Aug 13 05:54:16 PM PDT 24
Finished Aug 13 05:54:17 PM PDT 24
Peak memory 209340 kb
Host smart-f47cd9c3-9e3a-408e-bb7c-b08e969cdee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516954229 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1516954229
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1230952788
Short name T140
Test name
Test status
Simulation time 427593541 ps
CPU time 0.99 seconds
Started Aug 13 05:54:10 PM PDT 24
Finished Aug 13 05:54:11 PM PDT 24
Peak memory 200916 kb
Host smart-b3c5981f-4ab6-4763-89ce-3d32ae727904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230952788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1230952788
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3239179728
Short name T829
Test name
Test status
Simulation time 456313477 ps
CPU time 0.9 seconds
Started Aug 13 05:54:11 PM PDT 24
Finished Aug 13 05:54:12 PM PDT 24
Peak memory 200912 kb
Host smart-bd5c175c-380c-4584-b132-c45d3b645fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239179728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3239179728
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1177146663
Short name T893
Test name
Test status
Simulation time 4292229786 ps
CPU time 9.29 seconds
Started Aug 13 05:54:09 PM PDT 24
Finished Aug 13 05:54:18 PM PDT 24
Peak memory 201164 kb
Host smart-db737ec7-7eb0-4b99-80b8-aad800123624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177146663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1177146663
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1743149958
Short name T917
Test name
Test status
Simulation time 540961588 ps
CPU time 1.95 seconds
Started Aug 13 05:54:10 PM PDT 24
Finished Aug 13 05:54:12 PM PDT 24
Peak memory 201184 kb
Host smart-d5cf75ce-41c1-4129-bdaf-6556821ca7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743149958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1743149958
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1613518546
Short name T809
Test name
Test status
Simulation time 452524142 ps
CPU time 0.76 seconds
Started Aug 13 05:54:45 PM PDT 24
Finished Aug 13 05:54:46 PM PDT 24
Peak memory 200844 kb
Host smart-e9e850c1-deab-46df-950b-4979387d24fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613518546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1613518546
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.346526724
Short name T817
Test name
Test status
Simulation time 652403801 ps
CPU time 0.77 seconds
Started Aug 13 05:54:48 PM PDT 24
Finished Aug 13 05:54:49 PM PDT 24
Peak memory 200916 kb
Host smart-8e974134-6580-4203-b4bd-782a3bafbf53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346526724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.346526724
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2837288448
Short name T807
Test name
Test status
Simulation time 430537299 ps
CPU time 0.91 seconds
Started Aug 13 05:54:45 PM PDT 24
Finished Aug 13 05:54:46 PM PDT 24
Peak memory 200860 kb
Host smart-e9d9e497-7dda-4f5d-9363-c5ea34f064f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837288448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2837288448
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4190584531
Short name T834
Test name
Test status
Simulation time 516690854 ps
CPU time 0.89 seconds
Started Aug 13 05:54:48 PM PDT 24
Finished Aug 13 05:54:49 PM PDT 24
Peak memory 200892 kb
Host smart-062b092d-0acd-44da-ac38-aef19f5c9b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190584531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.4190584531
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2203516121
Short name T810
Test name
Test status
Simulation time 528113720 ps
CPU time 1.17 seconds
Started Aug 13 05:54:42 PM PDT 24
Finished Aug 13 05:54:43 PM PDT 24
Peak memory 200760 kb
Host smart-d637be52-5bf9-4a92-b8c3-ec5ee0850d1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203516121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2203516121
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2191571897
Short name T832
Test name
Test status
Simulation time 308902764 ps
CPU time 1.01 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:54:57 PM PDT 24
Peak memory 200872 kb
Host smart-5fdba91a-654b-4f30-b01b-9bd92324fb14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191571897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2191571897
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.448413882
Short name T847
Test name
Test status
Simulation time 458086339 ps
CPU time 0.86 seconds
Started Aug 13 05:54:45 PM PDT 24
Finished Aug 13 05:54:46 PM PDT 24
Peak memory 200924 kb
Host smart-af018d4f-7216-4b7d-b639-0b49ae515131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448413882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.448413882
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1934362068
Short name T850
Test name
Test status
Simulation time 393753722 ps
CPU time 0.86 seconds
Started Aug 13 05:54:47 PM PDT 24
Finished Aug 13 05:54:48 PM PDT 24
Peak memory 200860 kb
Host smart-2d59d8dc-6172-4277-bdf1-bab0e7714c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934362068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1934362068
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3062897331
Short name T806
Test name
Test status
Simulation time 513621232 ps
CPU time 1.04 seconds
Started Aug 13 05:54:45 PM PDT 24
Finished Aug 13 05:54:46 PM PDT 24
Peak memory 200900 kb
Host smart-09d4d084-6667-4309-b59b-a10ce4f17f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062897331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3062897331
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1561445507
Short name T889
Test name
Test status
Simulation time 508842788 ps
CPU time 0.95 seconds
Started Aug 13 05:54:54 PM PDT 24
Finished Aug 13 05:54:55 PM PDT 24
Peak memory 200032 kb
Host smart-cafc802b-303a-4c1c-93eb-f2e2f1aa6a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561445507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1561445507
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1377460746
Short name T137
Test name
Test status
Simulation time 488927166 ps
CPU time 2.55 seconds
Started Aug 13 05:54:13 PM PDT 24
Finished Aug 13 05:54:16 PM PDT 24
Peak memory 201024 kb
Host smart-59d7d218-dcb5-48f0-9954-8dcaca71994b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377460746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1377460746
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.413805621
Short name T134
Test name
Test status
Simulation time 47917187469 ps
CPU time 45.91 seconds
Started Aug 13 05:54:11 PM PDT 24
Finished Aug 13 05:54:57 PM PDT 24
Peak memory 201216 kb
Host smart-c4c226cc-b4e5-4227-acc7-51ed59c1fdee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413805621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.413805621
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.504548996
Short name T133
Test name
Test status
Simulation time 1214651103 ps
CPU time 1.22 seconds
Started Aug 13 05:54:13 PM PDT 24
Finished Aug 13 05:54:14 PM PDT 24
Peak memory 200856 kb
Host smart-0d11e135-6348-47ce-b8af-709f7f13c1db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504548996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.504548996
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3648610298
Short name T869
Test name
Test status
Simulation time 489871072 ps
CPU time 1.25 seconds
Started Aug 13 05:54:07 PM PDT 24
Finished Aug 13 05:54:08 PM PDT 24
Peak memory 201044 kb
Host smart-28fd34da-b382-4069-bedc-b2e608dec809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648610298 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3648610298
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4166088907
Short name T830
Test name
Test status
Simulation time 411165799 ps
CPU time 0.93 seconds
Started Aug 13 05:54:10 PM PDT 24
Finished Aug 13 05:54:11 PM PDT 24
Peak memory 200944 kb
Host smart-c6fac2b0-cb9e-4966-b9cf-8344d8b20b9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166088907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.4166088907
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4227091313
Short name T915
Test name
Test status
Simulation time 464246909 ps
CPU time 1.41 seconds
Started Aug 13 05:54:16 PM PDT 24
Finished Aug 13 05:54:17 PM PDT 24
Peak memory 200804 kb
Host smart-5538aa25-4dad-4f07-bdcc-7709c185fc4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227091313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4227091313
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.888360777
Short name T909
Test name
Test status
Simulation time 2209033968 ps
CPU time 5.77 seconds
Started Aug 13 05:54:16 PM PDT 24
Finished Aug 13 05:54:22 PM PDT 24
Peak memory 200948 kb
Host smart-0717d15f-2a9d-44fa-a5ac-f296a5bde761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888360777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.888360777
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.928577158
Short name T887
Test name
Test status
Simulation time 1017720326 ps
CPU time 3.21 seconds
Started Aug 13 05:54:11 PM PDT 24
Finished Aug 13 05:54:15 PM PDT 24
Peak memory 210436 kb
Host smart-8ec49bbb-1db9-4372-a74a-705f7f2f41d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928577158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.928577158
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2404998450
Short name T363
Test name
Test status
Simulation time 9980018086 ps
CPU time 4.23 seconds
Started Aug 13 05:54:11 PM PDT 24
Finished Aug 13 05:54:15 PM PDT 24
Peak memory 201216 kb
Host smart-c4beafd7-861f-4055-9268-d38a88222133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404998450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2404998450
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.923356437
Short name T808
Test name
Test status
Simulation time 535169079 ps
CPU time 1.01 seconds
Started Aug 13 05:54:44 PM PDT 24
Finished Aug 13 05:54:45 PM PDT 24
Peak memory 200808 kb
Host smart-a7c83226-ac76-4e0b-a058-2677d5a338ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923356437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.923356437
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3407537856
Short name T883
Test name
Test status
Simulation time 374004926 ps
CPU time 1.09 seconds
Started Aug 13 05:54:48 PM PDT 24
Finished Aug 13 05:54:50 PM PDT 24
Peak memory 200892 kb
Host smart-be5472ad-144b-4f7b-84a4-966eaa0719fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407537856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3407537856
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1182566430
Short name T822
Test name
Test status
Simulation time 575398369 ps
CPU time 0.71 seconds
Started Aug 13 05:54:54 PM PDT 24
Finished Aug 13 05:54:55 PM PDT 24
Peak memory 200268 kb
Host smart-8dbbb112-8866-43d3-8e0e-4cea1c6e2b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182566430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1182566430
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.136753710
Short name T884
Test name
Test status
Simulation time 522146279 ps
CPU time 1.23 seconds
Started Aug 13 05:54:43 PM PDT 24
Finished Aug 13 05:54:45 PM PDT 24
Peak memory 200908 kb
Host smart-4e200d4e-94bf-491c-8241-78b05f22ada7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136753710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.136753710
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1525299272
Short name T896
Test name
Test status
Simulation time 510768490 ps
CPU time 0.75 seconds
Started Aug 13 05:54:45 PM PDT 24
Finished Aug 13 05:54:46 PM PDT 24
Peak memory 200876 kb
Host smart-9bf78905-ff8d-4d1f-8bc8-779877204607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525299272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1525299272
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2132130848
Short name T877
Test name
Test status
Simulation time 648422666 ps
CPU time 0.7 seconds
Started Aug 13 05:54:54 PM PDT 24
Finished Aug 13 05:54:55 PM PDT 24
Peak memory 200872 kb
Host smart-ade336fa-9bc1-4b83-8cc1-f77beb1ae78e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132130848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2132130848
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2773229647
Short name T912
Test name
Test status
Simulation time 499258245 ps
CPU time 1.18 seconds
Started Aug 13 05:54:46 PM PDT 24
Finished Aug 13 05:54:47 PM PDT 24
Peak memory 200916 kb
Host smart-87d07593-45ab-446f-878c-d53ac60e7051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773229647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2773229647
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1347964006
Short name T904
Test name
Test status
Simulation time 307464121 ps
CPU time 1.41 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:54:58 PM PDT 24
Peak memory 200872 kb
Host smart-9419d1e3-4399-4045-935f-a43d0b890c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347964006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1347964006
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2854945896
Short name T842
Test name
Test status
Simulation time 547540466 ps
CPU time 1.01 seconds
Started Aug 13 05:54:46 PM PDT 24
Finished Aug 13 05:54:47 PM PDT 24
Peak memory 200912 kb
Host smart-1c68c08e-2bf6-4870-84b3-b6f6d7a48cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854945896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2854945896
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.262297024
Short name T799
Test name
Test status
Simulation time 324356394 ps
CPU time 0.78 seconds
Started Aug 13 05:54:46 PM PDT 24
Finished Aug 13 05:54:47 PM PDT 24
Peak memory 200892 kb
Host smart-e5ed029f-bc9f-4a90-bade-4bf1ac6f0dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262297024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.262297024
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.193694692
Short name T142
Test name
Test status
Simulation time 842428199 ps
CPU time 2.07 seconds
Started Aug 13 05:54:16 PM PDT 24
Finished Aug 13 05:54:18 PM PDT 24
Peak memory 201152 kb
Host smart-f7f62081-48c7-4a27-bfde-c369e344a036
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193694692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.193694692
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.781746004
Short name T851
Test name
Test status
Simulation time 1022048272 ps
CPU time 3.05 seconds
Started Aug 13 05:54:22 PM PDT 24
Finished Aug 13 05:54:25 PM PDT 24
Peak memory 200964 kb
Host smart-41db9d90-26ee-443d-a661-3e5df0f90af4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781746004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.781746004
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.842154872
Short name T876
Test name
Test status
Simulation time 586715331 ps
CPU time 1.28 seconds
Started Aug 13 05:54:19 PM PDT 24
Finished Aug 13 05:54:21 PM PDT 24
Peak memory 200984 kb
Host smart-af017b1a-f487-42c2-bd63-6557d27b003e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842154872 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.842154872
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1858107800
Short name T861
Test name
Test status
Simulation time 491863694 ps
CPU time 0.95 seconds
Started Aug 13 05:54:18 PM PDT 24
Finished Aug 13 05:54:19 PM PDT 24
Peak memory 200992 kb
Host smart-6bd56268-2c32-43df-9ccf-a02e630d054d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858107800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1858107800
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1720311467
Short name T814
Test name
Test status
Simulation time 304099365 ps
CPU time 1.26 seconds
Started Aug 13 05:54:15 PM PDT 24
Finished Aug 13 05:54:17 PM PDT 24
Peak memory 200796 kb
Host smart-4c866919-bc4c-47bd-8da4-759b10b8326a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720311467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1720311467
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.333616481
Short name T838
Test name
Test status
Simulation time 2930549099 ps
CPU time 10.21 seconds
Started Aug 13 05:54:19 PM PDT 24
Finished Aug 13 05:54:30 PM PDT 24
Peak memory 201060 kb
Host smart-3e12de87-d2d5-41a7-a4ea-4328c683152c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333616481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.333616481
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.956190645
Short name T80
Test name
Test status
Simulation time 566262542 ps
CPU time 3.56 seconds
Started Aug 13 05:54:10 PM PDT 24
Finished Aug 13 05:54:14 PM PDT 24
Peak memory 209416 kb
Host smart-0c3e8395-2055-4b1b-b713-1eca07819506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956190645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.956190645
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1538065443
Short name T72
Test name
Test status
Simulation time 8008835917 ps
CPU time 18.96 seconds
Started Aug 13 05:54:16 PM PDT 24
Finished Aug 13 05:54:35 PM PDT 24
Peak memory 201064 kb
Host smart-ad780d90-f664-40a0-9f17-61d21ffeb013
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538065443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1538065443
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2067719825
Short name T839
Test name
Test status
Simulation time 496121509 ps
CPU time 1.72 seconds
Started Aug 13 05:54:46 PM PDT 24
Finished Aug 13 05:54:48 PM PDT 24
Peak memory 200872 kb
Host smart-afd3439f-2316-406c-8736-d29c09d9d972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067719825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2067719825
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2738130523
Short name T818
Test name
Test status
Simulation time 451232569 ps
CPU time 1.69 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:54:58 PM PDT 24
Peak memory 200876 kb
Host smart-0e0df09a-a07d-4084-a07d-f2cb8cb6d086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738130523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2738130523
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3353852976
Short name T856
Test name
Test status
Simulation time 398689463 ps
CPU time 0.89 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:54:57 PM PDT 24
Peak memory 200884 kb
Host smart-98353541-ae6a-441d-92c8-8c7a22b6a5e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353852976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3353852976
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3940623347
Short name T908
Test name
Test status
Simulation time 527258817 ps
CPU time 1.68 seconds
Started Aug 13 05:54:57 PM PDT 24
Finished Aug 13 05:54:59 PM PDT 24
Peak memory 200900 kb
Host smart-5249db23-4b90-44f8-ad9e-4f3fbc0b8df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940623347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3940623347
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4081961143
Short name T844
Test name
Test status
Simulation time 311257648 ps
CPU time 1.39 seconds
Started Aug 13 05:54:55 PM PDT 24
Finished Aug 13 05:54:57 PM PDT 24
Peak memory 200892 kb
Host smart-6557be55-ff88-4e5f-82c1-4c53c127cbea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081961143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4081961143
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.4074118587
Short name T801
Test name
Test status
Simulation time 465907035 ps
CPU time 1.65 seconds
Started Aug 13 05:55:00 PM PDT 24
Finished Aug 13 05:55:02 PM PDT 24
Peak memory 200852 kb
Host smart-fe61aade-e393-4830-9991-f3d30f271a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074118587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.4074118587
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3772069740
Short name T805
Test name
Test status
Simulation time 496626825 ps
CPU time 0.81 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:54:57 PM PDT 24
Peak memory 200896 kb
Host smart-bfec3cf2-5f08-4b73-aa68-7532b3ab691f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772069740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3772069740
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3529884077
Short name T812
Test name
Test status
Simulation time 467224768 ps
CPU time 0.9 seconds
Started Aug 13 05:54:54 PM PDT 24
Finished Aug 13 05:54:55 PM PDT 24
Peak memory 200880 kb
Host smart-a01b8639-dfa5-43c0-bde9-26b36d9cfdc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529884077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3529884077
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2893516502
Short name T802
Test name
Test status
Simulation time 298190257 ps
CPU time 1.31 seconds
Started Aug 13 05:54:55 PM PDT 24
Finished Aug 13 05:54:56 PM PDT 24
Peak memory 200912 kb
Host smart-5a3c4518-c0ce-44c2-b9ff-5d797c83c2e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893516502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2893516502
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2495623024
Short name T811
Test name
Test status
Simulation time 397566566 ps
CPU time 0.85 seconds
Started Aug 13 05:54:57 PM PDT 24
Finished Aug 13 05:54:58 PM PDT 24
Peak memory 200924 kb
Host smart-5c61b251-5c15-4731-b566-9be0b0902888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495623024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2495623024
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3620515161
Short name T892
Test name
Test status
Simulation time 481362784 ps
CPU time 2.01 seconds
Started Aug 13 05:54:20 PM PDT 24
Finished Aug 13 05:54:22 PM PDT 24
Peak memory 201000 kb
Host smart-d6f6036c-d61c-4bdb-86e2-f3a195f197cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620515161 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3620515161
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1838127966
Short name T125
Test name
Test status
Simulation time 593049427 ps
CPU time 0.81 seconds
Started Aug 13 05:54:19 PM PDT 24
Finished Aug 13 05:54:20 PM PDT 24
Peak memory 200180 kb
Host smart-9be1568e-46af-4189-ac56-c8500da06b35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838127966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1838127966
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3194585518
Short name T837
Test name
Test status
Simulation time 396918219 ps
CPU time 1.47 seconds
Started Aug 13 05:54:20 PM PDT 24
Finished Aug 13 05:54:21 PM PDT 24
Peak memory 200840 kb
Host smart-b49ac068-37ba-427f-a197-54a556db10ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194585518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3194585518
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1850873584
Short name T873
Test name
Test status
Simulation time 5085000568 ps
CPU time 3.72 seconds
Started Aug 13 05:54:19 PM PDT 24
Finished Aug 13 05:54:23 PM PDT 24
Peak memory 201236 kb
Host smart-19fd795f-15e8-4ebc-91c2-4e06e59e8d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850873584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1850873584
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4110795477
Short name T836
Test name
Test status
Simulation time 484831686 ps
CPU time 3.78 seconds
Started Aug 13 05:54:20 PM PDT 24
Finished Aug 13 05:54:24 PM PDT 24
Peak memory 217196 kb
Host smart-317486bb-80c7-476a-a823-1b1a9951b7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110795477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4110795477
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2794953227
Short name T833
Test name
Test status
Simulation time 460330569 ps
CPU time 1.16 seconds
Started Aug 13 05:54:19 PM PDT 24
Finished Aug 13 05:54:21 PM PDT 24
Peak memory 200988 kb
Host smart-f421d51b-d9b9-4853-93be-4e1ac1f31962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794953227 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2794953227
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1054596088
Short name T132
Test name
Test status
Simulation time 375976237 ps
CPU time 1.73 seconds
Started Aug 13 05:54:19 PM PDT 24
Finished Aug 13 05:54:21 PM PDT 24
Peak memory 200988 kb
Host smart-525b7be1-2648-48a6-83b4-d1328e7dddfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054596088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1054596088
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.966321956
Short name T813
Test name
Test status
Simulation time 288893998 ps
CPU time 1.28 seconds
Started Aug 13 05:54:21 PM PDT 24
Finished Aug 13 05:54:22 PM PDT 24
Peak memory 200848 kb
Host smart-14a0ebd5-0bb9-419e-9de7-a0e02f851d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966321956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.966321956
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2850679553
Short name T916
Test name
Test status
Simulation time 4329238662 ps
CPU time 17.05 seconds
Started Aug 13 05:54:20 PM PDT 24
Finished Aug 13 05:54:37 PM PDT 24
Peak memory 201128 kb
Host smart-d78b2e55-637e-4b2b-870d-81ef712e0408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850679553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2850679553
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2528593368
Short name T81
Test name
Test status
Simulation time 460691281 ps
CPU time 1.62 seconds
Started Aug 13 05:54:21 PM PDT 24
Finished Aug 13 05:54:23 PM PDT 24
Peak memory 201212 kb
Host smart-63e86d2a-a18c-44af-9b53-7ffdefe7857e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528593368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2528593368
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.991341351
Short name T835
Test name
Test status
Simulation time 8546865220 ps
CPU time 17.78 seconds
Started Aug 13 05:54:20 PM PDT 24
Finished Aug 13 05:54:37 PM PDT 24
Peak memory 201172 kb
Host smart-214deb3a-387a-4835-9be6-20a558e9aa57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991341351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.991341351
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.702591984
Short name T890
Test name
Test status
Simulation time 568711445 ps
CPU time 1.24 seconds
Started Aug 13 05:54:20 PM PDT 24
Finished Aug 13 05:54:22 PM PDT 24
Peak memory 201028 kb
Host smart-d0ed5c0e-0ff8-49e8-b1c3-eb48da96d53c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702591984 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.702591984
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2682664758
Short name T878
Test name
Test status
Simulation time 321806579 ps
CPU time 1.14 seconds
Started Aug 13 05:54:21 PM PDT 24
Finished Aug 13 05:54:22 PM PDT 24
Peak memory 200944 kb
Host smart-b8b05e6c-116c-40ad-9d2e-c175775288f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682664758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2682664758
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3012961380
Short name T905
Test name
Test status
Simulation time 401299549 ps
CPU time 0.77 seconds
Started Aug 13 05:54:20 PM PDT 24
Finished Aug 13 05:54:21 PM PDT 24
Peak memory 200848 kb
Host smart-fda71e29-ee9d-4a08-b174-0488aff48cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012961380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3012961380
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3634392204
Short name T880
Test name
Test status
Simulation time 4068222620 ps
CPU time 6.24 seconds
Started Aug 13 05:54:20 PM PDT 24
Finished Aug 13 05:54:27 PM PDT 24
Peak memory 201176 kb
Host smart-371a88c2-0099-42f2-9dee-d91983bc43ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634392204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3634392204
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3142403469
Short name T74
Test name
Test status
Simulation time 330725116 ps
CPU time 2.29 seconds
Started Aug 13 05:54:19 PM PDT 24
Finished Aug 13 05:54:21 PM PDT 24
Peak memory 217528 kb
Host smart-cb6dccdf-0fcb-4450-8dfe-c56a6f3edb12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142403469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3142403469
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1254856011
Short name T907
Test name
Test status
Simulation time 3883447257 ps
CPU time 10.18 seconds
Started Aug 13 05:54:19 PM PDT 24
Finished Aug 13 05:54:30 PM PDT 24
Peak memory 201200 kb
Host smart-a7ab79b0-3435-4b43-bd3a-b02522af2897
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254856011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1254856011
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1739631880
Short name T919
Test name
Test status
Simulation time 613644266 ps
CPU time 1.2 seconds
Started Aug 13 05:54:30 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 201028 kb
Host smart-575f3254-456d-4a9e-84f2-f88be68d4437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739631880 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1739631880
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.373774505
Short name T128
Test name
Test status
Simulation time 552220360 ps
CPU time 1.24 seconds
Started Aug 13 05:54:29 PM PDT 24
Finished Aug 13 05:54:30 PM PDT 24
Peak memory 200992 kb
Host smart-57661120-dfee-41cd-9b20-04e67a51d671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373774505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.373774505
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.910529085
Short name T804
Test name
Test status
Simulation time 511637424 ps
CPU time 0.76 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:29 PM PDT 24
Peak memory 200904 kb
Host smart-af3d6e13-5f50-4804-9199-9217cfcc1b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910529085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.910529085
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4043723868
Short name T903
Test name
Test status
Simulation time 4487129669 ps
CPU time 2.74 seconds
Started Aug 13 05:54:27 PM PDT 24
Finished Aug 13 05:54:30 PM PDT 24
Peak memory 201124 kb
Host smart-a3008b70-e9e6-44a0-b6ae-66f3d7ccd786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043723868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.4043723868
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.189752979
Short name T900
Test name
Test status
Simulation time 858942758 ps
CPU time 1.46 seconds
Started Aug 13 05:54:20 PM PDT 24
Finished Aug 13 05:54:22 PM PDT 24
Peak memory 201220 kb
Host smart-fa6346e3-b96c-44d0-9ece-7001a30de60c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189752979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.189752979
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3555084330
Short name T857
Test name
Test status
Simulation time 8403624970 ps
CPU time 7.7 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:35 PM PDT 24
Peak memory 201192 kb
Host smart-53115946-9882-4ee6-8a93-02d19ceecdd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555084330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3555084330
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.274776099
Short name T854
Test name
Test status
Simulation time 627707414 ps
CPU time 1.44 seconds
Started Aug 13 05:54:30 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 201028 kb
Host smart-f3217bb9-7b95-437b-9b14-96950d6db3a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274776099 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.274776099
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3945922421
Short name T853
Test name
Test status
Simulation time 515717356 ps
CPU time 0.98 seconds
Started Aug 13 05:54:29 PM PDT 24
Finished Aug 13 05:54:30 PM PDT 24
Peak memory 200988 kb
Host smart-4d2b8aaf-6938-41b6-bd49-5fcc2abfed0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945922421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3945922421
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3000046517
Short name T821
Test name
Test status
Simulation time 444877869 ps
CPU time 0.72 seconds
Started Aug 13 05:54:27 PM PDT 24
Finished Aug 13 05:54:28 PM PDT 24
Peak memory 200824 kb
Host smart-234764c5-c48a-4ae3-8b53-0a64328ceb43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000046517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3000046517
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3510524685
Short name T906
Test name
Test status
Simulation time 4471379861 ps
CPU time 10.78 seconds
Started Aug 13 05:54:27 PM PDT 24
Finished Aug 13 05:54:38 PM PDT 24
Peak memory 201232 kb
Host smart-8017a751-17c9-4d6d-bdae-49002db0fa1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510524685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3510524685
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3789392535
Short name T86
Test name
Test status
Simulation time 782222843 ps
CPU time 2.17 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 201120 kb
Host smart-fc54336f-5ee8-4dd5-8a89-7226553ca5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789392535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3789392535
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.433849442
Short name T866
Test name
Test status
Simulation time 8447978181 ps
CPU time 20.71 seconds
Started Aug 13 05:54:28 PM PDT 24
Finished Aug 13 05:54:49 PM PDT 24
Peak memory 201188 kb
Host smart-966d323d-d0cb-4715-be95-adbaa3990f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433849442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.433849442
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2950935227
Short name T492
Test name
Test status
Simulation time 306482042 ps
CPU time 1.31 seconds
Started Aug 13 06:00:46 PM PDT 24
Finished Aug 13 06:00:47 PM PDT 24
Peak memory 202012 kb
Host smart-c980f2ae-cb1f-4a35-9b93-fdf566860cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950935227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2950935227
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1110603662
Short name T358
Test name
Test status
Simulation time 321380504579 ps
CPU time 731.36 seconds
Started Aug 13 06:00:43 PM PDT 24
Finished Aug 13 06:12:55 PM PDT 24
Peak memory 202112 kb
Host smart-c0af1d14-9d6d-4a34-9306-e0f84d41dc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110603662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1110603662
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4037467464
Short name T441
Test name
Test status
Simulation time 485500655165 ps
CPU time 1064.38 seconds
Started Aug 13 06:00:45 PM PDT 24
Finished Aug 13 06:18:29 PM PDT 24
Peak memory 202172 kb
Host smart-55ad3ea0-6d1a-461e-a641-9cf3e65accfe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037467464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4037467464
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1595475831
Short name T106
Test name
Test status
Simulation time 162661644352 ps
CPU time 178.49 seconds
Started Aug 13 06:00:43 PM PDT 24
Finished Aug 13 06:03:42 PM PDT 24
Peak memory 202156 kb
Host smart-03e72de6-46ab-4466-b5f8-58ad9c4e1935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595475831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1595475831
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.657512873
Short name T746
Test name
Test status
Simulation time 322368931744 ps
CPU time 703.22 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:12:28 PM PDT 24
Peak memory 202116 kb
Host smart-091422fe-f45d-4199-8fb0-853d3b7de627
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=657512873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.657512873
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1932661537
Short name T572
Test name
Test status
Simulation time 597343959614 ps
CPU time 348.44 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:06:33 PM PDT 24
Peak memory 202144 kb
Host smart-4b6fcc97-c615-451e-9d12-8053b077a41b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932661537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1932661537
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2194217247
Short name T600
Test name
Test status
Simulation time 603607882720 ps
CPU time 348.03 seconds
Started Aug 13 06:00:46 PM PDT 24
Finished Aug 13 06:06:34 PM PDT 24
Peak memory 202176 kb
Host smart-1a6eeae0-397f-47d5-a56a-f23dbedfea00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194217247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2194217247
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2675438827
Short name T610
Test name
Test status
Simulation time 123424569428 ps
CPU time 549.26 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:09:53 PM PDT 24
Peak memory 202416 kb
Host smart-4d4b4851-0528-4600-ae0b-4f70908906b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675438827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2675438827
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1076354374
Short name T476
Test name
Test status
Simulation time 45322449240 ps
CPU time 50.1 seconds
Started Aug 13 06:00:43 PM PDT 24
Finished Aug 13 06:01:33 PM PDT 24
Peak memory 201856 kb
Host smart-976b63ad-66e8-489e-a08f-b50eb1d7cc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076354374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1076354374
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2225274866
Short name T781
Test name
Test status
Simulation time 4250164419 ps
CPU time 10.55 seconds
Started Aug 13 06:00:46 PM PDT 24
Finished Aug 13 06:00:56 PM PDT 24
Peak memory 201992 kb
Host smart-9ce88721-79dd-4949-a322-8e1d76f819c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225274866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2225274866
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3286676858
Short name T10
Test name
Test status
Simulation time 5941366316 ps
CPU time 4.74 seconds
Started Aug 13 06:00:36 PM PDT 24
Finished Aug 13 06:00:41 PM PDT 24
Peak memory 201960 kb
Host smart-acd1caac-6c51-400b-b5a6-6209dd7cf2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286676858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3286676858
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1194325366
Short name T798
Test name
Test status
Simulation time 6585532017 ps
CPU time 6.58 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:00:50 PM PDT 24
Peak memory 202196 kb
Host smart-f7471b8d-3e18-4b97-9a98-637e6dc7f71a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194325366 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1194325366
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3864397617
Short name T707
Test name
Test status
Simulation time 340832507 ps
CPU time 1.36 seconds
Started Aug 13 06:00:53 PM PDT 24
Finished Aug 13 06:00:55 PM PDT 24
Peak memory 201960 kb
Host smart-31a1f163-93b5-43ee-95b1-c59755d0f279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864397617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3864397617
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1711610658
Short name T70
Test name
Test status
Simulation time 354190351437 ps
CPU time 386.52 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:07:11 PM PDT 24
Peak memory 202140 kb
Host smart-ebb116ea-ef1d-4db3-9566-7b9f93198d07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711610658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1711610658
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.885836371
Short name T309
Test name
Test status
Simulation time 324561112948 ps
CPU time 193.91 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:03:59 PM PDT 24
Peak memory 202148 kb
Host smart-a67288fc-b9b9-4c94-b879-9c5f943b7e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885836371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.885836371
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2933634796
Short name T296
Test name
Test status
Simulation time 495513331291 ps
CPU time 989.7 seconds
Started Aug 13 06:00:47 PM PDT 24
Finished Aug 13 06:17:17 PM PDT 24
Peak memory 202056 kb
Host smart-bb357b64-9cc5-43db-8f84-5507fcb968fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933634796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2933634796
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2763828984
Short name T390
Test name
Test status
Simulation time 327156696704 ps
CPU time 209.01 seconds
Started Aug 13 06:00:41 PM PDT 24
Finished Aug 13 06:04:10 PM PDT 24
Peak memory 202076 kb
Host smart-699fddd1-35d8-4cae-af6e-959b00e2e59f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763828984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2763828984
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1100244681
Short name T218
Test name
Test status
Simulation time 492464573196 ps
CPU time 256.46 seconds
Started Aug 13 06:00:41 PM PDT 24
Finished Aug 13 06:04:58 PM PDT 24
Peak memory 202120 kb
Host smart-23a599b2-da5b-4253-9716-ffcd88941a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100244681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1100244681
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1214719447
Short name T700
Test name
Test status
Simulation time 330058796275 ps
CPU time 373.92 seconds
Started Aug 13 06:00:43 PM PDT 24
Finished Aug 13 06:06:57 PM PDT 24
Peak memory 202120 kb
Host smart-bef28b37-b948-41a1-8014-238143cc7c89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214719447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1214719447
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3535593664
Short name T340
Test name
Test status
Simulation time 173241592027 ps
CPU time 105.74 seconds
Started Aug 13 06:00:47 PM PDT 24
Finished Aug 13 06:02:33 PM PDT 24
Peak memory 202044 kb
Host smart-553cbef5-adbc-445b-8f1d-e094c18d3e0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535593664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3535593664
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1831124836
Short name T589
Test name
Test status
Simulation time 606283457265 ps
CPU time 446.73 seconds
Started Aug 13 06:00:44 PM PDT 24
Finished Aug 13 06:08:11 PM PDT 24
Peak memory 202160 kb
Host smart-798073bb-ca1c-4e38-8a86-395aa07b1a13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831124836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1831124836
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.433471738
Short name T669
Test name
Test status
Simulation time 109903505686 ps
CPU time 567.43 seconds
Started Aug 13 06:00:56 PM PDT 24
Finished Aug 13 06:10:23 PM PDT 24
Peak memory 202380 kb
Host smart-d5b57536-3639-40c5-a34b-7ab5c078f28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433471738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.433471738
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1903136457
Short name T442
Test name
Test status
Simulation time 43306289738 ps
CPU time 94.87 seconds
Started Aug 13 06:00:54 PM PDT 24
Finished Aug 13 06:02:29 PM PDT 24
Peak memory 201948 kb
Host smart-13013fd4-faa1-4c01-94c0-4175c71ec847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903136457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1903136457
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3970361549
Short name T205
Test name
Test status
Simulation time 3728836680 ps
CPU time 2.6 seconds
Started Aug 13 06:00:53 PM PDT 24
Finished Aug 13 06:00:55 PM PDT 24
Peak memory 201904 kb
Host smart-6e604ec5-7380-4cc2-98fb-2533026e655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970361549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3970361549
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2929007614
Short name T90
Test name
Test status
Simulation time 4185845765 ps
CPU time 5.63 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:00:57 PM PDT 24
Peak memory 217432 kb
Host smart-4cd670ab-9dd5-4c64-b40b-ca7496945b31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929007614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2929007614
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.403342550
Short name T433
Test name
Test status
Simulation time 5799645019 ps
CPU time 1.59 seconds
Started Aug 13 06:00:47 PM PDT 24
Finished Aug 13 06:00:49 PM PDT 24
Peak memory 201900 kb
Host smart-929d0ff6-d0f5-450f-80a9-8181256cef3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403342550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.403342550
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.709675059
Short name T292
Test name
Test status
Simulation time 234970750790 ps
CPU time 121.12 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:02:53 PM PDT 24
Peak memory 202140 kb
Host smart-7ca5e8ff-67a2-43fb-a7b8-890d1a2fa3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709675059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.709675059
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1697005309
Short name T532
Test name
Test status
Simulation time 3780306918 ps
CPU time 11.28 seconds
Started Aug 13 06:00:53 PM PDT 24
Finished Aug 13 06:01:05 PM PDT 24
Peak memory 210492 kb
Host smart-b898db44-5243-4f80-bce6-586f02f2e223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697005309 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1697005309
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2956361432
Short name T120
Test name
Test status
Simulation time 506337968 ps
CPU time 0.9 seconds
Started Aug 13 06:01:46 PM PDT 24
Finished Aug 13 06:01:47 PM PDT 24
Peak memory 201964 kb
Host smart-3ed32769-41fc-4f5b-80c1-dda1578d0d85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956361432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2956361432
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2983228263
Short name T588
Test name
Test status
Simulation time 324724879183 ps
CPU time 73.43 seconds
Started Aug 13 06:01:47 PM PDT 24
Finished Aug 13 06:03:01 PM PDT 24
Peak memory 202136 kb
Host smart-3309a1ca-092c-47be-a97c-001e5b3af455
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983228263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2983228263
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1868630127
Short name T722
Test name
Test status
Simulation time 163614461851 ps
CPU time 208.08 seconds
Started Aug 13 06:01:45 PM PDT 24
Finished Aug 13 06:05:13 PM PDT 24
Peak memory 202128 kb
Host smart-fa6c21e7-4e95-462b-8e27-adeab20f8a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868630127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1868630127
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3531573576
Short name T435
Test name
Test status
Simulation time 335013132929 ps
CPU time 813.51 seconds
Started Aug 13 06:01:47 PM PDT 24
Finished Aug 13 06:15:21 PM PDT 24
Peak memory 202100 kb
Host smart-fc3ae599-ff32-49e5-8824-77fc2a6a7bce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531573576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3531573576
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1179673919
Short name T319
Test name
Test status
Simulation time 316364076294 ps
CPU time 153.32 seconds
Started Aug 13 06:01:46 PM PDT 24
Finished Aug 13 06:04:19 PM PDT 24
Peak memory 202112 kb
Host smart-7b6295cf-2559-4944-ad49-60f3e5011bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179673919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1179673919
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3461022219
Short name T421
Test name
Test status
Simulation time 319519756498 ps
CPU time 747.47 seconds
Started Aug 13 06:01:44 PM PDT 24
Finished Aug 13 06:14:12 PM PDT 24
Peak memory 202112 kb
Host smart-1fc74fb3-6221-4268-a050-adff37814a5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461022219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3461022219
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3737236516
Short name T699
Test name
Test status
Simulation time 553022830983 ps
CPU time 1255.09 seconds
Started Aug 13 06:01:49 PM PDT 24
Finished Aug 13 06:22:45 PM PDT 24
Peak memory 202132 kb
Host smart-709fa118-fc44-4da2-b352-e31bec488c56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737236516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3737236516
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2226688844
Short name T567
Test name
Test status
Simulation time 205384583738 ps
CPU time 464.32 seconds
Started Aug 13 06:01:46 PM PDT 24
Finished Aug 13 06:09:31 PM PDT 24
Peak memory 202164 kb
Host smart-10cb0054-a2e3-4384-8893-e5a8b26eccec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226688844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2226688844
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.26464594
Short name T701
Test name
Test status
Simulation time 24272347889 ps
CPU time 28.28 seconds
Started Aug 13 06:01:49 PM PDT 24
Finished Aug 13 06:02:17 PM PDT 24
Peak memory 201916 kb
Host smart-7a521a59-790b-479d-957c-b3e4ec6f613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26464594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.26464594
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3998860467
Short name T531
Test name
Test status
Simulation time 4126383514 ps
CPU time 2.65 seconds
Started Aug 13 06:01:45 PM PDT 24
Finished Aug 13 06:01:48 PM PDT 24
Peak memory 201952 kb
Host smart-4fc01a92-30aa-4b1b-8bfd-9a23c7b18cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998860467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3998860467
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2223938781
Short name T367
Test name
Test status
Simulation time 6070403594 ps
CPU time 5.78 seconds
Started Aug 13 06:01:34 PM PDT 24
Finished Aug 13 06:01:40 PM PDT 24
Peak memory 201976 kb
Host smart-0a41b1fc-9874-4c47-aef7-1860213a28e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223938781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2223938781
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1843668859
Short name T783
Test name
Test status
Simulation time 346622072 ps
CPU time 0.84 seconds
Started Aug 13 06:02:02 PM PDT 24
Finished Aug 13 06:02:03 PM PDT 24
Peak memory 201944 kb
Host smart-cc5348ab-5b66-49eb-8815-167d0e7ae38f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843668859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1843668859
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2393606468
Short name T268
Test name
Test status
Simulation time 326128935835 ps
CPU time 706.41 seconds
Started Aug 13 06:01:55 PM PDT 24
Finished Aug 13 06:13:42 PM PDT 24
Peak memory 202148 kb
Host smart-6aa2a942-437f-4a2c-b33a-d912a2968de5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393606468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2393606468
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2845362156
Short name T777
Test name
Test status
Simulation time 491738598745 ps
CPU time 1011.02 seconds
Started Aug 13 06:02:02 PM PDT 24
Finished Aug 13 06:18:53 PM PDT 24
Peak memory 202144 kb
Host smart-6bfdcdc8-3b0f-429b-80c4-6f7b6b3bd311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845362156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2845362156
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.4087345676
Short name T653
Test name
Test status
Simulation time 331824182424 ps
CPU time 729.04 seconds
Started Aug 13 06:01:48 PM PDT 24
Finished Aug 13 06:13:57 PM PDT 24
Peak memory 202156 kb
Host smart-de1b6f02-dbfc-4f7d-a18e-885614dfaa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087345676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4087345676
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.4128892187
Short name T720
Test name
Test status
Simulation time 321671513219 ps
CPU time 197.98 seconds
Started Aug 13 06:01:47 PM PDT 24
Finished Aug 13 06:05:05 PM PDT 24
Peak memory 202112 kb
Host smart-c07f9805-2c2b-483a-9aea-8607eea4114f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128892187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.4128892187
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.4101032256
Short name T270
Test name
Test status
Simulation time 521251865326 ps
CPU time 626.05 seconds
Started Aug 13 06:01:57 PM PDT 24
Finished Aug 13 06:12:23 PM PDT 24
Peak memory 202044 kb
Host smart-56647ee5-88d1-40b4-9a94-40f022dcbdab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101032256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.4101032256
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3020194610
Short name T507
Test name
Test status
Simulation time 396098510514 ps
CPU time 443.71 seconds
Started Aug 13 06:01:56 PM PDT 24
Finished Aug 13 06:09:20 PM PDT 24
Peak memory 202124 kb
Host smart-751a3d44-d656-4d56-8009-f4fc974dd286
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020194610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3020194610
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1136585390
Short name T635
Test name
Test status
Simulation time 75053682489 ps
CPU time 330.34 seconds
Started Aug 13 06:02:03 PM PDT 24
Finished Aug 13 06:07:33 PM PDT 24
Peak memory 202408 kb
Host smart-357d0ed9-390c-4959-b31d-99e4235da92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136585390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1136585390
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.4230790228
Short name T651
Test name
Test status
Simulation time 44122548460 ps
CPU time 22.07 seconds
Started Aug 13 06:02:01 PM PDT 24
Finished Aug 13 06:02:23 PM PDT 24
Peak memory 201944 kb
Host smart-617e770b-8471-4e75-8be9-395c06ee69be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230790228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.4230790228
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.541042779
Short name T30
Test name
Test status
Simulation time 5201972330 ps
CPU time 12.38 seconds
Started Aug 13 06:01:59 PM PDT 24
Finished Aug 13 06:02:12 PM PDT 24
Peak memory 201876 kb
Host smart-ea2f8e4f-a0d8-4a16-a911-8da0b3179f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541042779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.541042779
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.582326855
Short name T702
Test name
Test status
Simulation time 5744444349 ps
CPU time 4.35 seconds
Started Aug 13 06:01:49 PM PDT 24
Finished Aug 13 06:01:53 PM PDT 24
Peak memory 201960 kb
Host smart-e5f01ce7-6ab8-4fa7-9368-fda394878d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582326855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.582326855
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1978607501
Short name T60
Test name
Test status
Simulation time 847952013766 ps
CPU time 1722.64 seconds
Started Aug 13 06:02:02 PM PDT 24
Finished Aug 13 06:30:45 PM PDT 24
Peak memory 210580 kb
Host smart-8490e03b-422a-4eff-aa8c-6c78f4e764a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978607501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1978607501
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3697178482
Short name T797
Test name
Test status
Simulation time 309794336 ps
CPU time 0.77 seconds
Started Aug 13 06:02:06 PM PDT 24
Finished Aug 13 06:02:07 PM PDT 24
Peak memory 201988 kb
Host smart-a1dba9cf-c0dd-42d6-8476-f0dd87e0294d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697178482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3697178482
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.638006855
Short name T314
Test name
Test status
Simulation time 501180544916 ps
CPU time 540.54 seconds
Started Aug 13 06:02:05 PM PDT 24
Finished Aug 13 06:11:06 PM PDT 24
Peak memory 202068 kb
Host smart-93b9a795-edb3-4017-86b6-df086dee6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638006855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.638006855
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2265833978
Short name T212
Test name
Test status
Simulation time 333169008778 ps
CPU time 190.01 seconds
Started Aug 13 06:01:55 PM PDT 24
Finished Aug 13 06:05:06 PM PDT 24
Peak memory 202136 kb
Host smart-6764de94-f97f-4c8a-99aa-b2ab0cfdff87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265833978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2265833978
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2527780724
Short name T450
Test name
Test status
Simulation time 496579541871 ps
CPU time 322.72 seconds
Started Aug 13 06:02:04 PM PDT 24
Finished Aug 13 06:07:27 PM PDT 24
Peak memory 202160 kb
Host smart-93573bc0-b49e-49cc-9867-2781e0abe4a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527780724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2527780724
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3802937854
Short name T278
Test name
Test status
Simulation time 340401057013 ps
CPU time 753.54 seconds
Started Aug 13 06:01:54 PM PDT 24
Finished Aug 13 06:14:28 PM PDT 24
Peak memory 202148 kb
Host smart-3c9c6d23-eed9-42b0-b0a1-614940ca6c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802937854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3802937854
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2011246812
Short name T533
Test name
Test status
Simulation time 167293380016 ps
CPU time 104.07 seconds
Started Aug 13 06:01:51 PM PDT 24
Finished Aug 13 06:03:35 PM PDT 24
Peak memory 202116 kb
Host smart-94b7f21c-2a56-4ff7-84b4-c9a253e50139
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011246812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2011246812
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.719809765
Short name T691
Test name
Test status
Simulation time 166377038303 ps
CPU time 196.97 seconds
Started Aug 13 06:02:03 PM PDT 24
Finished Aug 13 06:05:20 PM PDT 24
Peak memory 202120 kb
Host smart-738541ba-728f-4f77-a30b-8299bee26d04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719809765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.719809765
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.258199017
Short name T786
Test name
Test status
Simulation time 603561277567 ps
CPU time 354.25 seconds
Started Aug 13 06:02:07 PM PDT 24
Finished Aug 13 06:08:01 PM PDT 24
Peak memory 202216 kb
Host smart-015c9cc8-b000-4c80-be87-889c69f12a85
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258199017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.258199017
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1410103080
Short name T505
Test name
Test status
Simulation time 82852727808 ps
CPU time 265.68 seconds
Started Aug 13 06:02:07 PM PDT 24
Finished Aug 13 06:06:32 PM PDT 24
Peak memory 202372 kb
Host smart-76f1bd22-6ba5-435a-9ffd-c6d1043b5976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410103080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1410103080
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3134263844
Short name T606
Test name
Test status
Simulation time 24662885426 ps
CPU time 14.68 seconds
Started Aug 13 06:02:12 PM PDT 24
Finished Aug 13 06:02:26 PM PDT 24
Peak memory 201940 kb
Host smart-d308c323-1445-4ae3-b6e1-f3a5bc44e89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134263844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3134263844
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2813310176
Short name T434
Test name
Test status
Simulation time 2889778309 ps
CPU time 2.29 seconds
Started Aug 13 06:02:11 PM PDT 24
Finished Aug 13 06:02:13 PM PDT 24
Peak memory 201984 kb
Host smart-6a164d35-783a-48c6-85ae-77ac0ec313bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813310176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2813310176
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3220451110
Short name T604
Test name
Test status
Simulation time 5515628729 ps
CPU time 6.9 seconds
Started Aug 13 06:01:56 PM PDT 24
Finished Aug 13 06:02:03 PM PDT 24
Peak memory 201960 kb
Host smart-44c2e6a3-f985-4994-a893-2b9d791858df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220451110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3220451110
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3236433041
Short name T436
Test name
Test status
Simulation time 6432931531 ps
CPU time 4.27 seconds
Started Aug 13 06:02:06 PM PDT 24
Finished Aug 13 06:02:10 PM PDT 24
Peak memory 202260 kb
Host smart-3add7223-87c6-41d1-b209-438bc4290f07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236433041 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3236433041
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1227078657
Short name T209
Test name
Test status
Simulation time 426518826 ps
CPU time 0.88 seconds
Started Aug 13 06:02:18 PM PDT 24
Finished Aug 13 06:02:19 PM PDT 24
Peak memory 201900 kb
Host smart-94723bc5-f60e-4d53-ac5e-6c7e86047a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227078657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1227078657
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.637391222
Short name T673
Test name
Test status
Simulation time 432072104309 ps
CPU time 1025.86 seconds
Started Aug 13 06:02:01 PM PDT 24
Finished Aug 13 06:19:07 PM PDT 24
Peak memory 202104 kb
Host smart-9352bd3d-bdd2-4519-a7a1-dbfd789c9e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637391222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.637391222
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.538722893
Short name T345
Test name
Test status
Simulation time 503686184148 ps
CPU time 293.72 seconds
Started Aug 13 06:02:05 PM PDT 24
Finished Aug 13 06:06:59 PM PDT 24
Peak memory 202064 kb
Host smart-8a5b0a1b-4ef9-444a-ba93-eaf5cca11f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538722893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.538722893
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.912529210
Short name T791
Test name
Test status
Simulation time 164785609209 ps
CPU time 307.31 seconds
Started Aug 13 06:02:13 PM PDT 24
Finished Aug 13 06:07:20 PM PDT 24
Peak memory 202116 kb
Host smart-8e513e90-4738-46fe-becf-614e22733ddd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=912529210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.912529210
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3201276566
Short name T405
Test name
Test status
Simulation time 164215539705 ps
CPU time 376.59 seconds
Started Aug 13 06:02:13 PM PDT 24
Finished Aug 13 06:08:30 PM PDT 24
Peak memory 202160 kb
Host smart-60548de7-2b58-43ae-8dfa-a5e70fb21a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201276566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3201276566
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.459100503
Short name T552
Test name
Test status
Simulation time 482977122806 ps
CPU time 528.11 seconds
Started Aug 13 06:02:06 PM PDT 24
Finished Aug 13 06:10:54 PM PDT 24
Peak memory 202124 kb
Host smart-4560f114-53b2-4c72-beb0-76751b0af0df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=459100503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.459100503
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3271080966
Short name T667
Test name
Test status
Simulation time 207816731266 ps
CPU time 114.89 seconds
Started Aug 13 06:02:12 PM PDT 24
Finished Aug 13 06:04:07 PM PDT 24
Peak memory 202100 kb
Host smart-1e1afdc6-c5dc-4483-9706-20b07fb3616f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271080966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3271080966
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.182086306
Short name T634
Test name
Test status
Simulation time 610299457766 ps
CPU time 361.93 seconds
Started Aug 13 06:02:07 PM PDT 24
Finished Aug 13 06:08:09 PM PDT 24
Peak memory 202148 kb
Host smart-2c7b8e7c-8309-4350-bd5b-991e2931e171
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182086306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.182086306
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3484495924
Short name T740
Test name
Test status
Simulation time 24902439899 ps
CPU time 9.94 seconds
Started Aug 13 06:02:17 PM PDT 24
Finished Aug 13 06:02:27 PM PDT 24
Peak memory 201876 kb
Host smart-2628f40d-1937-4286-a571-0d8c1a45730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484495924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3484495924
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4105564415
Short name T117
Test name
Test status
Simulation time 5159476816 ps
CPU time 3.1 seconds
Started Aug 13 06:02:05 PM PDT 24
Finished Aug 13 06:02:08 PM PDT 24
Peak memory 201972 kb
Host smart-d5d8236f-27cf-4a3c-bfb1-a0f91a52d3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105564415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4105564415
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2982563365
Short name T677
Test name
Test status
Simulation time 6134084698 ps
CPU time 3.3 seconds
Started Aug 13 06:02:08 PM PDT 24
Finished Aug 13 06:02:11 PM PDT 24
Peak memory 201928 kb
Host smart-d42f682b-97d3-454a-9328-0ef89624093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982563365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2982563365
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1366454355
Short name T515
Test name
Test status
Simulation time 53578659493 ps
CPU time 123.6 seconds
Started Aug 13 06:02:11 PM PDT 24
Finished Aug 13 06:04:15 PM PDT 24
Peak memory 202152 kb
Host smart-bbcf26a0-a336-482b-b099-48445214b107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366454355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1366454355
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1193522761
Short name T469
Test name
Test status
Simulation time 294280410 ps
CPU time 0.96 seconds
Started Aug 13 06:02:27 PM PDT 24
Finished Aug 13 06:02:28 PM PDT 24
Peak memory 201960 kb
Host smart-0dcd2d80-8f65-4a69-bb21-b4bfb32c3c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193522761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1193522761
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1965768698
Short name T312
Test name
Test status
Simulation time 515280881922 ps
CPU time 69.55 seconds
Started Aug 13 06:02:14 PM PDT 24
Finished Aug 13 06:03:24 PM PDT 24
Peak memory 202136 kb
Host smart-2d6f00a0-4226-4e11-940e-6a2c6e0dcca4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965768698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1965768698
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1463064111
Short name T355
Test name
Test status
Simulation time 160960279435 ps
CPU time 241.81 seconds
Started Aug 13 06:02:17 PM PDT 24
Finished Aug 13 06:06:19 PM PDT 24
Peak memory 202140 kb
Host smart-cce8cf5b-b214-42a7-892c-689673fcf1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463064111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1463064111
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.140480635
Short name T419
Test name
Test status
Simulation time 327077550228 ps
CPU time 99.13 seconds
Started Aug 13 06:02:15 PM PDT 24
Finished Aug 13 06:03:54 PM PDT 24
Peak memory 202036 kb
Host smart-60658b6b-fda9-4523-b953-97f500a8cec4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=140480635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.140480635
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3808208736
Short name T675
Test name
Test status
Simulation time 330670844120 ps
CPU time 754.22 seconds
Started Aug 13 06:02:13 PM PDT 24
Finished Aug 13 06:14:48 PM PDT 24
Peak memory 202072 kb
Host smart-59818f4f-c7ba-4695-9752-8df7b7e30b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808208736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3808208736
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1695904988
Short name T764
Test name
Test status
Simulation time 166004306395 ps
CPU time 65.85 seconds
Started Aug 13 06:02:13 PM PDT 24
Finished Aug 13 06:03:19 PM PDT 24
Peak memory 202084 kb
Host smart-98777a55-16cd-4b87-b833-ba40eff43f1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695904988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1695904988
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1076008231
Short name T202
Test name
Test status
Simulation time 354308800468 ps
CPU time 200.42 seconds
Started Aug 13 06:02:14 PM PDT 24
Finished Aug 13 06:05:34 PM PDT 24
Peak memory 202148 kb
Host smart-859eea8e-4e40-48dd-8201-f8a8f62b6ef8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076008231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1076008231
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1093288376
Short name T109
Test name
Test status
Simulation time 188152091847 ps
CPU time 392.85 seconds
Started Aug 13 06:02:13 PM PDT 24
Finished Aug 13 06:08:46 PM PDT 24
Peak memory 202220 kb
Host smart-d82677a7-e53c-403a-97c3-4aeedcd26bed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093288376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1093288376
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3995686541
Short name T236
Test name
Test status
Simulation time 124446835685 ps
CPU time 358.76 seconds
Started Aug 13 06:02:24 PM PDT 24
Finished Aug 13 06:08:23 PM PDT 24
Peak memory 202352 kb
Host smart-6b1e7b28-0948-48fa-809a-0ea8e7bc564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995686541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3995686541
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1568025096
Short name T609
Test name
Test status
Simulation time 42925704107 ps
CPU time 102.1 seconds
Started Aug 13 06:02:22 PM PDT 24
Finished Aug 13 06:04:04 PM PDT 24
Peak memory 201912 kb
Host smart-3f972b92-a278-4838-96ed-0e2740bf318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568025096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1568025096
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.868288502
Short name T501
Test name
Test status
Simulation time 3273577922 ps
CPU time 7.5 seconds
Started Aug 13 06:02:18 PM PDT 24
Finished Aug 13 06:02:26 PM PDT 24
Peak memory 201972 kb
Host smart-9c9a89f4-9029-4144-b13b-e470ee8beddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868288502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.868288502
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3184347308
Short name T585
Test name
Test status
Simulation time 5960334364 ps
CPU time 2.22 seconds
Started Aug 13 06:02:20 PM PDT 24
Finished Aug 13 06:02:22 PM PDT 24
Peak memory 201968 kb
Host smart-3a3790de-954d-4676-8da2-ec7fe7dee997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184347308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3184347308
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1383680214
Short name T671
Test name
Test status
Simulation time 361048911813 ps
CPU time 743.11 seconds
Started Aug 13 06:02:24 PM PDT 24
Finished Aug 13 06:14:47 PM PDT 24
Peak memory 202192 kb
Host smart-ca1de8f5-fe6f-4254-85cf-2e4fde5e0e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383680214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1383680214
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.806153829
Short name T253
Test name
Test status
Simulation time 10394389646 ps
CPU time 13.76 seconds
Started Aug 13 06:02:27 PM PDT 24
Finished Aug 13 06:02:40 PM PDT 24
Peak memory 210504 kb
Host smart-62361df6-2fc0-490f-8ca1-2f81a2af7d58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806153829 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.806153829
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3073623134
Short name T100
Test name
Test status
Simulation time 414073421 ps
CPU time 1.56 seconds
Started Aug 13 06:02:37 PM PDT 24
Finished Aug 13 06:02:38 PM PDT 24
Peak memory 201996 kb
Host smart-d15ecf55-f8b5-4bac-9e2e-68228241702d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073623134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3073623134
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2692371558
Short name T724
Test name
Test status
Simulation time 159585248329 ps
CPU time 10.34 seconds
Started Aug 13 06:02:21 PM PDT 24
Finished Aug 13 06:02:32 PM PDT 24
Peak memory 202136 kb
Host smart-9c4d6e80-d531-4e0d-a578-3f0ada3de166
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692371558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2692371558
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.991336286
Short name T347
Test name
Test status
Simulation time 374279365258 ps
CPU time 231.11 seconds
Started Aug 13 06:02:23 PM PDT 24
Finished Aug 13 06:06:14 PM PDT 24
Peak memory 202148 kb
Host smart-45a68960-a81e-4b5b-a04f-66df4fff101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991336286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.991336286
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3507692616
Short name T219
Test name
Test status
Simulation time 163872452423 ps
CPU time 354.79 seconds
Started Aug 13 06:02:21 PM PDT 24
Finished Aug 13 06:08:16 PM PDT 24
Peak memory 202048 kb
Host smart-2fb593d0-66df-4cfe-8262-ea06401cc52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507692616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3507692616
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3452242161
Short name T97
Test name
Test status
Simulation time 168902366354 ps
CPU time 194.13 seconds
Started Aug 13 06:02:23 PM PDT 24
Finished Aug 13 06:05:37 PM PDT 24
Peak memory 202140 kb
Host smart-f1c5e603-73e0-4681-af5f-e0f84e509c94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452242161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3452242161
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3519845384
Short name T217
Test name
Test status
Simulation time 496975145519 ps
CPU time 548.35 seconds
Started Aug 13 06:02:21 PM PDT 24
Finished Aug 13 06:11:30 PM PDT 24
Peak memory 202184 kb
Host smart-38389908-82ac-44b3-8c6e-2bb8a012ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519845384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3519845384
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3575321390
Short name T570
Test name
Test status
Simulation time 495538084720 ps
CPU time 266.79 seconds
Started Aug 13 06:02:27 PM PDT 24
Finished Aug 13 06:06:54 PM PDT 24
Peak memory 202076 kb
Host smart-01a9af8b-81ee-487e-b8eb-23997b96779a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575321390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3575321390
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.39284040
Short name T408
Test name
Test status
Simulation time 170255393141 ps
CPU time 363.46 seconds
Started Aug 13 06:02:23 PM PDT 24
Finished Aug 13 06:08:26 PM PDT 24
Peak memory 202032 kb
Host smart-a185d027-d3a6-4cdc-8660-b4d70345a516
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39284040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_w
akeup.39284040
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3276319715
Short name T401
Test name
Test status
Simulation time 413347015661 ps
CPU time 440.15 seconds
Started Aug 13 06:02:28 PM PDT 24
Finished Aug 13 06:09:49 PM PDT 24
Peak memory 202020 kb
Host smart-57f19e69-ae52-4ec8-80a2-37f31ae087a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276319715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3276319715
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2310583398
Short name T569
Test name
Test status
Simulation time 99135343657 ps
CPU time 535.27 seconds
Started Aug 13 06:02:21 PM PDT 24
Finished Aug 13 06:11:17 PM PDT 24
Peak memory 202432 kb
Host smart-39b6ad73-e2ca-4c29-971f-514a63ddd565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310583398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2310583398
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.246434353
Short name T666
Test name
Test status
Simulation time 40184777192 ps
CPU time 23.9 seconds
Started Aug 13 06:02:22 PM PDT 24
Finished Aug 13 06:02:46 PM PDT 24
Peak memory 201968 kb
Host smart-431832de-5531-478f-803c-35b9b1aabab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246434353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.246434353
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2763687181
Short name T468
Test name
Test status
Simulation time 3943763775 ps
CPU time 3.08 seconds
Started Aug 13 06:02:23 PM PDT 24
Finished Aug 13 06:02:26 PM PDT 24
Peak memory 201976 kb
Host smart-7026aafc-1c1a-4ef0-aba3-4d79a714fd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763687181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2763687181
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.453571835
Short name T47
Test name
Test status
Simulation time 5706294739 ps
CPU time 14.17 seconds
Started Aug 13 06:02:27 PM PDT 24
Finished Aug 13 06:02:41 PM PDT 24
Peak memory 201840 kb
Host smart-33b0c8d7-6283-4670-bc02-14819843908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453571835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.453571835
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2965017463
Short name T287
Test name
Test status
Simulation time 374069033379 ps
CPU time 438.57 seconds
Started Aug 13 06:02:39 PM PDT 24
Finished Aug 13 06:09:58 PM PDT 24
Peak memory 202036 kb
Host smart-30dc851b-dae4-4fef-86f5-3e3f9f156a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965017463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2965017463
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3572131770
Short name T706
Test name
Test status
Simulation time 3748291689 ps
CPU time 4.4 seconds
Started Aug 13 06:02:31 PM PDT 24
Finished Aug 13 06:02:35 PM PDT 24
Peak memory 210504 kb
Host smart-bfdafdff-9082-4d77-904e-5628912b3743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572131770 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3572131770
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3752245089
Short name T496
Test name
Test status
Simulation time 440383209 ps
CPU time 1.6 seconds
Started Aug 13 06:02:47 PM PDT 24
Finished Aug 13 06:02:48 PM PDT 24
Peak memory 201952 kb
Host smart-300e254c-88e3-467e-902f-f4885df68197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752245089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3752245089
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.4108811233
Short name T344
Test name
Test status
Simulation time 183532514159 ps
CPU time 109.94 seconds
Started Aug 13 06:02:41 PM PDT 24
Finished Aug 13 06:04:31 PM PDT 24
Peak memory 202160 kb
Host smart-c6f22028-3859-4033-b1cf-940f1db2cfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108811233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.4108811233
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3420846169
Short name T549
Test name
Test status
Simulation time 162628689738 ps
CPU time 110.03 seconds
Started Aug 13 06:02:36 PM PDT 24
Finished Aug 13 06:04:27 PM PDT 24
Peak memory 202176 kb
Host smart-624dc9b5-0250-456a-82ed-0597ad39a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420846169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3420846169
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1968782888
Short name T756
Test name
Test status
Simulation time 325072485737 ps
CPU time 169.35 seconds
Started Aug 13 06:02:37 PM PDT 24
Finished Aug 13 06:05:26 PM PDT 24
Peak memory 202160 kb
Host smart-487358b4-db3b-44e2-ab34-7269726ca1d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968782888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1968782888
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.548422433
Short name T330
Test name
Test status
Simulation time 484282363439 ps
CPU time 277.74 seconds
Started Aug 13 06:02:28 PM PDT 24
Finished Aug 13 06:07:06 PM PDT 24
Peak memory 202032 kb
Host smart-a40ad20b-214d-4084-b5ee-13730bc4dbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548422433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.548422433
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2994232827
Short name T429
Test name
Test status
Simulation time 505528992795 ps
CPU time 245.12 seconds
Started Aug 13 06:02:39 PM PDT 24
Finished Aug 13 06:06:45 PM PDT 24
Peak memory 202152 kb
Host smart-f3d18212-aee1-4c68-9dde-b5bfaca7d98d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994232827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2994232827
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2820597335
Short name T705
Test name
Test status
Simulation time 341163579356 ps
CPU time 172.16 seconds
Started Aug 13 06:02:33 PM PDT 24
Finished Aug 13 06:05:25 PM PDT 24
Peak memory 202068 kb
Host smart-abfe4954-9dea-41e4-a353-520cd6c8da3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820597335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2820597335
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2124999523
Short name T544
Test name
Test status
Simulation time 202628173711 ps
CPU time 64.74 seconds
Started Aug 13 06:02:32 PM PDT 24
Finished Aug 13 06:03:37 PM PDT 24
Peak memory 202104 kb
Host smart-306d57a9-5527-46ec-9cc6-18393b2c0ffa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124999523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2124999523
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1405958957
Short name T427
Test name
Test status
Simulation time 44553723207 ps
CPU time 18.42 seconds
Started Aug 13 06:02:47 PM PDT 24
Finished Aug 13 06:03:05 PM PDT 24
Peak memory 201880 kb
Host smart-a59b3059-8266-4b95-9782-4073d34aa25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405958957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1405958957
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3836233652
Short name T503
Test name
Test status
Simulation time 5144262846 ps
CPU time 1.53 seconds
Started Aug 13 06:02:40 PM PDT 24
Finished Aug 13 06:02:41 PM PDT 24
Peak memory 201968 kb
Host smart-fa9c2fce-e252-4aa2-8a42-09d0446c4407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836233652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3836233652
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2838033683
Short name T668
Test name
Test status
Simulation time 5918508572 ps
CPU time 4.38 seconds
Started Aug 13 06:02:32 PM PDT 24
Finished Aug 13 06:02:36 PM PDT 24
Peak memory 201936 kb
Host smart-c31f7813-e28a-412e-bb16-540286a4738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838033683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2838033683
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.921883332
Short name T767
Test name
Test status
Simulation time 615588496972 ps
CPU time 586.87 seconds
Started Aug 13 06:02:38 PM PDT 24
Finished Aug 13 06:12:25 PM PDT 24
Peak memory 202136 kb
Host smart-9ccebced-21e7-4bb8-bed2-0089d742e20b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921883332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
921883332
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.388398457
Short name T696
Test name
Test status
Simulation time 3597277043 ps
CPU time 10.92 seconds
Started Aug 13 06:02:40 PM PDT 24
Finished Aug 13 06:02:51 PM PDT 24
Peak memory 210748 kb
Host smart-72179792-1de3-4150-8387-2dc5f1b674d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388398457 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.388398457
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3715809148
Short name T413
Test name
Test status
Simulation time 327990297 ps
CPU time 0.84 seconds
Started Aug 13 06:02:47 PM PDT 24
Finished Aug 13 06:02:48 PM PDT 24
Peak memory 202100 kb
Host smart-583b0e52-26d2-4f5c-aab7-f5a20971196e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715809148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3715809148
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2662645495
Short name T261
Test name
Test status
Simulation time 367827639411 ps
CPU time 361.23 seconds
Started Aug 13 06:02:50 PM PDT 24
Finished Aug 13 06:08:52 PM PDT 24
Peak memory 202152 kb
Host smart-64721884-ad52-47d8-86e6-9712810241f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662645495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2662645495
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.965360548
Short name T530
Test name
Test status
Simulation time 404966236286 ps
CPU time 436.09 seconds
Started Aug 13 06:02:52 PM PDT 24
Finished Aug 13 06:10:08 PM PDT 24
Peak memory 202112 kb
Host smart-159f2a3c-b8fd-4563-9e8b-47583c4815f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965360548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.965360548
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3005178851
Short name T224
Test name
Test status
Simulation time 322947631438 ps
CPU time 424.85 seconds
Started Aug 13 06:02:41 PM PDT 24
Finished Aug 13 06:09:46 PM PDT 24
Peak memory 202140 kb
Host smart-599c0662-0682-495f-8698-9a4ec00b3ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005178851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3005178851
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1736490638
Short name T175
Test name
Test status
Simulation time 490889057237 ps
CPU time 268.91 seconds
Started Aug 13 06:02:41 PM PDT 24
Finished Aug 13 06:07:10 PM PDT 24
Peak memory 202152 kb
Host smart-817c4328-76e0-4500-af72-9c0bc5501d39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736490638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1736490638
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.809051514
Short name T352
Test name
Test status
Simulation time 499271204776 ps
CPU time 1023.28 seconds
Started Aug 13 06:02:42 PM PDT 24
Finished Aug 13 06:19:46 PM PDT 24
Peak memory 202140 kb
Host smart-360b10b3-065f-4d09-951e-5c0573e95890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809051514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.809051514
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.361093615
Short name T593
Test name
Test status
Simulation time 165931714612 ps
CPU time 397.59 seconds
Started Aug 13 06:02:41 PM PDT 24
Finished Aug 13 06:09:18 PM PDT 24
Peak memory 202092 kb
Host smart-c5487cd8-6836-4414-9e21-c69d95f290cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=361093615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.361093615
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.474063693
Short name T426
Test name
Test status
Simulation time 399105267073 ps
CPU time 857.66 seconds
Started Aug 13 06:02:45 PM PDT 24
Finished Aug 13 06:17:03 PM PDT 24
Peak memory 202116 kb
Host smart-5b154a9b-b7fc-4b97-804c-a6fdc6faad15
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474063693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.474063693
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.863917635
Short name T245
Test name
Test status
Simulation time 126398465919 ps
CPU time 496.22 seconds
Started Aug 13 06:02:51 PM PDT 24
Finished Aug 13 06:11:08 PM PDT 24
Peak memory 202512 kb
Host smart-1e8b3f53-30a4-4bbf-a2dc-1469ef16e9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863917635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.863917635
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3096602052
Short name T173
Test name
Test status
Simulation time 38090607525 ps
CPU time 22.17 seconds
Started Aug 13 06:02:53 PM PDT 24
Finished Aug 13 06:03:16 PM PDT 24
Peak memory 201964 kb
Host smart-a2561788-1c40-40be-a0a9-34e5d7e0511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096602052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3096602052
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1835252365
Short name T9
Test name
Test status
Simulation time 3697063401 ps
CPU time 2.92 seconds
Started Aug 13 06:02:50 PM PDT 24
Finished Aug 13 06:02:53 PM PDT 24
Peak memory 201924 kb
Host smart-f5b33d97-544d-4e7c-ab09-1d80f495a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835252365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1835252365
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3654381778
Short name T655
Test name
Test status
Simulation time 6033084843 ps
CPU time 16.47 seconds
Started Aug 13 06:02:41 PM PDT 24
Finished Aug 13 06:02:58 PM PDT 24
Peak memory 201956 kb
Host smart-90bad635-ed21-4600-9e77-b054a453118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654381778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3654381778
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2810261547
Short name T313
Test name
Test status
Simulation time 171290020917 ps
CPU time 160.57 seconds
Started Aug 13 06:02:50 PM PDT 24
Finished Aug 13 06:05:31 PM PDT 24
Peak memory 202132 kb
Host smart-49e35344-4d98-4c07-af9c-771e8969f8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810261547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2810261547
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3489344422
Short name T710
Test name
Test status
Simulation time 3128043571 ps
CPU time 6.65 seconds
Started Aug 13 06:02:47 PM PDT 24
Finished Aug 13 06:02:54 PM PDT 24
Peak memory 202124 kb
Host smart-ec104ae2-c7db-42c5-88c2-91266538423f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489344422 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3489344422
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1638454142
Short name T306
Test name
Test status
Simulation time 160371348774 ps
CPU time 98.08 seconds
Started Aug 13 06:03:10 PM PDT 24
Finished Aug 13 06:04:49 PM PDT 24
Peak memory 202160 kb
Host smart-3c61a312-609b-4e69-94b0-f621d3f4971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638454142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1638454142
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1402960263
Short name T201
Test name
Test status
Simulation time 498666282119 ps
CPU time 282.6 seconds
Started Aug 13 06:03:06 PM PDT 24
Finished Aug 13 06:07:49 PM PDT 24
Peak memory 202132 kb
Host smart-d82e72e5-b3a7-4ba8-ad28-d24800ddade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402960263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1402960263
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2507177564
Short name T714
Test name
Test status
Simulation time 488848433164 ps
CPU time 278.64 seconds
Started Aug 13 06:03:01 PM PDT 24
Finished Aug 13 06:07:40 PM PDT 24
Peak memory 202172 kb
Host smart-cae4940e-92bf-4f94-83f4-6e78fefa3a1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507177564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2507177564
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.446127328
Short name T3
Test name
Test status
Simulation time 326389071305 ps
CPU time 202.38 seconds
Started Aug 13 06:03:06 PM PDT 24
Finished Aug 13 06:06:28 PM PDT 24
Peak memory 202120 kb
Host smart-f6b8e9e0-14ee-4a59-9cde-972bb0696fe6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=446127328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.446127328
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1635759024
Short name T143
Test name
Test status
Simulation time 170248539024 ps
CPU time 399.75 seconds
Started Aug 13 06:03:03 PM PDT 24
Finished Aug 13 06:09:43 PM PDT 24
Peak memory 202108 kb
Host smart-35e45525-bcb4-45b8-8739-1b869dffc32d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635759024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1635759024
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1751826937
Short name T732
Test name
Test status
Simulation time 615864970860 ps
CPU time 1371.83 seconds
Started Aug 13 06:03:02 PM PDT 24
Finished Aug 13 06:25:54 PM PDT 24
Peak memory 202092 kb
Host smart-a2a20b51-f73d-4eac-809e-2036ada4273e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751826937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1751826937
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1590587031
Short name T697
Test name
Test status
Simulation time 118770457604 ps
CPU time 646.13 seconds
Started Aug 13 06:03:00 PM PDT 24
Finished Aug 13 06:13:47 PM PDT 24
Peak memory 202360 kb
Host smart-76febd6e-0518-4a1d-80fe-37cd534bfc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590587031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1590587031
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2616939512
Short name T719
Test name
Test status
Simulation time 37390933782 ps
CPU time 45.47 seconds
Started Aug 13 06:03:01 PM PDT 24
Finished Aug 13 06:03:46 PM PDT 24
Peak memory 201976 kb
Host smart-9a82c5ee-f395-44f4-8026-64732be801db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616939512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2616939512
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1260977451
Short name T392
Test name
Test status
Simulation time 3150892800 ps
CPU time 8.89 seconds
Started Aug 13 06:02:59 PM PDT 24
Finished Aug 13 06:03:08 PM PDT 24
Peak memory 201876 kb
Host smart-284c6a0d-668b-4eb2-8298-bc7a112e258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260977451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1260977451
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.687929232
Short name T649
Test name
Test status
Simulation time 5593166799 ps
CPU time 4.76 seconds
Started Aug 13 06:02:56 PM PDT 24
Finished Aug 13 06:03:01 PM PDT 24
Peak memory 201852 kb
Host smart-8c8a84ea-4b3f-47dd-8ba7-8492539efd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687929232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.687929232
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2953929064
Short name T757
Test name
Test status
Simulation time 163173026382 ps
CPU time 93.37 seconds
Started Aug 13 06:03:01 PM PDT 24
Finished Aug 13 06:04:34 PM PDT 24
Peak memory 202204 kb
Host smart-3e692c44-4ddb-4721-8ece-c1641efc262c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953929064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2953929064
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2723027108
Short name T493
Test name
Test status
Simulation time 1498481771 ps
CPU time 5.31 seconds
Started Aug 13 06:03:06 PM PDT 24
Finished Aug 13 06:03:11 PM PDT 24
Peak memory 202056 kb
Host smart-530374a5-38d4-4574-8384-a3022b774004
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723027108 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2723027108
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3333765264
Short name T789
Test name
Test status
Simulation time 455208257 ps
CPU time 1.63 seconds
Started Aug 13 06:03:11 PM PDT 24
Finished Aug 13 06:03:12 PM PDT 24
Peak memory 201852 kb
Host smart-01bf7c36-738e-42a3-aaa8-68b8b83fef30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333765264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3333765264
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3958793962
Short name T191
Test name
Test status
Simulation time 171020397143 ps
CPU time 383.91 seconds
Started Aug 13 06:03:11 PM PDT 24
Finished Aug 13 06:09:35 PM PDT 24
Peak memory 202140 kb
Host smart-1bf07c61-3ef1-424b-89f7-331843a1927b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958793962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3958793962
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3837616672
Short name T162
Test name
Test status
Simulation time 162071495394 ps
CPU time 84.65 seconds
Started Aug 13 06:03:02 PM PDT 24
Finished Aug 13 06:04:26 PM PDT 24
Peak memory 202104 kb
Host smart-340ee183-20b7-4f25-afa9-4441cb1ca9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837616672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3837616672
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2153091704
Short name T475
Test name
Test status
Simulation time 324358968439 ps
CPU time 183.74 seconds
Started Aug 13 06:03:18 PM PDT 24
Finished Aug 13 06:06:21 PM PDT 24
Peak memory 202076 kb
Host smart-d303e16a-26ca-4ceb-b83d-6824d5d24269
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153091704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2153091704
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1518490125
Short name T763
Test name
Test status
Simulation time 496276173804 ps
CPU time 606.33 seconds
Started Aug 13 06:03:07 PM PDT 24
Finished Aug 13 06:13:13 PM PDT 24
Peak memory 202032 kb
Host smart-cdec9ba9-8913-4957-8744-565aee258b96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518490125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1518490125
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3237931000
Short name T271
Test name
Test status
Simulation time 178699002442 ps
CPU time 211.4 seconds
Started Aug 13 06:03:18 PM PDT 24
Finished Aug 13 06:06:49 PM PDT 24
Peak memory 202148 kb
Host smart-b3943f2c-6b6f-491a-90bf-225ae5b620a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237931000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3237931000
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3418747617
Short name T482
Test name
Test status
Simulation time 411479117902 ps
CPU time 478.24 seconds
Started Aug 13 06:03:17 PM PDT 24
Finished Aug 13 06:11:16 PM PDT 24
Peak memory 202192 kb
Host smart-86004a4b-b2fd-403f-bb49-868ca54da34d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418747617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3418747617
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1507907532
Short name T481
Test name
Test status
Simulation time 45384398157 ps
CPU time 48.98 seconds
Started Aug 13 06:03:16 PM PDT 24
Finished Aug 13 06:04:05 PM PDT 24
Peak memory 201980 kb
Host smart-ced2500a-ef2d-4153-ac7a-f660a38754e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507907532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1507907532
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2250928454
Short name T520
Test name
Test status
Simulation time 4021352236 ps
CPU time 4.49 seconds
Started Aug 13 06:03:06 PM PDT 24
Finished Aug 13 06:03:10 PM PDT 24
Peak memory 201964 kb
Host smart-48a2b917-0669-44b2-9030-7120e789c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250928454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2250928454
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1760995437
Short name T630
Test name
Test status
Simulation time 5818871181 ps
CPU time 6.83 seconds
Started Aug 13 06:03:09 PM PDT 24
Finished Aug 13 06:03:16 PM PDT 24
Peak memory 201976 kb
Host smart-97c40704-3ce8-4c31-b4fb-77746efbad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760995437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1760995437
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3047303643
Short name T52
Test name
Test status
Simulation time 194214919281 ps
CPU time 458.34 seconds
Started Aug 13 06:03:11 PM PDT 24
Finished Aug 13 06:10:49 PM PDT 24
Peak memory 202148 kb
Host smart-fefd6ae1-d085-4bf2-bb52-a06a0ffbdaa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047303643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3047303643
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3855814363
Short name T795
Test name
Test status
Simulation time 4340857652 ps
CPU time 13.76 seconds
Started Aug 13 06:03:09 PM PDT 24
Finished Aug 13 06:03:23 PM PDT 24
Peak memory 218928 kb
Host smart-8a196f60-77c9-43e5-8c52-59dc0b8dd07d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855814363 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3855814363
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2224055652
Short name T414
Test name
Test status
Simulation time 300792314 ps
CPU time 0.86 seconds
Started Aug 13 06:00:54 PM PDT 24
Finished Aug 13 06:00:55 PM PDT 24
Peak memory 201996 kb
Host smart-d0378985-a86a-4e9b-a882-1c9364e75a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224055652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2224055652
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.359095583
Short name T652
Test name
Test status
Simulation time 353256153212 ps
CPU time 731.32 seconds
Started Aug 13 06:00:54 PM PDT 24
Finished Aug 13 06:13:05 PM PDT 24
Peak memory 202156 kb
Host smart-d46c6df9-0708-495f-9246-4da984b2a803
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359095583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.359095583
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.559365860
Short name T650
Test name
Test status
Simulation time 203707520720 ps
CPU time 167.63 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:03:40 PM PDT 24
Peak memory 202144 kb
Host smart-1819c764-6c91-4cbc-84f4-239527356b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559365860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.559365860
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.151884489
Short name T15
Test name
Test status
Simulation time 323320975811 ps
CPU time 221.04 seconds
Started Aug 13 06:00:53 PM PDT 24
Finished Aug 13 06:04:34 PM PDT 24
Peak memory 202028 kb
Host smart-5f4d80f9-9f13-4ce0-958e-75ec400e8227
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=151884489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.151884489
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3316738434
Short name T637
Test name
Test status
Simulation time 165318394689 ps
CPU time 110.82 seconds
Started Aug 13 06:00:55 PM PDT 24
Finished Aug 13 06:02:46 PM PDT 24
Peak memory 202136 kb
Host smart-3dd6ff8b-4e40-4ed4-96e8-3897c496c316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316738434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3316738434
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.539632164
Short name T402
Test name
Test status
Simulation time 327981807158 ps
CPU time 233.39 seconds
Started Aug 13 06:00:53 PM PDT 24
Finished Aug 13 06:04:47 PM PDT 24
Peak memory 202068 kb
Host smart-27c28e99-7193-430f-abc2-c7283038df3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=539632164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.539632164
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.159064245
Short name T590
Test name
Test status
Simulation time 163542770150 ps
CPU time 365.85 seconds
Started Aug 13 06:00:54 PM PDT 24
Finished Aug 13 06:07:00 PM PDT 24
Peak memory 202128 kb
Host smart-3f098ef7-fd27-48d4-a58f-882a9acba49f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159064245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.159064245
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1182356425
Short name T241
Test name
Test status
Simulation time 136944766315 ps
CPU time 455.72 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:08:28 PM PDT 24
Peak memory 202432 kb
Host smart-2a58b158-98e0-435e-8024-9266bd55aea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182356425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1182356425
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3351043014
Short name T780
Test name
Test status
Simulation time 34864857812 ps
CPU time 6.52 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:00:58 PM PDT 24
Peak memory 201948 kb
Host smart-6e0927f9-de86-4329-a35f-23b6057577c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351043014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3351043014
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1532922772
Short name T389
Test name
Test status
Simulation time 3403377525 ps
CPU time 8.04 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:01:01 PM PDT 24
Peak memory 201924 kb
Host smart-89eaaa15-d4eb-4138-935b-020b6a18adf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532922772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1532922772
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3465671295
Short name T91
Test name
Test status
Simulation time 7712628308 ps
CPU time 9.36 seconds
Started Aug 13 06:00:54 PM PDT 24
Finished Aug 13 06:01:03 PM PDT 24
Peak memory 218472 kb
Host smart-5a20c863-2017-4771-96ed-68a2eeccc11e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465671295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3465671295
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2041027180
Short name T449
Test name
Test status
Simulation time 5650394506 ps
CPU time 14.87 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:01:08 PM PDT 24
Peak memory 201992 kb
Host smart-13059733-4c42-425e-aec6-c94dd055bcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041027180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2041027180
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1826504282
Short name T657
Test name
Test status
Simulation time 181264445797 ps
CPU time 201.7 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:04:14 PM PDT 24
Peak memory 202152 kb
Host smart-ff9dbb50-5337-4efb-a642-7fc70cf28189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826504282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1826504282
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1704419930
Short name T626
Test name
Test status
Simulation time 29348391600 ps
CPU time 7.83 seconds
Started Aug 13 06:00:54 PM PDT 24
Finished Aug 13 06:01:02 PM PDT 24
Peak memory 210532 kb
Host smart-7bc95490-b554-4879-9f86-84b15540c268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704419930 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1704419930
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.342113539
Short name T551
Test name
Test status
Simulation time 327504152 ps
CPU time 1.38 seconds
Started Aug 13 06:03:21 PM PDT 24
Finished Aug 13 06:03:23 PM PDT 24
Peak memory 201992 kb
Host smart-161081ba-43ed-447b-88ea-f3fb0d2df0cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342113539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.342113539
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1609693384
Short name T739
Test name
Test status
Simulation time 336366229332 ps
CPU time 799.39 seconds
Started Aug 13 06:03:21 PM PDT 24
Finished Aug 13 06:16:41 PM PDT 24
Peak memory 202120 kb
Host smart-10a836fa-bb66-4f49-a866-3d9024bed3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609693384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1609693384
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1806507946
Short name T166
Test name
Test status
Simulation time 317318502109 ps
CPU time 376.83 seconds
Started Aug 13 06:03:11 PM PDT 24
Finished Aug 13 06:09:28 PM PDT 24
Peak memory 202176 kb
Host smart-a06942a9-dc2a-40ed-9175-d8858087585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806507946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1806507946
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1303185310
Short name T729
Test name
Test status
Simulation time 170950956346 ps
CPU time 369.59 seconds
Started Aug 13 06:03:17 PM PDT 24
Finished Aug 13 06:09:26 PM PDT 24
Peak memory 202144 kb
Host smart-3c56bdab-b3e4-4d16-b8fa-1b6e25923b8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303185310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1303185310
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2766664285
Short name T114
Test name
Test status
Simulation time 164254560037 ps
CPU time 388.86 seconds
Started Aug 13 06:03:10 PM PDT 24
Finished Aug 13 06:09:39 PM PDT 24
Peak memory 202140 kb
Host smart-024bafdf-5003-4b61-b6a1-2bbf55b16d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766664285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2766664285
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1367287886
Short name T464
Test name
Test status
Simulation time 488932507640 ps
CPU time 1158.13 seconds
Started Aug 13 06:03:17 PM PDT 24
Finished Aug 13 06:22:35 PM PDT 24
Peak memory 202120 kb
Host smart-b83a43df-0bab-4595-a2da-aa9b492a4b97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367287886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1367287886
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2359384221
Short name T324
Test name
Test status
Simulation time 682240816117 ps
CPU time 305.38 seconds
Started Aug 13 06:03:11 PM PDT 24
Finished Aug 13 06:08:17 PM PDT 24
Peak memory 202140 kb
Host smart-1c97315a-76a9-48c9-9bec-2b7ed8fd7093
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359384221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2359384221
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1976454866
Short name T725
Test name
Test status
Simulation time 600040065344 ps
CPU time 343.33 seconds
Started Aug 13 06:03:11 PM PDT 24
Finished Aug 13 06:08:55 PM PDT 24
Peak memory 202104 kb
Host smart-97c87a79-eb79-4fb0-88ce-a673c051b081
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976454866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1976454866
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.994644039
Short name T250
Test name
Test status
Simulation time 101630191672 ps
CPU time 390.87 seconds
Started Aug 13 06:03:26 PM PDT 24
Finished Aug 13 06:09:57 PM PDT 24
Peak memory 202364 kb
Host smart-777f7fdf-3d8b-475d-9d7d-062db3b6e7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994644039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.994644039
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.703915349
Short name T8
Test name
Test status
Simulation time 22911391335 ps
CPU time 57.76 seconds
Started Aug 13 06:03:18 PM PDT 24
Finished Aug 13 06:04:16 PM PDT 24
Peak memory 201920 kb
Host smart-71a28c62-7533-4856-818e-0e34f9a48c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703915349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.703915349
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.695628877
Short name T439
Test name
Test status
Simulation time 4799421619 ps
CPU time 13.24 seconds
Started Aug 13 06:03:21 PM PDT 24
Finished Aug 13 06:03:35 PM PDT 24
Peak memory 201960 kb
Host smart-70971ea1-6022-4fd5-89d7-532ab8918c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695628877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.695628877
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2288774433
Short name T105
Test name
Test status
Simulation time 5733646287 ps
CPU time 14.29 seconds
Started Aug 13 06:03:16 PM PDT 24
Finished Aug 13 06:03:30 PM PDT 24
Peak memory 201964 kb
Host smart-a53f267b-0474-45c9-a0d0-ec99a8f6c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288774433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2288774433
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3012320405
Short name T754
Test name
Test status
Simulation time 531768755636 ps
CPU time 86.01 seconds
Started Aug 13 06:03:24 PM PDT 24
Finished Aug 13 06:04:50 PM PDT 24
Peak memory 202044 kb
Host smart-b6679497-f1f1-47ac-b9f8-0351b5fc5034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012320405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3012320405
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.558531499
Short name T495
Test name
Test status
Simulation time 2570993016 ps
CPU time 6.75 seconds
Started Aug 13 06:03:21 PM PDT 24
Finished Aug 13 06:03:28 PM PDT 24
Peak memory 202080 kb
Host smart-ca962868-a168-46d1-b22d-988dc3988538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558531499 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.558531499
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1681003215
Short name T103
Test name
Test status
Simulation time 499934769 ps
CPU time 1.17 seconds
Started Aug 13 06:03:28 PM PDT 24
Finished Aug 13 06:03:30 PM PDT 24
Peak memory 202008 kb
Host smart-70c74e29-5512-414e-bede-637b6a5ff58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681003215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1681003215
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2366991361
Short name T744
Test name
Test status
Simulation time 165346110952 ps
CPU time 8.56 seconds
Started Aug 13 06:03:33 PM PDT 24
Finished Aug 13 06:03:42 PM PDT 24
Peak memory 202136 kb
Host smart-0757124b-8691-4d96-b6f4-ae0713297497
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366991361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2366991361
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2944550070
Short name T718
Test name
Test status
Simulation time 487303346787 ps
CPU time 315.17 seconds
Started Aug 13 06:03:35 PM PDT 24
Finished Aug 13 06:08:51 PM PDT 24
Peak memory 202088 kb
Host smart-92e47d29-8b1a-4dad-83f2-1d4706e18fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944550070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2944550070
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2057941589
Short name T398
Test name
Test status
Simulation time 163433537104 ps
CPU time 358.1 seconds
Started Aug 13 06:03:30 PM PDT 24
Finished Aug 13 06:09:28 PM PDT 24
Peak memory 202160 kb
Host smart-107a858c-b19c-47a5-802a-ca61984d0120
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057941589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2057941589
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.111651907
Short name T176
Test name
Test status
Simulation time 496874310850 ps
CPU time 308.94 seconds
Started Aug 13 06:03:22 PM PDT 24
Finished Aug 13 06:08:31 PM PDT 24
Peak memory 202152 kb
Host smart-eeab9d94-e0fe-46cf-8425-7595d5c2c300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111651907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.111651907
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.474086597
Short name T575
Test name
Test status
Simulation time 163627552232 ps
CPU time 392.25 seconds
Started Aug 13 06:03:31 PM PDT 24
Finished Aug 13 06:10:04 PM PDT 24
Peak memory 202116 kb
Host smart-828280b9-8e9c-4e42-b265-20b012c06d21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=474086597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.474086597
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3328543491
Short name T311
Test name
Test status
Simulation time 409401209214 ps
CPU time 867.72 seconds
Started Aug 13 06:03:29 PM PDT 24
Finished Aug 13 06:17:56 PM PDT 24
Peak memory 202076 kb
Host smart-5553115a-d9d6-4eea-bc3a-febba6d4bdb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328543491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3328543491
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1381538281
Short name T788
Test name
Test status
Simulation time 193678018609 ps
CPU time 435.5 seconds
Started Aug 13 06:03:31 PM PDT 24
Finished Aug 13 06:10:47 PM PDT 24
Peak memory 202196 kb
Host smart-074b68e3-3f5f-4006-a012-da01ce84ffa6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381538281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1381538281
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3215974726
Short name T779
Test name
Test status
Simulation time 113964954717 ps
CPU time 592.69 seconds
Started Aug 13 06:03:30 PM PDT 24
Finished Aug 13 06:13:23 PM PDT 24
Peak memory 202392 kb
Host smart-97470647-cbb7-42cc-8405-a9c8b8e9d1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215974726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3215974726
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.58476381
Short name T581
Test name
Test status
Simulation time 21559310058 ps
CPU time 23.88 seconds
Started Aug 13 06:03:31 PM PDT 24
Finished Aug 13 06:03:55 PM PDT 24
Peak memory 201876 kb
Host smart-66e60eac-779a-447a-a82a-9f6eaff7c03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58476381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.58476381
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2193868189
Short name T709
Test name
Test status
Simulation time 3212061958 ps
CPU time 7.25 seconds
Started Aug 13 06:03:32 PM PDT 24
Finished Aug 13 06:03:39 PM PDT 24
Peak memory 201848 kb
Host smart-aabf0412-cfd4-43a1-b11c-7f85ad205d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193868189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2193868189
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.577016415
Short name T7
Test name
Test status
Simulation time 5929118242 ps
CPU time 4.48 seconds
Started Aug 13 06:03:15 PM PDT 24
Finished Aug 13 06:03:19 PM PDT 24
Peak memory 201960 kb
Host smart-ad49a907-08da-4441-aaa7-29d0c0ff576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577016415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.577016415
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3507652528
Short name T432
Test name
Test status
Simulation time 175653335198 ps
CPU time 109.19 seconds
Started Aug 13 06:03:28 PM PDT 24
Finished Aug 13 06:05:18 PM PDT 24
Peak memory 202148 kb
Host smart-b705f2f6-8f54-472c-bd00-bacebaa66880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507652528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3507652528
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2121213796
Short name T22
Test name
Test status
Simulation time 2671130167 ps
CPU time 6.58 seconds
Started Aug 13 06:03:29 PM PDT 24
Finished Aug 13 06:03:35 PM PDT 24
Peak memory 210540 kb
Host smart-2834667e-af30-4e04-8164-d123a4b59256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121213796 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2121213796
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.542544104
Short name T553
Test name
Test status
Simulation time 299587284 ps
CPU time 0.79 seconds
Started Aug 13 06:03:40 PM PDT 24
Finished Aug 13 06:03:41 PM PDT 24
Peak memory 201984 kb
Host smart-ff9b4b32-5b23-446f-a0a9-b0ce999bd0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542544104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.542544104
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4211611219
Short name T350
Test name
Test status
Simulation time 159836809477 ps
CPU time 156.69 seconds
Started Aug 13 06:03:39 PM PDT 24
Finished Aug 13 06:06:16 PM PDT 24
Peak memory 202156 kb
Host smart-fc0503b3-62d7-4d09-a13d-50c477be5dc2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211611219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4211611219
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1465157917
Short name T527
Test name
Test status
Simulation time 326130444439 ps
CPU time 755.72 seconds
Started Aug 13 06:03:43 PM PDT 24
Finished Aug 13 06:16:19 PM PDT 24
Peak memory 202156 kb
Host smart-63204caa-93e2-47fc-b76a-f54ffe7b1c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465157917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1465157917
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2603847136
Short name T638
Test name
Test status
Simulation time 166576329958 ps
CPU time 355.77 seconds
Started Aug 13 06:03:35 PM PDT 24
Finished Aug 13 06:09:31 PM PDT 24
Peak memory 202140 kb
Host smart-10e14b61-7f15-4d45-a240-d6ac964d6a51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603847136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2603847136
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.4136978571
Short name T227
Test name
Test status
Simulation time 487792466383 ps
CPU time 301.6 seconds
Started Aug 13 06:03:39 PM PDT 24
Finished Aug 13 06:08:41 PM PDT 24
Peak memory 202040 kb
Host smart-61ef7b86-bb6b-45d9-9f19-e75db8308c05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136978571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.4136978571
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3498166677
Short name T149
Test name
Test status
Simulation time 170834925236 ps
CPU time 345.48 seconds
Started Aug 13 06:03:46 PM PDT 24
Finished Aug 13 06:09:31 PM PDT 24
Peak memory 202044 kb
Host smart-ad720482-6d3d-4917-8d71-0007d2d4c087
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498166677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3498166677
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.146597909
Short name T663
Test name
Test status
Simulation time 607420507686 ps
CPU time 710.7 seconds
Started Aug 13 06:03:39 PM PDT 24
Finished Aug 13 06:15:30 PM PDT 24
Peak memory 202144 kb
Host smart-05bee695-988c-4479-8016-773d7a82379f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146597909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.146597909
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.53399222
Short name T233
Test name
Test status
Simulation time 96870705878 ps
CPU time 401.23 seconds
Started Aug 13 06:03:37 PM PDT 24
Finished Aug 13 06:10:19 PM PDT 24
Peak memory 202400 kb
Host smart-113d5fa0-22c8-43a2-aba1-95f918d8f44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53399222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.53399222
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.830802485
Short name T733
Test name
Test status
Simulation time 25995003461 ps
CPU time 14.74 seconds
Started Aug 13 06:03:43 PM PDT 24
Finished Aug 13 06:03:58 PM PDT 24
Peak memory 201924 kb
Host smart-430ef3b4-f1c2-4b88-8785-bfc5a4469519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830802485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.830802485
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1157866638
Short name T765
Test name
Test status
Simulation time 4946837697 ps
CPU time 3.83 seconds
Started Aug 13 06:03:37 PM PDT 24
Finished Aug 13 06:03:41 PM PDT 24
Peak memory 201960 kb
Host smart-e37a3869-c9ca-4f9c-bfdc-bfddc6e17072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157866638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1157866638
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1873825903
Short name T379
Test name
Test status
Simulation time 5658466488 ps
CPU time 3.81 seconds
Started Aug 13 06:03:29 PM PDT 24
Finished Aug 13 06:03:33 PM PDT 24
Peak memory 201964 kb
Host smart-da8a2643-8da7-4a55-916e-febd6bd6cb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873825903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1873825903
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.61898753
Short name T761
Test name
Test status
Simulation time 377750013571 ps
CPU time 203.38 seconds
Started Aug 13 06:03:38 PM PDT 24
Finished Aug 13 06:07:02 PM PDT 24
Peak memory 202124 kb
Host smart-980f923b-a4d5-4183-a2fa-6d3e2bb66f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61898753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.61898753
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1074511235
Short name T621
Test name
Test status
Simulation time 323917893 ps
CPU time 0.88 seconds
Started Aug 13 06:03:55 PM PDT 24
Finished Aug 13 06:03:56 PM PDT 24
Peak memory 201852 kb
Host smart-c09020e2-4ee8-4400-96dc-e1c0ef65292d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074511235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1074511235
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1050975780
Short name T338
Test name
Test status
Simulation time 532740287586 ps
CPU time 712.13 seconds
Started Aug 13 06:03:50 PM PDT 24
Finished Aug 13 06:15:43 PM PDT 24
Peak memory 202132 kb
Host smart-90cd14a0-ceb6-4550-b189-d41b58f74445
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050975780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1050975780
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.728021879
Short name T784
Test name
Test status
Simulation time 177484980810 ps
CPU time 90.43 seconds
Started Aug 13 06:03:51 PM PDT 24
Finished Aug 13 06:05:21 PM PDT 24
Peak memory 202032 kb
Host smart-8894231c-0b6c-4fc7-9f68-37cd5bc5ce5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728021879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.728021879
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.696997403
Short name T328
Test name
Test status
Simulation time 167442120218 ps
CPU time 201.48 seconds
Started Aug 13 06:03:51 PM PDT 24
Finished Aug 13 06:07:13 PM PDT 24
Peak memory 202104 kb
Host smart-3e02f194-26a8-4f6f-9ff9-7dd5c6deed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696997403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.696997403
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.251835970
Short name T693
Test name
Test status
Simulation time 490598339848 ps
CPU time 548.2 seconds
Started Aug 13 06:03:50 PM PDT 24
Finished Aug 13 06:12:58 PM PDT 24
Peak memory 202208 kb
Host smart-b5c2c253-d97c-4759-a8fd-8a3b0f5c1107
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=251835970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.251835970
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3329573240
Short name T713
Test name
Test status
Simulation time 159303863171 ps
CPU time 92.43 seconds
Started Aug 13 06:03:46 PM PDT 24
Finished Aug 13 06:05:18 PM PDT 24
Peak memory 202196 kb
Host smart-e703a0f6-61ee-4e40-a84e-a9618922f2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329573240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3329573240
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1452798112
Short name T682
Test name
Test status
Simulation time 500376262655 ps
CPU time 180.22 seconds
Started Aug 13 06:03:51 PM PDT 24
Finished Aug 13 06:06:51 PM PDT 24
Peak memory 202000 kb
Host smart-3081db6d-cc16-4fd3-8a51-43ad25347ece
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452798112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1452798112
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.533645073
Short name T659
Test name
Test status
Simulation time 551777294252 ps
CPU time 1266.25 seconds
Started Aug 13 06:03:40 PM PDT 24
Finished Aug 13 06:24:47 PM PDT 24
Peak memory 202260 kb
Host smart-52b7e626-1a41-4b6f-a8db-b0e1037aa8c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533645073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.533645073
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.217238653
Short name T684
Test name
Test status
Simulation time 591379312874 ps
CPU time 103.52 seconds
Started Aug 13 06:03:45 PM PDT 24
Finished Aug 13 06:05:29 PM PDT 24
Peak memory 202116 kb
Host smart-f43b7dc6-d648-40a9-96b6-6259e3feda79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217238653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.217238653
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.515151180
Short name T662
Test name
Test status
Simulation time 118421243646 ps
CPU time 493.35 seconds
Started Aug 13 06:03:48 PM PDT 24
Finished Aug 13 06:12:02 PM PDT 24
Peak memory 202412 kb
Host smart-a09ff541-6c8b-45c9-b0ee-c340b66ed6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515151180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.515151180
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3107173430
Short name T438
Test name
Test status
Simulation time 46815900359 ps
CPU time 15.57 seconds
Started Aug 13 06:03:46 PM PDT 24
Finished Aug 13 06:04:02 PM PDT 24
Peak memory 201936 kb
Host smart-8c42c5cc-1d42-4e9d-8dd1-8e952b5a0544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107173430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3107173430
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.556114377
Short name T556
Test name
Test status
Simulation time 5527176408 ps
CPU time 3.57 seconds
Started Aug 13 06:03:48 PM PDT 24
Finished Aug 13 06:03:52 PM PDT 24
Peak memory 202072 kb
Host smart-910d3df8-54fa-4c7e-8411-a7b0fc68a3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556114377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.556114377
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2993958430
Short name T562
Test name
Test status
Simulation time 5893685351 ps
CPU time 8.38 seconds
Started Aug 13 06:03:47 PM PDT 24
Finished Aug 13 06:03:55 PM PDT 24
Peak memory 201912 kb
Host smart-5cbfccf1-36ba-4172-ba71-dc7860b04e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993958430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2993958430
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1056288822
Short name T46
Test name
Test status
Simulation time 10561211307 ps
CPU time 11.22 seconds
Started Aug 13 06:03:53 PM PDT 24
Finished Aug 13 06:04:04 PM PDT 24
Peak memory 210492 kb
Host smart-a6ee3748-605d-455b-8396-1e00ee7dd331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056288822 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1056288822
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.675779259
Short name T545
Test name
Test status
Simulation time 428340459 ps
CPU time 0.8 seconds
Started Aug 13 06:04:07 PM PDT 24
Finished Aug 13 06:04:08 PM PDT 24
Peak memory 201968 kb
Host smart-fd4a0c07-0c17-4e33-83db-182937a44a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675779259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.675779259
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1097185969
Short name T403
Test name
Test status
Simulation time 159272953269 ps
CPU time 84.45 seconds
Started Aug 13 06:03:55 PM PDT 24
Finished Aug 13 06:05:19 PM PDT 24
Peak memory 202120 kb
Host smart-0e810f6f-7e10-4851-929f-8c0b74ff9a70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097185969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1097185969
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3580497739
Short name T178
Test name
Test status
Simulation time 315781023716 ps
CPU time 185.33 seconds
Started Aug 13 06:04:01 PM PDT 24
Finished Aug 13 06:07:06 PM PDT 24
Peak memory 202096 kb
Host smart-ff8b5507-902e-47b4-997c-c3a4de836425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580497739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3580497739
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2802900382
Short name T454
Test name
Test status
Simulation time 173130153907 ps
CPU time 208.52 seconds
Started Aug 13 06:04:00 PM PDT 24
Finished Aug 13 06:07:29 PM PDT 24
Peak memory 202048 kb
Host smart-00ad4ce7-37a4-4059-813b-4a03a949290d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802900382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2802900382
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4254025526
Short name T748
Test name
Test status
Simulation time 600484382385 ps
CPU time 1414.22 seconds
Started Aug 13 06:03:59 PM PDT 24
Finished Aug 13 06:27:33 PM PDT 24
Peak memory 202204 kb
Host smart-f78a653d-52cb-4331-81a4-076284c1e044
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254025526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4254025526
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1356061504
Short name T235
Test name
Test status
Simulation time 91393742064 ps
CPU time 363.26 seconds
Started Aug 13 06:04:01 PM PDT 24
Finished Aug 13 06:10:05 PM PDT 24
Peak memory 202464 kb
Host smart-5144f7b3-f54d-4a96-a9c8-5776c0d2427d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356061504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1356061504
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2511935787
Short name T399
Test name
Test status
Simulation time 25017966992 ps
CPU time 29.73 seconds
Started Aug 13 06:04:10 PM PDT 24
Finished Aug 13 06:04:40 PM PDT 24
Peak memory 201940 kb
Host smart-9d688cc0-5a2e-40be-ae6e-fb1872fa3a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511935787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2511935787
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1116488698
Short name T573
Test name
Test status
Simulation time 4256845869 ps
CPU time 5.16 seconds
Started Aug 13 06:04:11 PM PDT 24
Finished Aug 13 06:04:16 PM PDT 24
Peak memory 201912 kb
Host smart-ad2baab0-1c0d-430a-b3ce-fcc1637fd060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116488698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1116488698
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2029510628
Short name T794
Test name
Test status
Simulation time 6055274260 ps
CPU time 3.98 seconds
Started Aug 13 06:03:50 PM PDT 24
Finished Aug 13 06:03:54 PM PDT 24
Peak memory 201964 kb
Host smart-652c5382-fcdc-412a-8324-2fc858e0e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029510628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2029510628
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3106102131
Short name T6
Test name
Test status
Simulation time 37423646963 ps
CPU time 36.48 seconds
Started Aug 13 06:04:05 PM PDT 24
Finished Aug 13 06:04:41 PM PDT 24
Peak memory 201896 kb
Host smart-a6a1f7b5-54b6-4be2-ac91-8211b3e2bac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106102131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3106102131
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2524882544
Short name T43
Test name
Test status
Simulation time 13653957630 ps
CPU time 7.64 seconds
Started Aug 13 06:04:02 PM PDT 24
Finished Aug 13 06:04:10 PM PDT 24
Peak memory 210456 kb
Host smart-f0808b28-3646-4ee9-9016-189878770c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524882544 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2524882544
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1693117304
Short name T477
Test name
Test status
Simulation time 496491523 ps
CPU time 1.72 seconds
Started Aug 13 06:04:21 PM PDT 24
Finished Aug 13 06:04:22 PM PDT 24
Peak memory 201988 kb
Host smart-64e16dfa-4494-4b96-804b-55d6cb4a7cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693117304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1693117304
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1893904834
Short name T343
Test name
Test status
Simulation time 341697709543 ps
CPU time 189.25 seconds
Started Aug 13 06:04:10 PM PDT 24
Finished Aug 13 06:07:20 PM PDT 24
Peak memory 202104 kb
Host smart-b3ca977b-3ab2-4935-a41f-2b2d189f5a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893904834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1893904834
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1338116784
Short name T164
Test name
Test status
Simulation time 337384528183 ps
CPU time 689.95 seconds
Started Aug 13 06:04:04 PM PDT 24
Finished Aug 13 06:15:34 PM PDT 24
Peak memory 202112 kb
Host smart-effa4410-6ea5-4274-ab9b-549dcd5e893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338116784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1338116784
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1813665436
Short name T542
Test name
Test status
Simulation time 497222650397 ps
CPU time 591.8 seconds
Started Aug 13 06:04:11 PM PDT 24
Finished Aug 13 06:14:03 PM PDT 24
Peak memory 202160 kb
Host smart-cad4bac6-86df-4adc-9cc5-0554e6e83fff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813665436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1813665436
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3814722000
Short name T196
Test name
Test status
Simulation time 488434844735 ps
CPU time 290.61 seconds
Started Aug 13 06:04:09 PM PDT 24
Finished Aug 13 06:08:59 PM PDT 24
Peak memory 202024 kb
Host smart-7688ba24-fdbb-4fb1-9298-413ed053712a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814722000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3814722000
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.668634989
Short name T425
Test name
Test status
Simulation time 159245446281 ps
CPU time 21.86 seconds
Started Aug 13 06:04:17 PM PDT 24
Finished Aug 13 06:04:39 PM PDT 24
Peak memory 202120 kb
Host smart-ce0276b9-6281-48ea-aa36-04efbc95197b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=668634989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.668634989
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3889100866
Short name T689
Test name
Test status
Simulation time 569640154616 ps
CPU time 77.26 seconds
Started Aug 13 06:04:09 PM PDT 24
Finished Aug 13 06:05:27 PM PDT 24
Peak memory 202132 kb
Host smart-b80c2cfb-63e0-4c21-a813-9a24c366f82a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889100866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3889100866
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2444883985
Short name T57
Test name
Test status
Simulation time 194786636981 ps
CPU time 47.13 seconds
Started Aug 13 06:04:09 PM PDT 24
Finished Aug 13 06:04:57 PM PDT 24
Peak memory 202140 kb
Host smart-d94d5451-1e23-459b-836f-aeee981c034e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444883985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2444883985
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2695868289
Short name T790
Test name
Test status
Simulation time 122096741172 ps
CPU time 668.82 seconds
Started Aug 13 06:04:08 PM PDT 24
Finished Aug 13 06:15:17 PM PDT 24
Peak memory 202388 kb
Host smart-f94bf881-ad7f-4502-9bf6-12ff4251f538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695868289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2695868289
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.844920743
Short name T41
Test name
Test status
Simulation time 23280883539 ps
CPU time 25.88 seconds
Started Aug 13 06:04:14 PM PDT 24
Finished Aug 13 06:04:40 PM PDT 24
Peak memory 201940 kb
Host smart-a54ab76c-161b-4842-8db3-6cb3cd79315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844920743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.844920743
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1154296160
Short name T566
Test name
Test status
Simulation time 3928452378 ps
CPU time 11.08 seconds
Started Aug 13 06:04:11 PM PDT 24
Finished Aug 13 06:04:22 PM PDT 24
Peak memory 201968 kb
Host smart-6cc8930b-576a-4729-920b-16c4ad2a32c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154296160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1154296160
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.473525259
Short name T601
Test name
Test status
Simulation time 5960690446 ps
CPU time 4.22 seconds
Started Aug 13 06:04:10 PM PDT 24
Finished Aug 13 06:04:14 PM PDT 24
Peak memory 201876 kb
Host smart-a99cb1d4-3cf1-4120-9685-1822f3fcba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473525259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.473525259
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1554567863
Short name T38
Test name
Test status
Simulation time 536725192056 ps
CPU time 644.08 seconds
Started Aug 13 06:04:10 PM PDT 24
Finished Aug 13 06:14:54 PM PDT 24
Peak memory 202064 kb
Host smart-62c2e4cf-a0f1-440b-b763-4cf679af3414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554567863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1554567863
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.719810271
Short name T654
Test name
Test status
Simulation time 500521256 ps
CPU time 0.93 seconds
Started Aug 13 06:04:30 PM PDT 24
Finished Aug 13 06:04:32 PM PDT 24
Peak memory 201992 kb
Host smart-0fefdc57-19b9-4c89-85d1-f7db0940f88e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719810271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.719810271
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1672729233
Short name T735
Test name
Test status
Simulation time 437907237079 ps
CPU time 945.57 seconds
Started Aug 13 06:04:21 PM PDT 24
Finished Aug 13 06:20:07 PM PDT 24
Peak memory 202116 kb
Host smart-7e446393-4c6e-49b3-b701-f89f727712fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672729233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1672729233
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2412409833
Short name T335
Test name
Test status
Simulation time 489935535038 ps
CPU time 1146.86 seconds
Started Aug 13 06:04:20 PM PDT 24
Finished Aug 13 06:23:27 PM PDT 24
Peak memory 202144 kb
Host smart-59f0d7c4-f6ce-4009-8ea9-15b6bf58959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412409833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2412409833
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2971284692
Short name T490
Test name
Test status
Simulation time 170311851269 ps
CPU time 382.31 seconds
Started Aug 13 06:04:20 PM PDT 24
Finished Aug 13 06:10:43 PM PDT 24
Peak memory 202140 kb
Host smart-442363d4-60ff-44e0-b89a-9e1809ae60d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971284692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2971284692
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.472694541
Short name T156
Test name
Test status
Simulation time 334917413310 ps
CPU time 188.92 seconds
Started Aug 13 06:04:18 PM PDT 24
Finished Aug 13 06:07:27 PM PDT 24
Peak memory 202160 kb
Host smart-42879a51-61a9-497e-9c15-91045ffeb700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472694541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.472694541
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3709160287
Short name T462
Test name
Test status
Simulation time 327164886225 ps
CPU time 147.75 seconds
Started Aug 13 06:04:18 PM PDT 24
Finished Aug 13 06:06:46 PM PDT 24
Peak memory 202136 kb
Host smart-3117d991-56ea-4520-8c17-1c85f467a4fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709160287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3709160287
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2344017227
Short name T348
Test name
Test status
Simulation time 166703012025 ps
CPU time 345.74 seconds
Started Aug 13 06:04:14 PM PDT 24
Finished Aug 13 06:10:00 PM PDT 24
Peak memory 202108 kb
Host smart-17e87fb5-b00e-459a-968c-588ec6f3b5e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344017227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2344017227
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3643488939
Short name T547
Test name
Test status
Simulation time 398979630795 ps
CPU time 232.66 seconds
Started Aug 13 06:04:14 PM PDT 24
Finished Aug 13 06:08:07 PM PDT 24
Peak memory 202164 kb
Host smart-59b0193a-b61e-4e99-b351-f087468627f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643488939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3643488939
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.390629805
Short name T248
Test name
Test status
Simulation time 111061233488 ps
CPU time 361.83 seconds
Started Aug 13 06:04:24 PM PDT 24
Finished Aug 13 06:10:26 PM PDT 24
Peak memory 202408 kb
Host smart-de87f9ed-3986-474f-abb6-adefceca9495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390629805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.390629805
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1615742208
Short name T372
Test name
Test status
Simulation time 39277617998 ps
CPU time 10.78 seconds
Started Aug 13 06:04:25 PM PDT 24
Finished Aug 13 06:04:36 PM PDT 24
Peak memory 201956 kb
Host smart-0d2fb2e8-473d-4843-bc37-e5b214a71aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615742208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1615742208
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2008241946
Short name T214
Test name
Test status
Simulation time 4927173523 ps
CPU time 3.15 seconds
Started Aug 13 06:04:26 PM PDT 24
Finished Aug 13 06:04:30 PM PDT 24
Peak memory 201968 kb
Host smart-a15e3a2d-6648-465a-93c5-a28098af0dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008241946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2008241946
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4131151190
Short name T548
Test name
Test status
Simulation time 5674602824 ps
CPU time 7.19 seconds
Started Aug 13 06:04:18 PM PDT 24
Finished Aug 13 06:04:25 PM PDT 24
Peak memory 201972 kb
Host smart-c172ffb9-3475-49e2-ab1d-1a9e9dc5d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131151190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4131151190
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1380327325
Short name T63
Test name
Test status
Simulation time 129155334083 ps
CPU time 690.41 seconds
Started Aug 13 06:04:21 PM PDT 24
Finished Aug 13 06:15:52 PM PDT 24
Peak memory 202388 kb
Host smart-562231a0-3485-478e-bc5a-5fe6194fd59b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380327325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1380327325
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.968952164
Short name T20
Test name
Test status
Simulation time 4022075413 ps
CPU time 17.11 seconds
Started Aug 13 06:04:27 PM PDT 24
Finished Aug 13 06:04:44 PM PDT 24
Peak memory 210384 kb
Host smart-607dcfdc-b432-49ac-becf-6ffcaa5b28f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968952164 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.968952164
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.748167940
Short name T380
Test name
Test status
Simulation time 315936918 ps
CPU time 0.82 seconds
Started Aug 13 06:04:37 PM PDT 24
Finished Aug 13 06:04:38 PM PDT 24
Peak memory 201988 kb
Host smart-22b6ed5b-040a-41a1-8419-6ebefbd56288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748167940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.748167940
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1240803105
Short name T254
Test name
Test status
Simulation time 170992335929 ps
CPU time 384.65 seconds
Started Aug 13 06:04:32 PM PDT 24
Finished Aug 13 06:10:57 PM PDT 24
Peak memory 202156 kb
Host smart-26704065-da5a-415f-9a49-7115f37ae4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240803105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1240803105
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2385794175
Short name T28
Test name
Test status
Simulation time 323007126969 ps
CPU time 323.2 seconds
Started Aug 13 06:04:24 PM PDT 24
Finished Aug 13 06:09:47 PM PDT 24
Peak memory 202128 kb
Host smart-918fb4f9-0b95-40a5-8f4d-c06a09829899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385794175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2385794175
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3416728916
Short name T215
Test name
Test status
Simulation time 330208717026 ps
CPU time 730.2 seconds
Started Aug 13 06:04:31 PM PDT 24
Finished Aug 13 06:16:42 PM PDT 24
Peak memory 202216 kb
Host smart-f370a5f1-45d8-41b7-8ff3-11af6bf36f29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416728916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3416728916
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3886527291
Short name T195
Test name
Test status
Simulation time 165058794395 ps
CPU time 369.97 seconds
Started Aug 13 06:04:25 PM PDT 24
Finished Aug 13 06:10:35 PM PDT 24
Peak memory 202152 kb
Host smart-46115d5f-fd30-403e-a0b7-c0dbbb68140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886527291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3886527291
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2382833696
Short name T463
Test name
Test status
Simulation time 331107256837 ps
CPU time 186.69 seconds
Started Aug 13 06:04:25 PM PDT 24
Finished Aug 13 06:07:32 PM PDT 24
Peak memory 202208 kb
Host smart-3f7e616e-b70d-4ac9-b345-5931acd50bff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382833696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2382833696
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.765717032
Short name T796
Test name
Test status
Simulation time 189239494959 ps
CPU time 434.02 seconds
Started Aug 13 06:04:24 PM PDT 24
Finished Aug 13 06:11:38 PM PDT 24
Peak memory 202144 kb
Host smart-9599dfb8-8c57-471a-8698-78ca9e374109
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765717032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.765717032
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3854057554
Short name T374
Test name
Test status
Simulation time 394710680238 ps
CPU time 961.99 seconds
Started Aug 13 06:04:25 PM PDT 24
Finished Aug 13 06:20:27 PM PDT 24
Peak memory 202132 kb
Host smart-7e5bab0c-32ff-4d02-8c3e-92e037b8158d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854057554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3854057554
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3832695198
Short name T231
Test name
Test status
Simulation time 67498483386 ps
CPU time 407.78 seconds
Started Aug 13 06:04:34 PM PDT 24
Finished Aug 13 06:11:22 PM PDT 24
Peak memory 202352 kb
Host smart-f2a0d36a-4c6c-4705-b7c3-703d2e31aaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832695198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3832695198
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1769004859
Short name T535
Test name
Test status
Simulation time 23663780344 ps
CPU time 8.21 seconds
Started Aug 13 06:04:30 PM PDT 24
Finished Aug 13 06:04:38 PM PDT 24
Peak memory 201916 kb
Host smart-ca0df675-a729-469f-8b5e-36e53de06705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769004859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1769004859
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2705575703
Short name T793
Test name
Test status
Simulation time 5017250718 ps
CPU time 12.77 seconds
Started Aug 13 06:04:27 PM PDT 24
Finished Aug 13 06:04:40 PM PDT 24
Peak memory 201968 kb
Host smart-9c1fce83-a7bb-49dd-bbfc-5e25c246936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705575703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2705575703
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.432904714
Short name T409
Test name
Test status
Simulation time 5674208659 ps
CPU time 15.08 seconds
Started Aug 13 06:04:34 PM PDT 24
Finished Aug 13 06:04:49 PM PDT 24
Peak memory 201972 kb
Host smart-a9977e68-b783-4555-afd1-b7fdb4e40357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432904714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.432904714
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1470157258
Short name T257
Test name
Test status
Simulation time 338349224046 ps
CPU time 384.74 seconds
Started Aug 13 06:04:32 PM PDT 24
Finished Aug 13 06:10:57 PM PDT 24
Peak memory 202204 kb
Host smart-633ca138-1c64-4a35-aa9c-08cbf7f00796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470157258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1470157258
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2171346090
Short name T615
Test name
Test status
Simulation time 511511085 ps
CPU time 0.92 seconds
Started Aug 13 06:04:47 PM PDT 24
Finished Aug 13 06:04:48 PM PDT 24
Peak memory 202008 kb
Host smart-9361e677-7066-450a-9f88-45f84c82b2ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171346090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2171346090
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.573059881
Short name T305
Test name
Test status
Simulation time 505547209173 ps
CPU time 204.9 seconds
Started Aug 13 06:04:36 PM PDT 24
Finished Aug 13 06:08:01 PM PDT 24
Peak memory 202152 kb
Host smart-cc08ad46-6b04-4713-9739-f5cdf6b5956c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573059881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.573059881
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4281819052
Short name T269
Test name
Test status
Simulation time 174761081123 ps
CPU time 99.3 seconds
Started Aug 13 06:04:36 PM PDT 24
Finished Aug 13 06:06:15 PM PDT 24
Peak memory 202136 kb
Host smart-ee0dfa3d-8ff7-45e2-829c-f2c513e3f08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281819052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4281819052
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.654121790
Short name T511
Test name
Test status
Simulation time 497908615137 ps
CPU time 1076.07 seconds
Started Aug 13 06:04:43 PM PDT 24
Finished Aug 13 06:22:39 PM PDT 24
Peak memory 202148 kb
Host smart-84dadb93-c210-4281-b3a1-a877bc807678
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=654121790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.654121790
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3499950056
Short name T580
Test name
Test status
Simulation time 166164283534 ps
CPU time 372.08 seconds
Started Aug 13 06:04:32 PM PDT 24
Finished Aug 13 06:10:44 PM PDT 24
Peak memory 202144 kb
Host smart-e7cdc249-799e-4a6d-a1ec-ce62e5292018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499950056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3499950056
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3365391406
Short name T473
Test name
Test status
Simulation time 336415706232 ps
CPU time 354.74 seconds
Started Aug 13 06:04:42 PM PDT 24
Finished Aug 13 06:10:37 PM PDT 24
Peak memory 202116 kb
Host smart-94a0eb75-cb70-4c7f-994c-72cb78a3cea8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365391406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3365391406
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.892043931
Short name T279
Test name
Test status
Simulation time 354296242293 ps
CPU time 827.28 seconds
Started Aug 13 06:04:47 PM PDT 24
Finished Aug 13 06:18:35 PM PDT 24
Peak memory 202044 kb
Host smart-c7361ef3-844c-4698-9dcf-ca29d3590401
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892043931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.892043931
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3153050257
Short name T774
Test name
Test status
Simulation time 602544412780 ps
CPU time 380.15 seconds
Started Aug 13 06:04:51 PM PDT 24
Finished Aug 13 06:11:11 PM PDT 24
Peak memory 202028 kb
Host smart-325e15e8-6295-4a9a-b186-7e2e78163e8d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153050257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3153050257
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1733198239
Short name T249
Test name
Test status
Simulation time 80747791239 ps
CPU time 266.1 seconds
Started Aug 13 06:04:41 PM PDT 24
Finished Aug 13 06:09:07 PM PDT 24
Peak memory 202392 kb
Host smart-f06d97c0-ba5b-4b04-8ba0-ab27368c9b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733198239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1733198239
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3712977193
Short name T753
Test name
Test status
Simulation time 22700177737 ps
CPU time 14.41 seconds
Started Aug 13 06:04:40 PM PDT 24
Finished Aug 13 06:04:54 PM PDT 24
Peak memory 201940 kb
Host smart-45f2da70-8335-4e15-a3fd-294644358821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712977193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3712977193
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2829407192
Short name T394
Test name
Test status
Simulation time 4450159204 ps
CPU time 2.54 seconds
Started Aug 13 06:04:39 PM PDT 24
Finished Aug 13 06:04:42 PM PDT 24
Peak memory 201968 kb
Host smart-20c273c3-a027-42f0-aae2-2c789a9147e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829407192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2829407192
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1818160495
Short name T599
Test name
Test status
Simulation time 5904330709 ps
CPU time 13.94 seconds
Started Aug 13 06:04:32 PM PDT 24
Finished Aug 13 06:04:46 PM PDT 24
Peak memory 201976 kb
Host smart-ebae5e75-afbc-4d5a-8652-b348514bcc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818160495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1818160495
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2761495162
Short name T34
Test name
Test status
Simulation time 145517898600 ps
CPU time 422.5 seconds
Started Aug 13 06:04:48 PM PDT 24
Finished Aug 13 06:11:51 PM PDT 24
Peak memory 202336 kb
Host smart-96186b13-8cf1-41bf-b374-317e5c8db24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761495162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2761495162
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.468347723
Short name T420
Test name
Test status
Simulation time 308324814 ps
CPU time 0.78 seconds
Started Aug 13 06:04:57 PM PDT 24
Finished Aug 13 06:04:58 PM PDT 24
Peak memory 202004 kb
Host smart-19a55359-d2c9-4279-94ab-b00e0afa7094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468347723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.468347723
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.395347352
Short name T750
Test name
Test status
Simulation time 167566295203 ps
CPU time 193.14 seconds
Started Aug 13 06:04:47 PM PDT 24
Finished Aug 13 06:08:00 PM PDT 24
Peak memory 202152 kb
Host smart-e7a09100-44ec-466a-ae52-5d03c67dc242
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395347352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.395347352
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1710431174
Short name T14
Test name
Test status
Simulation time 164161876570 ps
CPU time 113.01 seconds
Started Aug 13 06:04:47 PM PDT 24
Finished Aug 13 06:06:40 PM PDT 24
Peak memory 202048 kb
Host smart-9ecc5fc5-befd-4678-8578-a8f2e5391c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710431174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1710431174
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4000348603
Short name T745
Test name
Test status
Simulation time 329292143335 ps
CPU time 737.38 seconds
Started Aug 13 06:04:47 PM PDT 24
Finished Aug 13 06:17:05 PM PDT 24
Peak memory 202176 kb
Host smart-d12a1771-e3bb-49c2-9d7f-fb188ebf9787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000348603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4000348603
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2089839389
Short name T494
Test name
Test status
Simulation time 329307616905 ps
CPU time 760.31 seconds
Started Aug 13 06:04:49 PM PDT 24
Finished Aug 13 06:17:29 PM PDT 24
Peak memory 202164 kb
Host smart-5ca938e9-abf3-4ffa-877d-4a4cf6f663db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089839389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2089839389
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1780744077
Short name T594
Test name
Test status
Simulation time 321564895597 ps
CPU time 754.55 seconds
Started Aug 13 06:04:48 PM PDT 24
Finished Aug 13 06:17:22 PM PDT 24
Peak memory 202144 kb
Host smart-6ce3d69a-839e-4ac6-9578-c7723c1280d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780744077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1780744077
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3211072751
Short name T388
Test name
Test status
Simulation time 494317183046 ps
CPU time 343.52 seconds
Started Aug 13 06:04:42 PM PDT 24
Finished Aug 13 06:10:26 PM PDT 24
Peak memory 202096 kb
Host smart-a3fd8703-70a9-4537-bce5-27642589dad0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211072751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3211072751
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.188319983
Short name T443
Test name
Test status
Simulation time 397270110614 ps
CPU time 908.12 seconds
Started Aug 13 06:04:47 PM PDT 24
Finished Aug 13 06:19:55 PM PDT 24
Peak memory 202160 kb
Host smart-4073b8b7-8674-433b-9d39-e538da76bbb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188319983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.188319983
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1429359627
Short name T614
Test name
Test status
Simulation time 130205658473 ps
CPU time 636.33 seconds
Started Aug 13 06:04:59 PM PDT 24
Finished Aug 13 06:15:36 PM PDT 24
Peak memory 202368 kb
Host smart-ebc4050d-37f9-4d88-9a5d-612b91a75ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429359627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1429359627
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.433888109
Short name T558
Test name
Test status
Simulation time 38312292301 ps
CPU time 23.34 seconds
Started Aug 13 06:04:58 PM PDT 24
Finished Aug 13 06:05:21 PM PDT 24
Peak memory 201840 kb
Host smart-843a2924-ba69-4072-9772-fe7412f5df8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433888109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.433888109
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2150807931
Short name T536
Test name
Test status
Simulation time 3341027506 ps
CPU time 8.46 seconds
Started Aug 13 06:04:51 PM PDT 24
Finished Aug 13 06:05:00 PM PDT 24
Peak memory 201948 kb
Host smart-b687c59c-c742-4f21-a685-d169c5bab005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150807931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2150807931
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3976848929
Short name T622
Test name
Test status
Simulation time 5704899123 ps
CPU time 8.14 seconds
Started Aug 13 06:04:48 PM PDT 24
Finished Aug 13 06:04:56 PM PDT 24
Peak memory 201928 kb
Host smart-2f232c82-0ed8-4cc9-b32c-f8733dcab447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976848929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3976848929
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1133459958
Short name T59
Test name
Test status
Simulation time 300574234624 ps
CPU time 912.55 seconds
Started Aug 13 06:04:54 PM PDT 24
Finished Aug 13 06:20:07 PM PDT 24
Peak memory 218776 kb
Host smart-4b3698a5-010c-4785-9872-141847b7a18b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133459958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1133459958
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3186934931
Short name T113
Test name
Test status
Simulation time 19508386769 ps
CPU time 16.8 seconds
Started Aug 13 06:04:55 PM PDT 24
Finished Aug 13 06:05:12 PM PDT 24
Peak memory 210792 kb
Host smart-c3ea7f4e-cfc5-4e5e-8c9b-2cfe1e8cd469
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186934931 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3186934931
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1543397356
Short name T411
Test name
Test status
Simulation time 334140276 ps
CPU time 0.83 seconds
Started Aug 13 06:01:06 PM PDT 24
Finished Aug 13 06:01:07 PM PDT 24
Peak memory 201952 kb
Host smart-ca623a4d-42be-462a-b43d-1dfe3849e442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543397356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1543397356
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2630526314
Short name T152
Test name
Test status
Simulation time 335300709990 ps
CPU time 826.27 seconds
Started Aug 13 06:00:51 PM PDT 24
Finished Aug 13 06:14:37 PM PDT 24
Peak memory 202124 kb
Host smart-a49a84e7-0b96-4f84-b42f-9b15d0d7f476
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630526314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2630526314
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1133379123
Short name T632
Test name
Test status
Simulation time 321099648954 ps
CPU time 307.41 seconds
Started Aug 13 06:00:53 PM PDT 24
Finished Aug 13 06:06:00 PM PDT 24
Peak memory 202172 kb
Host smart-83f01c37-b7c0-4d53-a89c-2272b80e57a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133379123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1133379123
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.997585701
Short name T762
Test name
Test status
Simulation time 163843989032 ps
CPU time 92.63 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:02:24 PM PDT 24
Peak memory 202148 kb
Host smart-582e2889-0f87-4bd1-b44c-6cdbfe0e5c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997585701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.997585701
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3569974754
Short name T642
Test name
Test status
Simulation time 159589826362 ps
CPU time 385.81 seconds
Started Aug 13 06:00:53 PM PDT 24
Finished Aug 13 06:07:19 PM PDT 24
Peak memory 202136 kb
Host smart-2d9bc3b4-17a1-4a07-8eee-b880e796a931
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569974754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3569974754
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3950681019
Short name T356
Test name
Test status
Simulation time 328398426680 ps
CPU time 198.17 seconds
Started Aug 13 06:00:55 PM PDT 24
Finished Aug 13 06:04:13 PM PDT 24
Peak memory 202132 kb
Host smart-425c2d24-a888-433d-bbd1-24e66de5a97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950681019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3950681019
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.422101313
Short name T5
Test name
Test status
Simulation time 330676008887 ps
CPU time 184.81 seconds
Started Aug 13 06:00:54 PM PDT 24
Finished Aug 13 06:03:59 PM PDT 24
Peak memory 202116 kb
Host smart-5969685d-ece9-4fe2-a269-bc94918ce2a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=422101313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.422101313
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3918404189
Short name T221
Test name
Test status
Simulation time 375921941294 ps
CPU time 91.4 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:02:24 PM PDT 24
Peak memory 202064 kb
Host smart-aa760227-f7f2-4d6d-9774-5c695940a51f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918404189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3918404189
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.628375495
Short name T518
Test name
Test status
Simulation time 582909236453 ps
CPU time 673.7 seconds
Started Aug 13 06:00:52 PM PDT 24
Finished Aug 13 06:12:05 PM PDT 24
Peak memory 202160 kb
Host smart-d0d29d68-d416-4c80-940c-947f988ef920
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628375495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.628375495
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1878980881
Short name T681
Test name
Test status
Simulation time 101443317979 ps
CPU time 477.52 seconds
Started Aug 13 06:01:08 PM PDT 24
Finished Aug 13 06:09:05 PM PDT 24
Peak memory 202456 kb
Host smart-9f70dde5-8b91-46c1-b586-f3df5856ddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878980881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1878980881
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1493398794
Short name T759
Test name
Test status
Simulation time 23065914131 ps
CPU time 14.22 seconds
Started Aug 13 06:01:06 PM PDT 24
Finished Aug 13 06:01:20 PM PDT 24
Peak memory 201920 kb
Host smart-b57acad0-610e-4f64-b5be-e47f9f4e5567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493398794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1493398794
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1533195518
Short name T386
Test name
Test status
Simulation time 4849397239 ps
CPU time 11.7 seconds
Started Aug 13 06:01:04 PM PDT 24
Finished Aug 13 06:01:16 PM PDT 24
Peak memory 201964 kb
Host smart-4bda0764-60db-4a7b-b9fd-6db41246eeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533195518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1533195518
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.4086003758
Short name T78
Test name
Test status
Simulation time 4042998052 ps
CPU time 9.94 seconds
Started Aug 13 06:01:06 PM PDT 24
Finished Aug 13 06:01:16 PM PDT 24
Peak memory 217464 kb
Host smart-2dd0b9e7-6ef4-4321-8047-5d82c8128964
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086003758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.4086003758
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1383884033
Short name T456
Test name
Test status
Simulation time 5818320655 ps
CPU time 4.65 seconds
Started Aug 13 06:00:55 PM PDT 24
Finished Aug 13 06:01:00 PM PDT 24
Peak memory 201972 kb
Host smart-5378f8b5-78ff-4b6d-bcec-a71d4688f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383884033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1383884033
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2754129621
Short name T550
Test name
Test status
Simulation time 41459735135 ps
CPU time 100.37 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:02:45 PM PDT 24
Peak memory 201976 kb
Host smart-4d573b92-5e8e-49d2-a9aa-e9be1ffacd30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754129621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2754129621
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3642809149
Short name T499
Test name
Test status
Simulation time 3566231769 ps
CPU time 15.3 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:01:21 PM PDT 24
Peak memory 210720 kb
Host smart-eed73149-d923-4145-a715-0c2f3d190ae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642809149 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3642809149
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2827302199
Short name T579
Test name
Test status
Simulation time 392958272 ps
CPU time 1.53 seconds
Started Aug 13 06:05:07 PM PDT 24
Finished Aug 13 06:05:09 PM PDT 24
Peak memory 201868 kb
Host smart-c277806c-cd9c-4cc2-ab35-051782c73cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827302199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2827302199
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1354694850
Short name T523
Test name
Test status
Simulation time 190885767754 ps
CPU time 11.99 seconds
Started Aug 13 06:04:59 PM PDT 24
Finished Aug 13 06:05:12 PM PDT 24
Peak memory 202160 kb
Host smart-a4ef6221-ef7f-4ebe-a22d-d0f5d97c8e8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354694850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1354694850
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2479573594
Short name T286
Test name
Test status
Simulation time 333311290061 ps
CPU time 807.96 seconds
Started Aug 13 06:04:53 PM PDT 24
Finished Aug 13 06:18:21 PM PDT 24
Peak memory 202040 kb
Host smart-73b9b025-5037-4762-b669-f0326c9cc867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479573594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2479573594
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3404395381
Short name T546
Test name
Test status
Simulation time 489338737264 ps
CPU time 535.77 seconds
Started Aug 13 06:04:54 PM PDT 24
Finished Aug 13 06:13:50 PM PDT 24
Peak memory 202204 kb
Host smart-6b6b4116-99d0-4ef8-8ad7-7b7aa10829fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404395381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3404395381
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.368392129
Short name T431
Test name
Test status
Simulation time 162564563724 ps
CPU time 97.41 seconds
Started Aug 13 06:04:58 PM PDT 24
Finished Aug 13 06:06:35 PM PDT 24
Peak memory 202052 kb
Host smart-76e61a72-5f19-4bfe-a783-14880a209b82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=368392129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.368392129
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1216342428
Short name T181
Test name
Test status
Simulation time 346263750670 ps
CPU time 709.88 seconds
Started Aug 13 06:05:00 PM PDT 24
Finished Aug 13 06:16:50 PM PDT 24
Peak memory 202012 kb
Host smart-e79db7d1-a6db-4d3d-82d6-fd543c7ca0b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216342428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1216342428
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3631238173
Short name T703
Test name
Test status
Simulation time 194606995000 ps
CPU time 427.79 seconds
Started Aug 13 06:05:06 PM PDT 24
Finished Aug 13 06:12:14 PM PDT 24
Peak memory 202120 kb
Host smart-da8bff72-f559-4677-96e3-ea3fefa97994
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631238173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3631238173
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1767800851
Short name T576
Test name
Test status
Simulation time 76256462513 ps
CPU time 226.77 seconds
Started Aug 13 06:05:06 PM PDT 24
Finished Aug 13 06:08:53 PM PDT 24
Peak memory 202368 kb
Host smart-4ce27f9e-1313-45cb-bc55-1ab471362b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767800851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1767800851
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1966933023
Short name T665
Test name
Test status
Simulation time 25134771870 ps
CPU time 57.74 seconds
Started Aug 13 06:04:59 PM PDT 24
Finished Aug 13 06:05:57 PM PDT 24
Peak memory 201884 kb
Host smart-22b4962e-0e17-4a8c-8fdf-d272e6061285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966933023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1966933023
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2494723530
Short name T172
Test name
Test status
Simulation time 4654220133 ps
CPU time 11.39 seconds
Started Aug 13 06:04:59 PM PDT 24
Finished Aug 13 06:05:11 PM PDT 24
Peak memory 201924 kb
Host smart-08f9e7b6-b324-4ae1-881d-9697c78c4098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494723530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2494723530
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1734020682
Short name T766
Test name
Test status
Simulation time 6037133210 ps
CPU time 6.35 seconds
Started Aug 13 06:04:58 PM PDT 24
Finished Aug 13 06:05:04 PM PDT 24
Peak memory 201840 kb
Host smart-69afff50-0e08-48fb-9219-b18b908d34b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734020682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1734020682
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2518429635
Short name T260
Test name
Test status
Simulation time 697071794383 ps
CPU time 477.05 seconds
Started Aug 13 06:04:59 PM PDT 24
Finished Aug 13 06:12:56 PM PDT 24
Peak memory 202128 kb
Host smart-df1d5016-c2a4-44fb-93f4-7f180669cef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518429635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2518429635
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1841800655
Short name T18
Test name
Test status
Simulation time 3163804091 ps
CPU time 10.61 seconds
Started Aug 13 06:05:08 PM PDT 24
Finished Aug 13 06:05:18 PM PDT 24
Peak memory 202332 kb
Host smart-fc6ef60f-854b-4b03-8233-961ce788ee48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841800655 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1841800655
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.421610661
Short name T555
Test name
Test status
Simulation time 487276409 ps
CPU time 0.9 seconds
Started Aug 13 06:05:11 PM PDT 24
Finished Aug 13 06:05:12 PM PDT 24
Peak memory 201996 kb
Host smart-ed3a0783-2c07-471f-bf01-b313df66e04c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421610661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.421610661
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.281839439
Short name T534
Test name
Test status
Simulation time 335686796188 ps
CPU time 369.3 seconds
Started Aug 13 06:05:07 PM PDT 24
Finished Aug 13 06:11:16 PM PDT 24
Peak memory 202104 kb
Host smart-e6e97dbe-aa3c-42d9-a6ad-19d50969bda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281839439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.281839439
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3573887179
Short name T695
Test name
Test status
Simulation time 162619076072 ps
CPU time 358.22 seconds
Started Aug 13 06:05:04 PM PDT 24
Finished Aug 13 06:11:03 PM PDT 24
Peak memory 202204 kb
Host smart-fad90b00-84a1-4394-8163-1e77d0a9b98a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573887179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3573887179
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2196823663
Short name T616
Test name
Test status
Simulation time 493924630433 ps
CPU time 908.68 seconds
Started Aug 13 06:05:08 PM PDT 24
Finished Aug 13 06:20:17 PM PDT 24
Peak memory 202068 kb
Host smart-c38cbce5-75e7-4438-843d-e030e904c9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196823663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2196823663
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2742581748
Short name T396
Test name
Test status
Simulation time 478755110897 ps
CPU time 555.28 seconds
Started Aug 13 06:05:08 PM PDT 24
Finished Aug 13 06:14:23 PM PDT 24
Peak memory 202136 kb
Host smart-25d62435-e6b4-4a32-8f64-b41dfb3c277c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742581748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2742581748
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1722215875
Short name T769
Test name
Test status
Simulation time 594695008300 ps
CPU time 737.94 seconds
Started Aug 13 06:05:08 PM PDT 24
Finished Aug 13 06:17:26 PM PDT 24
Peak memory 202064 kb
Host smart-78f3cf8f-4d4b-4239-8053-72e9493c9a14
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722215875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1722215875
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.766512601
Short name T641
Test name
Test status
Simulation time 125708437408 ps
CPU time 376.02 seconds
Started Aug 13 06:05:06 PM PDT 24
Finished Aug 13 06:11:22 PM PDT 24
Peak memory 202388 kb
Host smart-f90a39d1-66c1-4343-8337-5248c024bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766512601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.766512601
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1069961057
Short name T738
Test name
Test status
Simulation time 39271366442 ps
CPU time 93.97 seconds
Started Aug 13 06:05:06 PM PDT 24
Finished Aug 13 06:06:40 PM PDT 24
Peak memory 201964 kb
Host smart-6ba36938-fbcf-4a66-ac99-65080ed12f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069961057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1069961057
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1287298293
Short name T565
Test name
Test status
Simulation time 3432347062 ps
CPU time 8.45 seconds
Started Aug 13 06:05:07 PM PDT 24
Finished Aug 13 06:05:15 PM PDT 24
Peak memory 201968 kb
Host smart-542a09e6-058e-427a-bf5b-75033b72b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287298293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1287298293
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1588609448
Short name T768
Test name
Test status
Simulation time 6006500395 ps
CPU time 13.95 seconds
Started Aug 13 06:05:07 PM PDT 24
Finished Aug 13 06:05:21 PM PDT 24
Peak memory 201964 kb
Host smart-4929b592-97d1-4e58-b0fe-503d8e28be39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588609448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1588609448
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1534751168
Short name T193
Test name
Test status
Simulation time 530244324325 ps
CPU time 332.89 seconds
Started Aug 13 06:05:08 PM PDT 24
Finished Aug 13 06:10:41 PM PDT 24
Peak memory 202128 kb
Host smart-5e491ee5-ab0e-4fb4-aaf7-df4ad2e3e2ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534751168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1534751168
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3171972326
Short name T50
Test name
Test status
Simulation time 60043575904 ps
CPU time 10.6 seconds
Started Aug 13 06:05:07 PM PDT 24
Finished Aug 13 06:05:18 PM PDT 24
Peak memory 211172 kb
Host smart-71fcb9ad-1c86-40fa-932f-eb0d800d4ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171972326 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3171972326
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1657687161
Short name T384
Test name
Test status
Simulation time 446003762 ps
CPU time 1.62 seconds
Started Aug 13 06:05:21 PM PDT 24
Finished Aug 13 06:05:23 PM PDT 24
Peak memory 201904 kb
Host smart-c24d13ea-032a-4b60-b196-9229c9e31130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657687161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1657687161
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3070834553
Short name T619
Test name
Test status
Simulation time 329450361091 ps
CPU time 191.26 seconds
Started Aug 13 06:05:22 PM PDT 24
Finished Aug 13 06:08:33 PM PDT 24
Peak memory 202156 kb
Host smart-3c15cbfd-183c-4314-a671-2c677005b662
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070834553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3070834553
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1671866491
Short name T182
Test name
Test status
Simulation time 329215771686 ps
CPU time 69.46 seconds
Started Aug 13 06:05:21 PM PDT 24
Finished Aug 13 06:06:31 PM PDT 24
Peak memory 202140 kb
Host smart-a464cdca-f324-4d1f-9270-8338ac266e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671866491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1671866491
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1258588348
Short name T204
Test name
Test status
Simulation time 161306836465 ps
CPU time 101.16 seconds
Started Aug 13 06:05:13 PM PDT 24
Finished Aug 13 06:06:55 PM PDT 24
Peak memory 202128 kb
Host smart-1ea63b47-72d8-43ae-96ad-adfc9d8d5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258588348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1258588348
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4041086201
Short name T728
Test name
Test status
Simulation time 167562968501 ps
CPU time 352.04 seconds
Started Aug 13 06:05:14 PM PDT 24
Finished Aug 13 06:11:06 PM PDT 24
Peak memory 202204 kb
Host smart-c3ddb534-4111-44ef-adda-0fba19f44f39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041086201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.4041086201
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1574134527
Short name T683
Test name
Test status
Simulation time 328632611971 ps
CPU time 750.38 seconds
Started Aug 13 06:05:14 PM PDT 24
Finished Aug 13 06:17:45 PM PDT 24
Peak memory 202144 kb
Host smart-630efbbd-c9b8-4741-9217-92946d4bb4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574134527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1574134527
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3021049448
Short name T170
Test name
Test status
Simulation time 158232659695 ps
CPU time 97.97 seconds
Started Aug 13 06:05:11 PM PDT 24
Finished Aug 13 06:06:49 PM PDT 24
Peak memory 202100 kb
Host smart-4f81a505-c0b1-4ead-bc62-c16275d0087f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021049448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3021049448
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.850004047
Short name T148
Test name
Test status
Simulation time 371725107617 ps
CPU time 448.19 seconds
Started Aug 13 06:05:13 PM PDT 24
Finished Aug 13 06:12:41 PM PDT 24
Peak memory 202160 kb
Host smart-763fcf2b-3d02-4f02-99c0-3a734d342c94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850004047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.850004047
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1486802214
Short name T110
Test name
Test status
Simulation time 201380501392 ps
CPU time 472.08 seconds
Started Aug 13 06:05:14 PM PDT 24
Finished Aug 13 06:13:06 PM PDT 24
Peak memory 202172 kb
Host smart-01977752-f0ae-4ffb-9e35-9d1e50406578
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486802214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1486802214
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.991893605
Short name T247
Test name
Test status
Simulation time 90220381098 ps
CPU time 329.13 seconds
Started Aug 13 06:05:22 PM PDT 24
Finished Aug 13 06:10:52 PM PDT 24
Peak memory 202436 kb
Host smart-37c666f7-eb42-4ac5-9345-32035ba89188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991893605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.991893605
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3483515373
Short name T190
Test name
Test status
Simulation time 34534302434 ps
CPU time 41.54 seconds
Started Aug 13 06:05:21 PM PDT 24
Finished Aug 13 06:06:03 PM PDT 24
Peak memory 201964 kb
Host smart-6ec8933e-20e4-41ce-bf71-f5551f6034fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483515373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3483515373
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.44314924
Short name T184
Test name
Test status
Simulation time 4498691350 ps
CPU time 11.36 seconds
Started Aug 13 06:05:23 PM PDT 24
Finished Aug 13 06:05:35 PM PDT 24
Peak memory 201956 kb
Host smart-550cf2ad-bc1c-4b8b-a8b3-f87fb1a73fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44314924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.44314924
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1288987755
Short name T506
Test name
Test status
Simulation time 6010097742 ps
CPU time 7.06 seconds
Started Aug 13 06:05:14 PM PDT 24
Finished Aug 13 06:05:21 PM PDT 24
Peak memory 201976 kb
Host smart-48a8d516-2833-48ca-bf89-d430321a06c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288987755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1288987755
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1877290969
Short name T168
Test name
Test status
Simulation time 511781110931 ps
CPU time 637.64 seconds
Started Aug 13 06:05:20 PM PDT 24
Finished Aug 13 06:15:58 PM PDT 24
Peak memory 202376 kb
Host smart-c7b05c44-c8df-4d39-9754-05830e05a8c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877290969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1877290969
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.100133936
Short name T351
Test name
Test status
Simulation time 14246794847 ps
CPU time 13.5 seconds
Started Aug 13 06:05:22 PM PDT 24
Finished Aug 13 06:05:36 PM PDT 24
Peak memory 210536 kb
Host smart-7a42ab1d-dae4-41c1-86e5-5683b0233c2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100133936 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.100133936
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3122272027
Short name T48
Test name
Test status
Simulation time 413138774 ps
CPU time 0.74 seconds
Started Aug 13 06:05:30 PM PDT 24
Finished Aug 13 06:05:31 PM PDT 24
Peak memory 201996 kb
Host smart-8bf2f6e0-eda2-43b0-be17-28a5a997cf41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122272027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3122272027
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.810338067
Short name T154
Test name
Test status
Simulation time 501851261947 ps
CPU time 350 seconds
Started Aug 13 06:05:22 PM PDT 24
Finished Aug 13 06:11:13 PM PDT 24
Peak memory 202176 kb
Host smart-af0e38de-cd49-4ba8-846b-24fcdacf8c24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810338067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.810338067
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2478290367
Short name T370
Test name
Test status
Simulation time 488126071703 ps
CPU time 315.85 seconds
Started Aug 13 06:05:23 PM PDT 24
Finished Aug 13 06:10:39 PM PDT 24
Peak memory 202040 kb
Host smart-8ad5977a-6a52-4a5f-b10f-c63507559ebe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478290367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2478290367
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.293163290
Short name T208
Test name
Test status
Simulation time 161102289492 ps
CPU time 173.07 seconds
Started Aug 13 06:05:21 PM PDT 24
Finished Aug 13 06:08:14 PM PDT 24
Peak memory 202048 kb
Host smart-4985ef65-8bb5-4316-8b5c-7add0dc0721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293163290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.293163290
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3048452402
Short name T365
Test name
Test status
Simulation time 161540913420 ps
CPU time 375.56 seconds
Started Aug 13 06:05:23 PM PDT 24
Finished Aug 13 06:11:38 PM PDT 24
Peak memory 202148 kb
Host smart-e055b42e-6a42-4e92-9eff-79f6f604e140
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048452402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3048452402
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1109427964
Short name T346
Test name
Test status
Simulation time 368507552193 ps
CPU time 398.7 seconds
Started Aug 13 06:05:22 PM PDT 24
Finished Aug 13 06:12:01 PM PDT 24
Peak memory 201996 kb
Host smart-c0de6500-1d80-4b20-a225-97a3f6ac1558
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109427964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1109427964
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3451317559
Short name T207
Test name
Test status
Simulation time 396851478384 ps
CPU time 423.59 seconds
Started Aug 13 06:05:23 PM PDT 24
Finished Aug 13 06:12:26 PM PDT 24
Peak memory 202148 kb
Host smart-1d49e9c2-f89a-4332-941c-6d3d910bb6c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451317559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3451317559
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2947076264
Short name T692
Test name
Test status
Simulation time 93587436028 ps
CPU time 431.07 seconds
Started Aug 13 06:05:29 PM PDT 24
Finished Aug 13 06:12:40 PM PDT 24
Peak memory 202412 kb
Host smart-46f32450-c4d0-4381-96cf-4e27a550dd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947076264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2947076264
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.427492916
Short name T118
Test name
Test status
Simulation time 47002221277 ps
CPU time 57.07 seconds
Started Aug 13 06:05:30 PM PDT 24
Finished Aug 13 06:06:27 PM PDT 24
Peak memory 201972 kb
Host smart-a1a72128-920a-49d3-a91d-7336dafd965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427492916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.427492916
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2635542145
Short name T459
Test name
Test status
Simulation time 3524603625 ps
CPU time 4.4 seconds
Started Aug 13 06:05:29 PM PDT 24
Finished Aug 13 06:05:34 PM PDT 24
Peak memory 201964 kb
Host smart-e10a0038-578a-4ca7-b636-fdff86a111f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635542145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2635542145
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3725678030
Short name T472
Test name
Test status
Simulation time 6064721245 ps
CPU time 15.79 seconds
Started Aug 13 06:05:21 PM PDT 24
Finished Aug 13 06:05:37 PM PDT 24
Peak memory 201964 kb
Host smart-e6f5ac41-ae34-4346-9e90-de542b659be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725678030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3725678030
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3016531515
Short name T474
Test name
Test status
Simulation time 364290979660 ps
CPU time 84.93 seconds
Started Aug 13 06:05:26 PM PDT 24
Finished Aug 13 06:06:51 PM PDT 24
Peak memory 202132 kb
Host smart-e93023e9-183b-4f23-acc8-ad6663632ec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016531515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3016531515
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3230120266
Short name T44
Test name
Test status
Simulation time 10080358961 ps
CPU time 6.89 seconds
Started Aug 13 06:05:30 PM PDT 24
Finished Aug 13 06:05:37 PM PDT 24
Peak memory 210480 kb
Host smart-564b6613-d24f-4a77-814c-6b254c6677c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230120266 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3230120266
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1957982362
Short name T646
Test name
Test status
Simulation time 365604607 ps
CPU time 1.43 seconds
Started Aug 13 06:05:48 PM PDT 24
Finished Aug 13 06:05:49 PM PDT 24
Peak memory 201864 kb
Host smart-61025b10-c077-43ca-967f-008bfdb23d18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957982362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1957982362
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2753705479
Short name T698
Test name
Test status
Simulation time 331764525461 ps
CPU time 808.06 seconds
Started Aug 13 06:05:30 PM PDT 24
Finished Aug 13 06:18:58 PM PDT 24
Peak memory 202048 kb
Host smart-13b29d8a-9e87-4f79-8935-3972f9654cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753705479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2753705479
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1406169548
Short name T636
Test name
Test status
Simulation time 485642515234 ps
CPU time 194.55 seconds
Started Aug 13 06:05:37 PM PDT 24
Finished Aug 13 06:08:52 PM PDT 24
Peak memory 200464 kb
Host smart-b45de821-73dd-4b69-abb2-5515433c3471
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406169548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1406169548
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4060969215
Short name T704
Test name
Test status
Simulation time 337275764451 ps
CPU time 821.85 seconds
Started Aug 13 06:05:30 PM PDT 24
Finished Aug 13 06:19:12 PM PDT 24
Peak memory 202044 kb
Host smart-00b73cc8-8637-4051-b0eb-31d2fe97f1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060969215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4060969215
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1996797549
Short name T455
Test name
Test status
Simulation time 331089567778 ps
CPU time 349.37 seconds
Started Aug 13 06:05:30 PM PDT 24
Finished Aug 13 06:11:19 PM PDT 24
Peak memory 202120 kb
Host smart-58e1355a-d5a6-4cd6-abbf-f06f1231182a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996797549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1996797549
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3008315353
Short name T775
Test name
Test status
Simulation time 612423949328 ps
CPU time 356.21 seconds
Started Aug 13 06:05:34 PM PDT 24
Finished Aug 13 06:11:31 PM PDT 24
Peak memory 202136 kb
Host smart-6523fc36-fdca-4b26-a2d5-2a56eeb22b47
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008315353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3008315353
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.631885301
Short name T755
Test name
Test status
Simulation time 207258834246 ps
CPU time 134.71 seconds
Started Aug 13 06:05:38 PM PDT 24
Finished Aug 13 06:07:53 PM PDT 24
Peak memory 202124 kb
Host smart-faa99799-69ae-4bd1-b4a5-3bf7b2d77fac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631885301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.631885301
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4025975284
Short name T440
Test name
Test status
Simulation time 122115540968 ps
CPU time 608.13 seconds
Started Aug 13 06:05:38 PM PDT 24
Finished Aug 13 06:15:46 PM PDT 24
Peak memory 202388 kb
Host smart-7809abde-bf30-467d-a8e0-f9232bd830df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025975284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4025975284
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.4150418614
Short name T171
Test name
Test status
Simulation time 44959575473 ps
CPU time 98.13 seconds
Started Aug 13 06:05:38 PM PDT 24
Finished Aug 13 06:07:16 PM PDT 24
Peak memory 201996 kb
Host smart-68b41175-9efd-4d6e-a9bd-94e05bb11b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150418614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.4150418614
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2217196462
Short name T203
Test name
Test status
Simulation time 4006484182 ps
CPU time 2.89 seconds
Started Aug 13 06:05:38 PM PDT 24
Finished Aug 13 06:05:41 PM PDT 24
Peak memory 201992 kb
Host smart-3d7d03da-e56a-44c5-a32c-7f2233a285d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217196462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2217196462
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1210132885
Short name T489
Test name
Test status
Simulation time 5993751662 ps
CPU time 14.36 seconds
Started Aug 13 06:05:29 PM PDT 24
Finished Aug 13 06:05:43 PM PDT 24
Peak memory 201908 kb
Host smart-b8bf5ef0-7f59-46fd-a9e7-d93056d714b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210132885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1210132885
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4119885137
Short name T656
Test name
Test status
Simulation time 1469930909 ps
CPU time 6.37 seconds
Started Aug 13 06:05:39 PM PDT 24
Finished Aug 13 06:05:45 PM PDT 24
Peak memory 201980 kb
Host smart-0ff3a041-ad52-4a15-9d2e-dccba6c25723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119885137 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4119885137
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.245103679
Short name T502
Test name
Test status
Simulation time 511017658 ps
CPU time 1.67 seconds
Started Aug 13 06:06:04 PM PDT 24
Finished Aug 13 06:06:06 PM PDT 24
Peak memory 201964 kb
Host smart-649543a9-bf80-4599-94d1-3e882faa05cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245103679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.245103679
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2727788769
Short name T222
Test name
Test status
Simulation time 162901202474 ps
CPU time 98.12 seconds
Started Aug 13 06:05:44 PM PDT 24
Finished Aug 13 06:07:22 PM PDT 24
Peak memory 202128 kb
Host smart-6979c52f-d404-4b7e-9518-b27f82c78d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727788769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2727788769
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1485348434
Short name T521
Test name
Test status
Simulation time 490376321452 ps
CPU time 1038.98 seconds
Started Aug 13 06:05:47 PM PDT 24
Finished Aug 13 06:23:06 PM PDT 24
Peak memory 202148 kb
Host smart-62557e31-acda-47f6-a6b1-4af40b5a7936
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485348434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1485348434
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.750339286
Short name T598
Test name
Test status
Simulation time 166108988914 ps
CPU time 325.28 seconds
Started Aug 13 06:05:44 PM PDT 24
Finished Aug 13 06:11:10 PM PDT 24
Peak memory 202140 kb
Host smart-e78e843b-37a8-40fb-8676-961a095852db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750339286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.750339286
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2807308582
Short name T404
Test name
Test status
Simulation time 326154875338 ps
CPU time 685.62 seconds
Started Aug 13 06:05:47 PM PDT 24
Finished Aug 13 06:17:13 PM PDT 24
Peak memory 202120 kb
Host smart-3fe1d9a8-4177-45c0-967e-8e3d5788605d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807308582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2807308582
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2349547419
Short name T264
Test name
Test status
Simulation time 513056338495 ps
CPU time 606.19 seconds
Started Aug 13 06:05:58 PM PDT 24
Finished Aug 13 06:16:04 PM PDT 24
Peak memory 202096 kb
Host smart-5a5715b2-720e-4d50-bde2-aed7eb965a65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349547419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2349547419
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.667471283
Short name T406
Test name
Test status
Simulation time 403944241492 ps
CPU time 237.28 seconds
Started Aug 13 06:05:56 PM PDT 24
Finished Aug 13 06:09:54 PM PDT 24
Peak memory 202152 kb
Host smart-a31ed047-b785-4eca-a1fd-b5a560a95f9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667471283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.667471283
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1084953530
Short name T244
Test name
Test status
Simulation time 120243430626 ps
CPU time 507.62 seconds
Started Aug 13 06:05:56 PM PDT 24
Finished Aug 13 06:14:24 PM PDT 24
Peak memory 202392 kb
Host smart-f6654394-63be-4add-afa4-7f28a0debdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084953530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1084953530
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1411585772
Short name T741
Test name
Test status
Simulation time 23580185505 ps
CPU time 29.27 seconds
Started Aug 13 06:05:56 PM PDT 24
Finished Aug 13 06:06:25 PM PDT 24
Peak memory 201912 kb
Host smart-e589614a-b514-4b47-984a-7d3f203afc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411585772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1411585772
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.147910109
Short name T625
Test name
Test status
Simulation time 3469220667 ps
CPU time 9.17 seconds
Started Aug 13 06:05:56 PM PDT 24
Finished Aug 13 06:06:05 PM PDT 24
Peak memory 201964 kb
Host smart-b4eaeba6-f0b9-4324-95aa-5d7506592140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147910109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.147910109
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3435846208
Short name T587
Test name
Test status
Simulation time 5933710048 ps
CPU time 14.03 seconds
Started Aug 13 06:05:47 PM PDT 24
Finished Aug 13 06:06:01 PM PDT 24
Peak memory 201940 kb
Host smart-aac5b465-31e6-494f-8c47-db6b3d357ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435846208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3435846208
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.421682325
Short name T21
Test name
Test status
Simulation time 66898217731 ps
CPU time 10.92 seconds
Started Aug 13 06:05:56 PM PDT 24
Finished Aug 13 06:06:07 PM PDT 24
Peak memory 202248 kb
Host smart-981aba9e-d7cb-4f0e-8f6b-8dcfc0a91673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421682325 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.421682325
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2361253609
Short name T771
Test name
Test status
Simulation time 500856747 ps
CPU time 0.91 seconds
Started Aug 13 06:06:05 PM PDT 24
Finished Aug 13 06:06:06 PM PDT 24
Peak memory 201896 kb
Host smart-d612dce0-89bb-478b-8fdc-63824c7b97ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361253609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2361253609
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1349148094
Short name T291
Test name
Test status
Simulation time 524338037365 ps
CPU time 605.83 seconds
Started Aug 13 06:06:06 PM PDT 24
Finished Aug 13 06:16:12 PM PDT 24
Peak memory 202156 kb
Host smart-fea47320-b125-4b85-aa52-b7a584d3c31a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349148094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1349148094
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1123663787
Short name T163
Test name
Test status
Simulation time 327418079160 ps
CPU time 725.32 seconds
Started Aug 13 06:06:05 PM PDT 24
Finished Aug 13 06:18:10 PM PDT 24
Peak memory 202156 kb
Host smart-a2d734bf-970b-4d97-b3c5-61e3ce623b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123663787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1123663787
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.724082734
Short name T516
Test name
Test status
Simulation time 163215718394 ps
CPU time 390.96 seconds
Started Aug 13 06:06:07 PM PDT 24
Finished Aug 13 06:12:38 PM PDT 24
Peak memory 202140 kb
Host smart-17ec3e24-0484-49a8-8762-475c0effa617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724082734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.724082734
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2865949385
Short name T13
Test name
Test status
Simulation time 330098715158 ps
CPU time 184.18 seconds
Started Aug 13 06:06:04 PM PDT 24
Finished Aug 13 06:09:08 PM PDT 24
Peak memory 202060 kb
Host smart-e05ec326-75a2-47e7-a6a1-24c7dfa2ba23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865949385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2865949385
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.946678984
Short name T150
Test name
Test status
Simulation time 482307672933 ps
CPU time 235.37 seconds
Started Aug 13 06:06:06 PM PDT 24
Finished Aug 13 06:10:02 PM PDT 24
Peak memory 202064 kb
Host smart-8364ef07-75b8-42d4-b40b-5a5947e002d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946678984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.946678984
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1943546980
Short name T670
Test name
Test status
Simulation time 491716779677 ps
CPU time 544.75 seconds
Started Aug 13 06:06:07 PM PDT 24
Finished Aug 13 06:15:12 PM PDT 24
Peak memory 202112 kb
Host smart-fc36c926-9f8c-44e4-9b34-dd01297dd50f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943546980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1943546980
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.4003587178
Short name T316
Test name
Test status
Simulation time 538015341797 ps
CPU time 1135.98 seconds
Started Aug 13 06:06:07 PM PDT 24
Finished Aug 13 06:25:03 PM PDT 24
Peak memory 202132 kb
Host smart-37d9ab8d-f79e-488e-85a7-b42da3fd29df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003587178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.4003587178
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.859682815
Short name T760
Test name
Test status
Simulation time 622797579764 ps
CPU time 363.61 seconds
Started Aug 13 06:06:06 PM PDT 24
Finished Aug 13 06:12:10 PM PDT 24
Peak memory 202080 kb
Host smart-bb7685d4-1ab3-4a98-8328-4fdf6384f130
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859682815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.859682815
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.827781158
Short name T230
Test name
Test status
Simulation time 130856247243 ps
CPU time 661.35 seconds
Started Aug 13 06:06:05 PM PDT 24
Finished Aug 13 06:17:07 PM PDT 24
Peak memory 202400 kb
Host smart-6e38f538-32b4-4233-a2c2-dfc59088d932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827781158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.827781158
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.883010584
Short name T466
Test name
Test status
Simulation time 24333758385 ps
CPU time 14.82 seconds
Started Aug 13 06:06:08 PM PDT 24
Finished Aug 13 06:06:22 PM PDT 24
Peak memory 201968 kb
Host smart-6c826444-d094-4860-9712-5a7eb98734b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883010584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.883010584
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3291132694
Short name T491
Test name
Test status
Simulation time 4961267639 ps
CPU time 3.87 seconds
Started Aug 13 06:06:05 PM PDT 24
Finished Aug 13 06:06:09 PM PDT 24
Peak memory 201828 kb
Host smart-f3a8942b-31c6-4273-a7b2-73e552fecd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291132694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3291132694
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3468453366
Short name T633
Test name
Test status
Simulation time 6130768082 ps
CPU time 4.58 seconds
Started Aug 13 06:06:06 PM PDT 24
Finished Aug 13 06:06:11 PM PDT 24
Peak memory 201880 kb
Host smart-2ccc5aa8-3c59-474a-8035-b30e8537043b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468453366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3468453366
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2857110042
Short name T228
Test name
Test status
Simulation time 362369947828 ps
CPU time 570.37 seconds
Started Aug 13 06:06:06 PM PDT 24
Finished Aug 13 06:15:37 PM PDT 24
Peak memory 210600 kb
Host smart-3b63d9a4-03ef-4f5c-88cd-b6c9aa7eb26c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857110042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2857110042
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2902060808
Short name T680
Test name
Test status
Simulation time 6073725360 ps
CPU time 3.08 seconds
Started Aug 13 06:06:03 PM PDT 24
Finished Aug 13 06:06:06 PM PDT 24
Peak memory 202032 kb
Host smart-1f3e9539-9776-4ce8-83e5-7250ee39945d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902060808 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2902060808
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2244559741
Short name T400
Test name
Test status
Simulation time 529428861 ps
CPU time 1.16 seconds
Started Aug 13 06:06:22 PM PDT 24
Finished Aug 13 06:06:23 PM PDT 24
Peak memory 201940 kb
Host smart-1110d6a8-3eb0-4350-9f94-fcf958dd8b99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244559741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2244559741
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.4166809186
Short name T220
Test name
Test status
Simulation time 336660274245 ps
CPU time 200.09 seconds
Started Aug 13 06:06:14 PM PDT 24
Finished Aug 13 06:09:34 PM PDT 24
Peak memory 202024 kb
Host smart-66b54562-81ad-4141-b8c5-8264e330db0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166809186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.4166809186
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4247550665
Short name T688
Test name
Test status
Simulation time 495035866022 ps
CPU time 322.63 seconds
Started Aug 13 06:06:14 PM PDT 24
Finished Aug 13 06:11:37 PM PDT 24
Peak memory 202140 kb
Host smart-c9ea9be4-381b-4e2b-99bd-2345e9b81244
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247550665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.4247550665
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2951567442
Short name T488
Test name
Test status
Simulation time 326685479248 ps
CPU time 180.36 seconds
Started Aug 13 06:06:14 PM PDT 24
Finished Aug 13 06:09:15 PM PDT 24
Peak memory 202136 kb
Host smart-08521bae-7d3e-4ea6-b28c-39c7ef87b72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951567442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2951567442
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3706756037
Short name T658
Test name
Test status
Simulation time 486487329674 ps
CPU time 306.41 seconds
Started Aug 13 06:06:14 PM PDT 24
Finished Aug 13 06:11:20 PM PDT 24
Peak memory 202128 kb
Host smart-9486e01d-b4c5-416e-95ed-887262de2097
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706756037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3706756037
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2938459068
Short name T160
Test name
Test status
Simulation time 398901434670 ps
CPU time 852.14 seconds
Started Aug 13 06:06:16 PM PDT 24
Finished Aug 13 06:20:28 PM PDT 24
Peak memory 202124 kb
Host smart-54064155-71ef-4150-a5ec-9cdd57c5dd6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938459068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2938459068
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.158268451
Short name T513
Test name
Test status
Simulation time 394532850079 ps
CPU time 241.57 seconds
Started Aug 13 06:06:15 PM PDT 24
Finished Aug 13 06:10:16 PM PDT 24
Peak memory 202096 kb
Host smart-38eb3ff3-686d-444b-b0cc-38889a7f9c2c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158268451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.158268451
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1280835558
Short name T602
Test name
Test status
Simulation time 99441140373 ps
CPU time 352.4 seconds
Started Aug 13 06:06:15 PM PDT 24
Finished Aug 13 06:12:08 PM PDT 24
Peak memory 202332 kb
Host smart-c0b4f585-e54f-4510-af72-8961f48579d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280835558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1280835558
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2126855366
Short name T484
Test name
Test status
Simulation time 30806387978 ps
CPU time 10.01 seconds
Started Aug 13 06:06:14 PM PDT 24
Finished Aug 13 06:06:24 PM PDT 24
Peak memory 201972 kb
Host smart-28457591-b33f-491e-bd61-824fcf859544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126855366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2126855366
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4220422532
Short name T453
Test name
Test status
Simulation time 4752911450 ps
CPU time 9.2 seconds
Started Aug 13 06:06:14 PM PDT 24
Finished Aug 13 06:06:23 PM PDT 24
Peak memory 201860 kb
Host smart-73e6476f-eaf9-4cd8-9369-97a382bbefb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220422532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4220422532
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3903092182
Short name T460
Test name
Test status
Simulation time 5932950430 ps
CPU time 13.3 seconds
Started Aug 13 06:06:07 PM PDT 24
Finished Aug 13 06:06:21 PM PDT 24
Peak memory 201868 kb
Host smart-df576191-5feb-4d57-bacb-1a46239e2f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903092182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3903092182
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1213513336
Short name T749
Test name
Test status
Simulation time 436229363715 ps
CPU time 1070.42 seconds
Started Aug 13 06:06:23 PM PDT 24
Finished Aug 13 06:24:14 PM PDT 24
Peak memory 202136 kb
Host smart-6364c9fb-6d2b-44be-8315-c3b2280d4713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213513336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1213513336
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2917446708
Short name T428
Test name
Test status
Simulation time 1395582073 ps
CPU time 3.96 seconds
Started Aug 13 06:06:22 PM PDT 24
Finished Aug 13 06:06:26 PM PDT 24
Peak memory 202060 kb
Host smart-16550042-1e74-4fc1-9a81-f73bb9e78d34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917446708 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2917446708
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3602392237
Short name T509
Test name
Test status
Simulation time 445803626 ps
CPU time 0.67 seconds
Started Aug 13 06:06:39 PM PDT 24
Finished Aug 13 06:06:39 PM PDT 24
Peak memory 202008 kb
Host smart-c4133a76-c141-4d41-90ad-df7ac68090d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602392237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3602392237
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2705108323
Short name T161
Test name
Test status
Simulation time 599060733096 ps
CPU time 665.31 seconds
Started Aug 13 06:06:30 PM PDT 24
Finished Aug 13 06:17:35 PM PDT 24
Peak memory 202148 kb
Host smart-a70986c7-0464-493b-b990-01b7cfed3366
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705108323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2705108323
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2316943878
Short name T16
Test name
Test status
Simulation time 317975399236 ps
CPU time 774.68 seconds
Started Aug 13 06:06:23 PM PDT 24
Finished Aug 13 06:19:17 PM PDT 24
Peak memory 202212 kb
Host smart-041f598c-bb84-470e-b173-3bc4c335828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316943878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2316943878
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3934161483
Short name T410
Test name
Test status
Simulation time 328752194551 ps
CPU time 728.48 seconds
Started Aug 13 06:06:23 PM PDT 24
Finished Aug 13 06:18:31 PM PDT 24
Peak memory 202156 kb
Host smart-333e9e0e-9abb-4b1a-9225-4350bd7b201e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934161483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3934161483
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.177611069
Short name T678
Test name
Test status
Simulation time 500720360042 ps
CPU time 295.49 seconds
Started Aug 13 06:06:23 PM PDT 24
Finished Aug 13 06:11:18 PM PDT 24
Peak memory 202196 kb
Host smart-380a2cc7-5cce-4cc1-8ce8-74500b3de356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177611069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.177611069
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.518325646
Short name T121
Test name
Test status
Simulation time 332467120388 ps
CPU time 176.5 seconds
Started Aug 13 06:06:22 PM PDT 24
Finished Aug 13 06:09:19 PM PDT 24
Peak memory 202120 kb
Host smart-93f56ccb-7eb1-4933-9522-ec16ed5abaf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=518325646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.518325646
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1603940754
Short name T349
Test name
Test status
Simulation time 168430810662 ps
CPU time 126.04 seconds
Started Aug 13 06:06:29 PM PDT 24
Finished Aug 13 06:08:35 PM PDT 24
Peak memory 202136 kb
Host smart-71f24e94-9518-4e2e-9e39-5c0f41dcbd88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603940754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1603940754
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.881414419
Short name T717
Test name
Test status
Simulation time 406984629855 ps
CPU time 236.48 seconds
Started Aug 13 06:06:31 PM PDT 24
Finished Aug 13 06:10:27 PM PDT 24
Peak memory 202096 kb
Host smart-61df0943-a31a-4e78-9b53-b9ef823bdde5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881414419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.881414419
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2215591165
Short name T617
Test name
Test status
Simulation time 134612206110 ps
CPU time 693.22 seconds
Started Aug 13 06:06:39 PM PDT 24
Finished Aug 13 06:18:12 PM PDT 24
Peak memory 202440 kb
Host smart-ee8babf3-9c72-4916-bf7f-ea2b91ed809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215591165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2215591165
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.605433841
Short name T151
Test name
Test status
Simulation time 46871309467 ps
CPU time 100.7 seconds
Started Aug 13 06:06:39 PM PDT 24
Finished Aug 13 06:08:20 PM PDT 24
Peak memory 201948 kb
Host smart-f01294b9-0cf9-485f-b112-f38640dd4315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605433841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.605433841
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3853842603
Short name T381
Test name
Test status
Simulation time 4753122422 ps
CPU time 2.58 seconds
Started Aug 13 06:06:37 PM PDT 24
Finished Aug 13 06:06:40 PM PDT 24
Peak memory 201968 kb
Host smart-6a17c3d3-1131-49b7-8abf-b1d6d869b4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853842603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3853842603
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1956341865
Short name T213
Test name
Test status
Simulation time 5889497103 ps
CPU time 4.92 seconds
Started Aug 13 06:06:21 PM PDT 24
Finished Aug 13 06:06:26 PM PDT 24
Peak memory 201964 kb
Host smart-dbea118e-d33b-4961-8a6f-0682527637d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956341865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1956341865
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2206266674
Short name T341
Test name
Test status
Simulation time 674561393262 ps
CPU time 436.44 seconds
Started Aug 13 06:06:38 PM PDT 24
Finished Aug 13 06:13:55 PM PDT 24
Peak memory 202112 kb
Host smart-9bdd8fb6-59f6-4bda-af48-6404f50aaebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206266674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2206266674
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3285066100
Short name T526
Test name
Test status
Simulation time 3503062345 ps
CPU time 8.48 seconds
Started Aug 13 06:06:36 PM PDT 24
Finished Aug 13 06:06:45 PM PDT 24
Peak memory 202352 kb
Host smart-8c7ac16a-68fc-4c39-833c-68d70b6b7ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285066100 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3285066100
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3169312847
Short name T174
Test name
Test status
Simulation time 404087124 ps
CPU time 1.12 seconds
Started Aug 13 06:06:53 PM PDT 24
Finished Aug 13 06:06:55 PM PDT 24
Peak memory 201852 kb
Host smart-e1badec4-6000-45cc-927d-a4c31320747c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169312847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3169312847
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1001912418
Short name T96
Test name
Test status
Simulation time 496165075791 ps
CPU time 279.12 seconds
Started Aug 13 06:06:45 PM PDT 24
Finished Aug 13 06:11:24 PM PDT 24
Peak memory 202064 kb
Host smart-b1ed73a6-9b0f-4ec3-ae1b-e570f0dfaeec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001912418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1001912418
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1050865204
Short name T289
Test name
Test status
Simulation time 161150513052 ps
CPU time 197.27 seconds
Started Aug 13 06:06:46 PM PDT 24
Finished Aug 13 06:10:03 PM PDT 24
Peak memory 202112 kb
Host smart-2cd0989d-52ad-4fd1-aa7b-21296ea0265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050865204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1050865204
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.588448461
Short name T323
Test name
Test status
Simulation time 165786960062 ps
CPU time 198.01 seconds
Started Aug 13 06:06:45 PM PDT 24
Finished Aug 13 06:10:04 PM PDT 24
Peak memory 202112 kb
Host smart-bab217f6-74cb-4263-9277-90e2c4383335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588448461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.588448461
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1242835151
Short name T639
Test name
Test status
Simulation time 504312581351 ps
CPU time 102.68 seconds
Started Aug 13 06:06:44 PM PDT 24
Finished Aug 13 06:08:27 PM PDT 24
Peak memory 202116 kb
Host smart-3bbf7a81-099b-40ed-bff7-40482d1a4df3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242835151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1242835151
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.270858474
Short name T736
Test name
Test status
Simulation time 330253093596 ps
CPU time 709.87 seconds
Started Aug 13 06:06:36 PM PDT 24
Finished Aug 13 06:18:26 PM PDT 24
Peak memory 202148 kb
Host smart-979622e0-fc78-4b89-9601-39029103a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270858474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.270858474
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1905081296
Short name T643
Test name
Test status
Simulation time 162560715666 ps
CPU time 97.36 seconds
Started Aug 13 06:06:45 PM PDT 24
Finished Aug 13 06:08:23 PM PDT 24
Peak memory 202076 kb
Host smart-bf5d325c-33e7-4d5d-8fbf-567ef4043aa9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905081296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1905081296
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.248707008
Short name T407
Test name
Test status
Simulation time 202458509817 ps
CPU time 108.2 seconds
Started Aug 13 06:06:45 PM PDT 24
Finished Aug 13 06:08:34 PM PDT 24
Peak memory 202060 kb
Host smart-b98f1e22-dc1a-489f-a0d6-aa2ca73d737d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248707008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.248707008
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2270772057
Short name T35
Test name
Test status
Simulation time 404357597105 ps
CPU time 948.21 seconds
Started Aug 13 06:06:47 PM PDT 24
Finished Aug 13 06:22:35 PM PDT 24
Peak memory 202128 kb
Host smart-264c17cc-f6da-4afb-803a-f9ddf124599c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270772057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2270772057
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3922887889
Short name T252
Test name
Test status
Simulation time 88310852833 ps
CPU time 474.84 seconds
Started Aug 13 06:06:47 PM PDT 24
Finished Aug 13 06:14:42 PM PDT 24
Peak memory 202396 kb
Host smart-dde525f0-0232-45f8-ab1c-3b15412ed6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922887889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3922887889
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2896122813
Short name T483
Test name
Test status
Simulation time 26155904115 ps
CPU time 64.57 seconds
Started Aug 13 06:06:44 PM PDT 24
Finished Aug 13 06:07:49 PM PDT 24
Peak memory 201916 kb
Host smart-a8cf68b2-853e-414d-b9aa-cc94e5a68ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896122813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2896122813
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1280190730
Short name T446
Test name
Test status
Simulation time 4288823067 ps
CPU time 6.67 seconds
Started Aug 13 06:06:45 PM PDT 24
Finished Aug 13 06:06:52 PM PDT 24
Peak memory 201932 kb
Host smart-648fc3df-d048-449c-bfac-9bc240d0f704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280190730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1280190730
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3242363251
Short name T660
Test name
Test status
Simulation time 5880079363 ps
CPU time 4.25 seconds
Started Aug 13 06:06:36 PM PDT 24
Finished Aug 13 06:06:40 PM PDT 24
Peak memory 201956 kb
Host smart-18da7792-a649-431c-b3e6-fae881ad3306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242363251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3242363251
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3783275717
Short name T66
Test name
Test status
Simulation time 250159926091 ps
CPU time 465.77 seconds
Started Aug 13 06:06:44 PM PDT 24
Finished Aug 13 06:14:30 PM PDT 24
Peak memory 210620 kb
Host smart-c031e992-3bac-484a-a4f0-8fc9bb96635c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783275717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3783275717
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1718388164
Short name T45
Test name
Test status
Simulation time 2424628921 ps
CPU time 3.78 seconds
Started Aug 13 06:06:47 PM PDT 24
Finished Aug 13 06:06:51 PM PDT 24
Peak memory 202124 kb
Host smart-5fde806f-2a05-442f-83e4-aa7d392ff1fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718388164 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1718388164
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2540844625
Short name T82
Test name
Test status
Simulation time 471195334 ps
CPU time 0.9 seconds
Started Aug 13 06:01:04 PM PDT 24
Finished Aug 13 06:01:05 PM PDT 24
Peak memory 201996 kb
Host smart-3ece0267-5ef4-4943-8269-c7fcde5c89ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540844625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2540844625
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.497523440
Short name T29
Test name
Test status
Simulation time 165429862589 ps
CPU time 180.64 seconds
Started Aug 13 06:01:02 PM PDT 24
Finished Aug 13 06:04:03 PM PDT 24
Peak memory 202124 kb
Host smart-0b05e8b7-a501-4b31-aa5c-d7d822261e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497523440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.497523440
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1886300134
Short name T295
Test name
Test status
Simulation time 165832840182 ps
CPU time 106.22 seconds
Started Aug 13 06:01:07 PM PDT 24
Finished Aug 13 06:02:53 PM PDT 24
Peak memory 202192 kb
Host smart-a79ae300-6ce9-4762-a531-759781f60d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886300134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1886300134
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3109615321
Short name T452
Test name
Test status
Simulation time 493262146477 ps
CPU time 293.27 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:05:58 PM PDT 24
Peak memory 202204 kb
Host smart-618f1b7f-208b-4c3f-862d-3f8881154761
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109615321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3109615321
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2844335244
Short name T751
Test name
Test status
Simulation time 493138237245 ps
CPU time 1006.83 seconds
Started Aug 13 06:01:06 PM PDT 24
Finished Aug 13 06:17:53 PM PDT 24
Peak memory 202156 kb
Host smart-5ba39575-3305-43c6-a979-9d45272cff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844335244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2844335244
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2101806574
Short name T661
Test name
Test status
Simulation time 163682182792 ps
CPU time 390.67 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:07:36 PM PDT 24
Peak memory 202120 kb
Host smart-85deb57d-3e8c-4944-865e-0b2327adbfce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101806574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2101806574
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3037359988
Short name T778
Test name
Test status
Simulation time 414461051197 ps
CPU time 931.31 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:16:36 PM PDT 24
Peak memory 202136 kb
Host smart-f84b2a47-ec11-410a-81b9-8e7f2f7d75dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037359988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3037359988
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.299290588
Short name T612
Test name
Test status
Simulation time 93188644799 ps
CPU time 485.86 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:09:11 PM PDT 24
Peak memory 202504 kb
Host smart-fecfefa1-93bd-4037-aa83-030b76673585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299290588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.299290588
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.44135774
Short name T485
Test name
Test status
Simulation time 31092105177 ps
CPU time 10.28 seconds
Started Aug 13 06:01:06 PM PDT 24
Finished Aug 13 06:01:16 PM PDT 24
Peak memory 202096 kb
Host smart-b3d0a492-774c-4fa8-809d-7eb14452eb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44135774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.44135774
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3610692367
Short name T416
Test name
Test status
Simulation time 4321051773 ps
CPU time 3.18 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:01:08 PM PDT 24
Peak memory 201948 kb
Host smart-3230c016-0ee0-41a3-bf1c-86d95e90e479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610692367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3610692367
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3338017036
Short name T79
Test name
Test status
Simulation time 7235265703 ps
CPU time 17.26 seconds
Started Aug 13 06:01:02 PM PDT 24
Finished Aug 13 06:01:20 PM PDT 24
Peak memory 218516 kb
Host smart-6b80925d-2b5c-45be-9780-aadfb6016a75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338017036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3338017036
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3824968328
Short name T393
Test name
Test status
Simulation time 5990044660 ps
CPU time 8.41 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:01:14 PM PDT 24
Peak memory 201928 kb
Host smart-ee99d54c-1931-44e1-924f-85cf544881c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824968328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3824968328
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3413497917
Short name T782
Test name
Test status
Simulation time 1387099601995 ps
CPU time 2274.39 seconds
Started Aug 13 06:01:04 PM PDT 24
Finished Aug 13 06:38:59 PM PDT 24
Peak memory 210652 kb
Host smart-1a61609e-7ade-48e5-99c4-5bcac96d5bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413497917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3413497917
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3145312729
Short name T708
Test name
Test status
Simulation time 3702827016 ps
CPU time 12.11 seconds
Started Aug 13 06:01:06 PM PDT 24
Finished Aug 13 06:01:18 PM PDT 24
Peak memory 210536 kb
Host smart-81c06bd5-3ff3-4286-8d93-1167fd9c7e1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145312729 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3145312729
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3282335715
Short name T538
Test name
Test status
Simulation time 442625462 ps
CPU time 0.87 seconds
Started Aug 13 06:07:02 PM PDT 24
Finished Aug 13 06:07:03 PM PDT 24
Peak memory 201984 kb
Host smart-9cbc2a4c-44d5-4d83-9ac9-a4d18a0379a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282335715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3282335715
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2074636267
Short name T787
Test name
Test status
Simulation time 179614683306 ps
CPU time 371.38 seconds
Started Aug 13 06:07:04 PM PDT 24
Finished Aug 13 06:13:15 PM PDT 24
Peak memory 202136 kb
Host smart-aa7547a8-e77a-4413-a832-96d164e85d18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074636267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2074636267
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2859497986
Short name T49
Test name
Test status
Simulation time 204568374888 ps
CPU time 39.25 seconds
Started Aug 13 06:06:59 PM PDT 24
Finished Aug 13 06:07:38 PM PDT 24
Peak memory 202132 kb
Host smart-ba999cba-e0e9-48a2-aa34-0fe5a0e24a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859497986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2859497986
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.531120979
Short name T321
Test name
Test status
Simulation time 496779179721 ps
CPU time 309.33 seconds
Started Aug 13 06:06:51 PM PDT 24
Finished Aug 13 06:12:01 PM PDT 24
Peak memory 202140 kb
Host smart-acd2ef46-0c8f-47c6-aa89-e657127fd95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531120979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.531120979
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3747199324
Short name T592
Test name
Test status
Simulation time 166251913341 ps
CPU time 64.28 seconds
Started Aug 13 06:06:54 PM PDT 24
Finished Aug 13 06:07:59 PM PDT 24
Peak memory 202064 kb
Host smart-7529e9da-3961-43f1-b909-c99c28d8cf95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747199324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3747199324
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.981214768
Short name T486
Test name
Test status
Simulation time 325648616778 ps
CPU time 637.27 seconds
Started Aug 13 06:06:50 PM PDT 24
Finished Aug 13 06:17:28 PM PDT 24
Peak memory 202196 kb
Host smart-78bb66d1-31bc-4e97-a6c0-c6647a7a381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981214768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.981214768
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.97758286
Short name T447
Test name
Test status
Simulation time 158995263148 ps
CPU time 21.86 seconds
Started Aug 13 06:06:53 PM PDT 24
Finished Aug 13 06:07:15 PM PDT 24
Peak memory 202012 kb
Host smart-ef6e09e9-6b6f-40c5-8f84-1ff53d4064b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=97758286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed
.97758286
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.594676620
Short name T179
Test name
Test status
Simulation time 513998778333 ps
CPU time 280.75 seconds
Started Aug 13 06:07:01 PM PDT 24
Finished Aug 13 06:11:42 PM PDT 24
Peak memory 202136 kb
Host smart-ff4fdf17-01a0-4d8a-b12a-7c50d168fa41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594676620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.594676620
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.808082579
Short name T644
Test name
Test status
Simulation time 601089710385 ps
CPU time 1344.97 seconds
Started Aug 13 06:07:01 PM PDT 24
Finished Aug 13 06:29:27 PM PDT 24
Peak memory 202096 kb
Host smart-f2eabda3-d335-472a-96c5-b4364e67f810
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808082579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.808082579
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2110784652
Short name T242
Test name
Test status
Simulation time 104776103291 ps
CPU time 331.55 seconds
Started Aug 13 06:07:02 PM PDT 24
Finished Aug 13 06:12:34 PM PDT 24
Peak memory 202308 kb
Host smart-915a5ea6-376e-4cef-add4-3be5f0bd5ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110784652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2110784652
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2149803097
Short name T458
Test name
Test status
Simulation time 21425227757 ps
CPU time 12.21 seconds
Started Aug 13 06:07:02 PM PDT 24
Finished Aug 13 06:07:14 PM PDT 24
Peak memory 201972 kb
Host smart-7743dcce-690f-4eac-8484-15772f74a420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149803097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2149803097
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1799070589
Short name T540
Test name
Test status
Simulation time 5468022202 ps
CPU time 12.27 seconds
Started Aug 13 06:06:58 PM PDT 24
Finished Aug 13 06:07:11 PM PDT 24
Peak memory 201856 kb
Host smart-c1f4bc30-7ce3-43aa-a539-10cca4bc7c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799070589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1799070589
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2067150524
Short name T375
Test name
Test status
Simulation time 5805064816 ps
CPU time 13.67 seconds
Started Aug 13 06:06:52 PM PDT 24
Finished Aug 13 06:07:06 PM PDT 24
Peak memory 201980 kb
Host smart-83d94b70-5b13-4356-8d95-5122055e8ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067150524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2067150524
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1098597555
Short name T385
Test name
Test status
Simulation time 8674409993 ps
CPU time 21.8 seconds
Started Aug 13 06:07:01 PM PDT 24
Finished Aug 13 06:07:23 PM PDT 24
Peak memory 201868 kb
Host smart-6962b71a-a6dd-49f1-bc94-b9aaf5c1522f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098597555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1098597555
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3703807555
Short name T586
Test name
Test status
Simulation time 9526495084 ps
CPU time 35.14 seconds
Started Aug 13 06:07:01 PM PDT 24
Finished Aug 13 06:07:36 PM PDT 24
Peak memory 210768 kb
Host smart-e153777c-9d48-426a-a46f-ef53c5967719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703807555 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3703807555
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1622107009
Short name T785
Test name
Test status
Simulation time 437586322 ps
CPU time 1.05 seconds
Started Aug 13 06:07:10 PM PDT 24
Finished Aug 13 06:07:11 PM PDT 24
Peak memory 201868 kb
Host smart-12a86e3a-2ce8-4cbc-80f6-2f8c8b801144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622107009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1622107009
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1514380453
Short name T357
Test name
Test status
Simulation time 481877555134 ps
CPU time 298.41 seconds
Started Aug 13 06:07:01 PM PDT 24
Finished Aug 13 06:12:00 PM PDT 24
Peak memory 202148 kb
Host smart-bdcdd9c0-4704-4461-b5f6-bce0fd738a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514380453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1514380453
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3591103886
Short name T368
Test name
Test status
Simulation time 158789429593 ps
CPU time 105.02 seconds
Started Aug 13 06:07:10 PM PDT 24
Finished Aug 13 06:08:55 PM PDT 24
Peak memory 202188 kb
Host smart-2f022949-e3ce-4dbe-b2fb-df12a0a3de73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591103886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3591103886
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3290702239
Short name T471
Test name
Test status
Simulation time 159999351557 ps
CPU time 163 seconds
Started Aug 13 06:07:02 PM PDT 24
Finished Aug 13 06:09:46 PM PDT 24
Peak memory 202140 kb
Host smart-0483304b-14de-4b42-8168-98d9777792a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290702239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3290702239
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.753884900
Short name T397
Test name
Test status
Simulation time 331748411996 ps
CPU time 691.85 seconds
Started Aug 13 06:07:02 PM PDT 24
Finished Aug 13 06:18:34 PM PDT 24
Peak memory 202028 kb
Host smart-def350ff-7b45-4c3e-bdee-a2684c66ed69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=753884900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.753884900
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3655355628
Short name T211
Test name
Test status
Simulation time 202227677295 ps
CPU time 411.44 seconds
Started Aug 13 06:07:11 PM PDT 24
Finished Aug 13 06:14:02 PM PDT 24
Peak memory 202136 kb
Host smart-d8846c63-da9c-4dab-a2c6-3fdcde417fc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655355628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3655355628
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3634953629
Short name T378
Test name
Test status
Simulation time 197357113355 ps
CPU time 429.16 seconds
Started Aug 13 06:07:12 PM PDT 24
Finished Aug 13 06:14:21 PM PDT 24
Peak memory 202004 kb
Host smart-6c854b89-8f2a-4434-b657-dd399b5047ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634953629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3634953629
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3714787115
Short name T723
Test name
Test status
Simulation time 111075029257 ps
CPU time 568.79 seconds
Started Aug 13 06:07:09 PM PDT 24
Finished Aug 13 06:16:38 PM PDT 24
Peak memory 202452 kb
Host smart-066974e1-bcbe-4040-9624-04a5eb323984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714787115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3714787115
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2364604376
Short name T623
Test name
Test status
Simulation time 35047726257 ps
CPU time 54.71 seconds
Started Aug 13 06:07:10 PM PDT 24
Finished Aug 13 06:08:04 PM PDT 24
Peak memory 201972 kb
Host smart-65bc1e96-4e34-459a-bfd0-8c6f769b8834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364604376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2364604376
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3104561556
Short name T528
Test name
Test status
Simulation time 5299130695 ps
CPU time 3.58 seconds
Started Aug 13 06:07:09 PM PDT 24
Finished Aug 13 06:07:12 PM PDT 24
Peak memory 201944 kb
Host smart-f3e9103b-ca6c-4e81-9a50-a899d2f4d4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104561556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3104561556
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3983630689
Short name T543
Test name
Test status
Simulation time 6292784120 ps
CPU time 1.58 seconds
Started Aug 13 06:07:03 PM PDT 24
Finished Aug 13 06:07:05 PM PDT 24
Peak memory 201960 kb
Host smart-6b012111-6ea5-4540-993a-e8b022567a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983630689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3983630689
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.961948945
Short name T39
Test name
Test status
Simulation time 40467451559 ps
CPU time 92.67 seconds
Started Aug 13 06:07:09 PM PDT 24
Finished Aug 13 06:08:42 PM PDT 24
Peak memory 201964 kb
Host smart-2f54a3b9-c14f-4a83-bf68-bea2d5a0d010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961948945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
961948945
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3817360780
Short name T336
Test name
Test status
Simulation time 23427009504 ps
CPU time 12.5 seconds
Started Aug 13 06:07:10 PM PDT 24
Finished Aug 13 06:07:23 PM PDT 24
Peak memory 210556 kb
Host smart-0c3c5867-93f3-4ee1-8a87-79214d53eaf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817360780 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3817360780
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1520362830
Short name T522
Test name
Test status
Simulation time 485572964 ps
CPU time 1.36 seconds
Started Aug 13 06:07:18 PM PDT 24
Finished Aug 13 06:07:19 PM PDT 24
Peak memory 202008 kb
Host smart-e917a8ff-303b-4b03-a0b4-8125ec180e09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520362830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1520362830
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.319396880
Short name T290
Test name
Test status
Simulation time 495461396102 ps
CPU time 503 seconds
Started Aug 13 06:07:18 PM PDT 24
Finished Aug 13 06:15:41 PM PDT 24
Peak memory 202132 kb
Host smart-8707b073-07b3-4dca-82a3-53affb6f85c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319396880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.319396880
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3606710159
Short name T444
Test name
Test status
Simulation time 163489239807 ps
CPU time 379.17 seconds
Started Aug 13 06:07:09 PM PDT 24
Finished Aug 13 06:13:29 PM PDT 24
Peak memory 202112 kb
Host smart-94fe4db5-da6b-490d-87d3-aa9f041ed83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606710159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3606710159
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3983467167
Short name T557
Test name
Test status
Simulation time 157832939403 ps
CPU time 358.75 seconds
Started Aug 13 06:07:17 PM PDT 24
Finished Aug 13 06:13:16 PM PDT 24
Peak memory 202204 kb
Host smart-b8d58c88-0d56-4efc-ae8a-4061d97ff3bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983467167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3983467167
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2617928965
Short name T277
Test name
Test status
Simulation time 325134637366 ps
CPU time 611.88 seconds
Started Aug 13 06:07:10 PM PDT 24
Finished Aug 13 06:17:22 PM PDT 24
Peak memory 202120 kb
Host smart-b3a04d27-5b74-47ea-b169-fcf8bd08e487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617928965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2617928965
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1948013509
Short name T387
Test name
Test status
Simulation time 335717580731 ps
CPU time 355.58 seconds
Started Aug 13 06:07:08 PM PDT 24
Finished Aug 13 06:13:03 PM PDT 24
Peak memory 202120 kb
Host smart-4471dffa-99ab-49bc-8efe-6ad724e40c37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948013509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1948013509
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.173658190
Short name T504
Test name
Test status
Simulation time 178844830615 ps
CPU time 24.69 seconds
Started Aug 13 06:07:17 PM PDT 24
Finished Aug 13 06:07:42 PM PDT 24
Peak memory 202132 kb
Host smart-2ba5853f-b23e-43f4-afef-09a4b5aba64d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173658190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.173658190
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1433639684
Short name T672
Test name
Test status
Simulation time 204347539842 ps
CPU time 418.03 seconds
Started Aug 13 06:07:18 PM PDT 24
Finished Aug 13 06:14:16 PM PDT 24
Peak memory 202120 kb
Host smart-b6c1a4fa-98cc-46be-bec1-e5f34ed01a23
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433639684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1433639684
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1383974730
Short name T508
Test name
Test status
Simulation time 72342771160 ps
CPU time 368.71 seconds
Started Aug 13 06:07:16 PM PDT 24
Finished Aug 13 06:13:25 PM PDT 24
Peak memory 202396 kb
Host smart-55610f09-d8ee-483d-9fbf-32f9760795fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383974730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1383974730
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2112058755
Short name T676
Test name
Test status
Simulation time 37639413253 ps
CPU time 88.44 seconds
Started Aug 13 06:07:17 PM PDT 24
Finished Aug 13 06:08:46 PM PDT 24
Peak memory 201972 kb
Host smart-48034d5f-916d-41cf-b0c9-cca4be8aad58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112058755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2112058755
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.4242913228
Short name T519
Test name
Test status
Simulation time 4373528374 ps
CPU time 9.16 seconds
Started Aug 13 06:07:17 PM PDT 24
Finished Aug 13 06:07:26 PM PDT 24
Peak memory 201880 kb
Host smart-72cae197-4650-4554-80ed-f746decdbc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242913228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4242913228
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3888398918
Short name T541
Test name
Test status
Simulation time 6039819557 ps
CPU time 3.8 seconds
Started Aug 13 06:07:09 PM PDT 24
Finished Aug 13 06:07:13 PM PDT 24
Peak memory 201876 kb
Host smart-3ca65e5e-7b6d-4c41-905c-401d2c95c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888398918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3888398918
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.267472932
Short name T98
Test name
Test status
Simulation time 375428625897 ps
CPU time 843.53 seconds
Started Aug 13 06:07:19 PM PDT 24
Finished Aug 13 06:21:22 PM PDT 24
Peak memory 202172 kb
Host smart-1d484ef6-0902-4f29-bd4d-593463aae3bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267472932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
267472932
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1502615215
Short name T92
Test name
Test status
Simulation time 901355323 ps
CPU time 4.58 seconds
Started Aug 13 06:07:16 PM PDT 24
Finished Aug 13 06:07:20 PM PDT 24
Peak memory 202056 kb
Host smart-00e325db-9bdb-4f90-b278-3e4f80d6b2dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502615215 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1502615215
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4113625656
Short name T185
Test name
Test status
Simulation time 532639499 ps
CPU time 1.21 seconds
Started Aug 13 06:07:34 PM PDT 24
Finished Aug 13 06:07:35 PM PDT 24
Peak memory 201868 kb
Host smart-a81c1a4a-298e-4fb1-a19e-250b2f5ec663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113625656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4113625656
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3805382406
Short name T578
Test name
Test status
Simulation time 161635681945 ps
CPU time 359.52 seconds
Started Aug 13 06:07:25 PM PDT 24
Finished Aug 13 06:13:25 PM PDT 24
Peak memory 202108 kb
Host smart-ffbb82f0-884c-4b10-a468-d6954d311d18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805382406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3805382406
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1946232671
Short name T561
Test name
Test status
Simulation time 165033731587 ps
CPU time 392.7 seconds
Started Aug 13 06:07:23 PM PDT 24
Finished Aug 13 06:13:56 PM PDT 24
Peak memory 202136 kb
Host smart-1f256e77-3ea8-4ec1-999b-de1557798ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946232671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1946232671
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1959464796
Short name T115
Test name
Test status
Simulation time 492157633496 ps
CPU time 162.61 seconds
Started Aug 13 06:07:24 PM PDT 24
Finished Aug 13 06:10:07 PM PDT 24
Peak memory 202140 kb
Host smart-0d5bc121-a010-46ef-b8be-1c2217780865
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959464796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1959464796
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2570552581
Short name T726
Test name
Test status
Simulation time 266173825913 ps
CPU time 596.43 seconds
Started Aug 13 06:07:36 PM PDT 24
Finished Aug 13 06:17:32 PM PDT 24
Peak memory 202256 kb
Host smart-da538394-4577-4c0f-8c42-eef53ff72ab3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570552581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2570552581
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2271665882
Short name T618
Test name
Test status
Simulation time 196064732648 ps
CPU time 401.58 seconds
Started Aug 13 06:07:35 PM PDT 24
Finished Aug 13 06:14:17 PM PDT 24
Peak memory 202256 kb
Host smart-b497ad27-6f78-42dd-ae5b-47f7088748e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271665882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2271665882
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3681126788
Short name T64
Test name
Test status
Simulation time 96791706913 ps
CPU time 367.62 seconds
Started Aug 13 06:07:37 PM PDT 24
Finished Aug 13 06:13:44 PM PDT 24
Peak memory 202508 kb
Host smart-7c28ab86-4e6b-41f7-af52-7b0207310c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681126788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3681126788
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3423579939
Short name T631
Test name
Test status
Simulation time 35558491268 ps
CPU time 37.38 seconds
Started Aug 13 06:07:36 PM PDT 24
Finished Aug 13 06:08:14 PM PDT 24
Peak memory 202092 kb
Host smart-543bab71-f7d7-4f66-8c46-040dd2b9981c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423579939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3423579939
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3333501745
Short name T620
Test name
Test status
Simulation time 4439617432 ps
CPU time 3.24 seconds
Started Aug 13 06:07:32 PM PDT 24
Finished Aug 13 06:07:36 PM PDT 24
Peak memory 201964 kb
Host smart-829ddf7b-45d7-4204-8e1b-a268c839fe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333501745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3333501745
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2492598973
Short name T554
Test name
Test status
Simulation time 5752299725 ps
CPU time 3.11 seconds
Started Aug 13 06:07:21 PM PDT 24
Finished Aug 13 06:07:24 PM PDT 24
Peak memory 201936 kb
Host smart-46fc59fa-9892-43c1-b77f-2faf5b748ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492598973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2492598973
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3026287770
Short name T747
Test name
Test status
Simulation time 222999086516 ps
CPU time 271.72 seconds
Started Aug 13 06:07:31 PM PDT 24
Finished Aug 13 06:12:03 PM PDT 24
Peak memory 202128 kb
Host smart-face70d3-44b0-4eee-9f78-618dc572ab5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026287770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3026287770
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.733242867
Short name T25
Test name
Test status
Simulation time 4876487597 ps
CPU time 17.36 seconds
Started Aug 13 06:07:33 PM PDT 24
Finished Aug 13 06:07:51 PM PDT 24
Peak memory 218572 kb
Host smart-6eb577f1-d82f-4bc1-a7db-a29c5b220a76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733242867 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.733242867
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.952166562
Short name T418
Test name
Test status
Simulation time 375690654 ps
CPU time 0.84 seconds
Started Aug 13 06:07:47 PM PDT 24
Finished Aug 13 06:07:48 PM PDT 24
Peak memory 201944 kb
Host smart-a6f0f83d-1f5a-4149-a952-5b87012e69b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952166562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.952166562
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3737039736
Short name T737
Test name
Test status
Simulation time 162626667048 ps
CPU time 22.52 seconds
Started Aug 13 06:07:42 PM PDT 24
Finished Aug 13 06:08:04 PM PDT 24
Peak memory 202132 kb
Host smart-87843e62-d96d-4275-be4b-cb63bd4e9e67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737039736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3737039736
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3702875304
Short name T629
Test name
Test status
Simulation time 164502637410 ps
CPU time 105.55 seconds
Started Aug 13 06:07:40 PM PDT 24
Finished Aug 13 06:09:25 PM PDT 24
Peak memory 202160 kb
Host smart-7123f421-8dca-446f-a9c4-a1b2c420b66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702875304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3702875304
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2021659788
Short name T772
Test name
Test status
Simulation time 327165288005 ps
CPU time 757.45 seconds
Started Aug 13 06:07:37 PM PDT 24
Finished Aug 13 06:20:15 PM PDT 24
Peak memory 202148 kb
Host smart-ad641249-0af0-4cec-a905-6e2d4953f473
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021659788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2021659788
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1811464317
Short name T107
Test name
Test status
Simulation time 491552554095 ps
CPU time 128.34 seconds
Started Aug 13 06:07:40 PM PDT 24
Finished Aug 13 06:09:48 PM PDT 24
Peak memory 202144 kb
Host smart-2e597264-c530-4eed-be17-fa3fb1eb1511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811464317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1811464317
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.7096051
Short name T498
Test name
Test status
Simulation time 164156151474 ps
CPU time 94.4 seconds
Started Aug 13 06:07:42 PM PDT 24
Finished Aug 13 06:09:17 PM PDT 24
Peak memory 202124 kb
Host smart-fdb5f38a-97a9-4b10-9cf9-e86bef23120a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=7096051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.7096051
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3708862612
Short name T727
Test name
Test status
Simulation time 391405964909 ps
CPU time 905.41 seconds
Started Aug 13 06:07:40 PM PDT 24
Finished Aug 13 06:22:45 PM PDT 24
Peak memory 202028 kb
Host smart-077663d2-c36e-4abb-b609-812868799516
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708862612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3708862612
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4053931896
Short name T239
Test name
Test status
Simulation time 108489428093 ps
CPU time 562.62 seconds
Started Aug 13 06:07:48 PM PDT 24
Finished Aug 13 06:17:11 PM PDT 24
Peak memory 202440 kb
Host smart-b5e5d1d5-c2fd-4f85-b359-d351a932b3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053931896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4053931896
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1545995598
Short name T391
Test name
Test status
Simulation time 46353244781 ps
CPU time 11.64 seconds
Started Aug 13 06:07:52 PM PDT 24
Finished Aug 13 06:08:04 PM PDT 24
Peak memory 201960 kb
Host smart-6770adc3-97ba-467a-bfa1-d5e856214f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545995598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1545995598
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3299743597
Short name T687
Test name
Test status
Simulation time 3734906841 ps
CPU time 3.83 seconds
Started Aug 13 06:07:41 PM PDT 24
Finished Aug 13 06:07:45 PM PDT 24
Peak memory 201832 kb
Host smart-4800fa59-cc4e-45ab-bda5-d4f4b0fbcc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299743597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3299743597
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.673634694
Short name T568
Test name
Test status
Simulation time 5528703940 ps
CPU time 12.6 seconds
Started Aug 13 06:07:41 PM PDT 24
Finished Aug 13 06:07:54 PM PDT 24
Peak memory 201940 kb
Host smart-9b878532-c0e8-4576-980f-2b8871f088cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673634694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.673634694
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3775345389
Short name T758
Test name
Test status
Simulation time 49737612482 ps
CPU time 90.46 seconds
Started Aug 13 06:07:47 PM PDT 24
Finished Aug 13 06:09:18 PM PDT 24
Peak memory 201964 kb
Host smart-21be7c08-c813-461a-b6cf-5ae321d3d4a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775345389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3775345389
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2519033560
Short name T51
Test name
Test status
Simulation time 24521214260 ps
CPU time 12.33 seconds
Started Aug 13 06:07:48 PM PDT 24
Finished Aug 13 06:08:00 PM PDT 24
Peak memory 210408 kb
Host smart-85b7fd89-d928-4197-aaa6-c238af633d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519033560 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2519033560
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3455832308
Short name T694
Test name
Test status
Simulation time 481170625 ps
CPU time 1.71 seconds
Started Aug 13 06:08:00 PM PDT 24
Finished Aug 13 06:08:02 PM PDT 24
Peak memory 202008 kb
Host smart-6ca98a31-54a7-49e3-9685-6a270bf2d87f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455832308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3455832308
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2502640396
Short name T574
Test name
Test status
Simulation time 332461763451 ps
CPU time 56.62 seconds
Started Aug 13 06:07:46 PM PDT 24
Finished Aug 13 06:08:43 PM PDT 24
Peak memory 202044 kb
Host smart-89719943-e6a9-48f0-b96f-b1d03a0387ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502640396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2502640396
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.58990266
Short name T320
Test name
Test status
Simulation time 510914751995 ps
CPU time 306.68 seconds
Started Aug 13 06:07:55 PM PDT 24
Finished Aug 13 06:13:02 PM PDT 24
Peak memory 202124 kb
Host smart-b03ac51d-7261-4814-aabf-6717ccf2a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58990266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.58990266
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3511417329
Short name T647
Test name
Test status
Simulation time 494426967154 ps
CPU time 629.52 seconds
Started Aug 13 06:07:47 PM PDT 24
Finished Aug 13 06:18:17 PM PDT 24
Peak memory 202060 kb
Host smart-ef8a3e94-a373-41a6-b462-b7fbd04bfb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511417329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3511417329
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1037066365
Short name T582
Test name
Test status
Simulation time 328550470635 ps
CPU time 224.5 seconds
Started Aug 13 06:07:52 PM PDT 24
Finished Aug 13 06:11:36 PM PDT 24
Peak memory 202188 kb
Host smart-efb2ffa7-8248-461b-aed3-57fde0aaf2bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037066365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1037066365
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3528225619
Short name T297
Test name
Test status
Simulation time 165569609570 ps
CPU time 343.16 seconds
Started Aug 13 06:07:47 PM PDT 24
Finished Aug 13 06:13:30 PM PDT 24
Peak memory 202144 kb
Host smart-5cad6690-ef05-47d4-9a24-01ed77033c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528225619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3528225619
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3796088244
Short name T627
Test name
Test status
Simulation time 163476754657 ps
CPU time 348.16 seconds
Started Aug 13 06:07:47 PM PDT 24
Finished Aug 13 06:13:36 PM PDT 24
Peak memory 202000 kb
Host smart-de95d4b4-3489-42f0-a1bc-156a627941dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796088244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3796088244
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2923008767
Short name T180
Test name
Test status
Simulation time 538759402817 ps
CPU time 698.64 seconds
Started Aug 13 06:07:52 PM PDT 24
Finished Aug 13 06:19:31 PM PDT 24
Peak memory 202112 kb
Host smart-17de6856-f02f-45c2-9f2d-6ee8294b0c5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923008767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2923008767
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3305830899
Short name T112
Test name
Test status
Simulation time 617855012214 ps
CPU time 110.66 seconds
Started Aug 13 06:07:47 PM PDT 24
Finished Aug 13 06:09:38 PM PDT 24
Peak memory 202148 kb
Host smart-adf90de0-a3ec-4602-af70-3827940f7a30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305830899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3305830899
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1737413469
Short name T246
Test name
Test status
Simulation time 82827239013 ps
CPU time 344.81 seconds
Started Aug 13 06:07:57 PM PDT 24
Finished Aug 13 06:13:42 PM PDT 24
Peak memory 202460 kb
Host smart-f78200d3-1450-4720-b736-6664c9866406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737413469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1737413469
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2335719505
Short name T608
Test name
Test status
Simulation time 31820156383 ps
CPU time 62.32 seconds
Started Aug 13 06:07:56 PM PDT 24
Finished Aug 13 06:08:58 PM PDT 24
Peak memory 201936 kb
Host smart-b953c6b6-923e-4f1f-ab20-4f5ac7dca4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335719505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2335719505
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3631863577
Short name T537
Test name
Test status
Simulation time 3021889635 ps
CPU time 8.1 seconds
Started Aug 13 06:07:57 PM PDT 24
Finished Aug 13 06:08:05 PM PDT 24
Peak memory 201884 kb
Host smart-a5015cfc-ff80-4ac4-b960-4cf8406ba0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631863577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3631863577
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3865435684
Short name T500
Test name
Test status
Simulation time 5808363892 ps
CPU time 14.39 seconds
Started Aug 13 06:07:47 PM PDT 24
Finished Aug 13 06:08:02 PM PDT 24
Peak memory 201960 kb
Host smart-2191aa1d-572e-4bea-9246-d8a872788da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865435684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3865435684
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3351199225
Short name T730
Test name
Test status
Simulation time 6866268920 ps
CPU time 11.34 seconds
Started Aug 13 06:08:00 PM PDT 24
Finished Aug 13 06:08:11 PM PDT 24
Peak memory 210740 kb
Host smart-05d817aa-6158-4b80-8434-11dbc09d0d78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351199225 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3351199225
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2281365376
Short name T461
Test name
Test status
Simulation time 493014577 ps
CPU time 0.77 seconds
Started Aug 13 06:08:05 PM PDT 24
Finished Aug 13 06:08:06 PM PDT 24
Peak memory 201932 kb
Host smart-7f8727d8-232d-48f9-9988-19fc1f01ff34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281365376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2281365376
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.4152320851
Short name T742
Test name
Test status
Simulation time 343449695531 ps
CPU time 197.5 seconds
Started Aug 13 06:08:00 PM PDT 24
Finished Aug 13 06:11:18 PM PDT 24
Peak memory 202160 kb
Host smart-bb72f923-1d50-4dd5-9d3c-8c7cbefb4cc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152320851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.4152320851
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4014370727
Short name T189
Test name
Test status
Simulation time 165655588649 ps
CPU time 175.05 seconds
Started Aug 13 06:08:07 PM PDT 24
Finished Aug 13 06:11:02 PM PDT 24
Peak memory 202200 kb
Host smart-2a7e7179-2156-455e-8d59-99732aadb7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014370727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4014370727
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2012683234
Short name T167
Test name
Test status
Simulation time 494608088112 ps
CPU time 1202.04 seconds
Started Aug 13 06:07:58 PM PDT 24
Finished Aug 13 06:28:00 PM PDT 24
Peak memory 202192 kb
Host smart-b537e16f-e0fb-44b6-a119-5233ddd5ca12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012683234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2012683234
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1801391801
Short name T497
Test name
Test status
Simulation time 163214656424 ps
CPU time 182.72 seconds
Started Aug 13 06:07:58 PM PDT 24
Finished Aug 13 06:11:00 PM PDT 24
Peak memory 202168 kb
Host smart-a6d9a35c-8bb9-4f74-a917-90b40eaef9b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801391801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1801391801
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3888572873
Short name T712
Test name
Test status
Simulation time 491677529365 ps
CPU time 1126.65 seconds
Started Aug 13 06:07:57 PM PDT 24
Finished Aug 13 06:26:44 PM PDT 24
Peak memory 202160 kb
Host smart-b5eaecd4-eb3e-488f-8cee-f72be23cc9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888572873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3888572873
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1370886214
Short name T664
Test name
Test status
Simulation time 327912598374 ps
CPU time 766.35 seconds
Started Aug 13 06:08:07 PM PDT 24
Finished Aug 13 06:20:54 PM PDT 24
Peak memory 202120 kb
Host smart-da48d063-b4a1-45d7-964f-af9b624a80ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370886214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1370886214
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3443279428
Short name T198
Test name
Test status
Simulation time 359072899854 ps
CPU time 212.29 seconds
Started Aug 13 06:07:58 PM PDT 24
Finished Aug 13 06:11:31 PM PDT 24
Peak memory 202144 kb
Host smart-27bc42fe-a3a6-430a-8a30-b51f1c55cfad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443279428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3443279428
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1478820899
Short name T577
Test name
Test status
Simulation time 193468546299 ps
CPU time 212.74 seconds
Started Aug 13 06:07:57 PM PDT 24
Finished Aug 13 06:11:29 PM PDT 24
Peak memory 202112 kb
Host smart-f932622e-8d7d-4130-a768-37916959995e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478820899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1478820899
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3186528685
Short name T237
Test name
Test status
Simulation time 92312896182 ps
CPU time 329.85 seconds
Started Aug 13 06:08:09 PM PDT 24
Finished Aug 13 06:13:39 PM PDT 24
Peak memory 202272 kb
Host smart-bc1062f4-359c-44a7-9a75-553cdc099400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186528685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3186528685
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3199664152
Short name T711
Test name
Test status
Simulation time 22373839557 ps
CPU time 26.67 seconds
Started Aug 13 06:08:07 PM PDT 24
Finished Aug 13 06:08:34 PM PDT 24
Peak memory 201860 kb
Host smart-105dc394-d359-4047-9b85-f04b51bec7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199664152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3199664152
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1950835504
Short name T382
Test name
Test status
Simulation time 3419100876 ps
CPU time 8.38 seconds
Started Aug 13 06:08:08 PM PDT 24
Finished Aug 13 06:08:17 PM PDT 24
Peak memory 201880 kb
Host smart-c0bf079e-cc8a-4568-9cf4-1ef5b9f20686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950835504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1950835504
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.169241391
Short name T743
Test name
Test status
Simulation time 6101477294 ps
CPU time 4.43 seconds
Started Aug 13 06:07:57 PM PDT 24
Finished Aug 13 06:08:02 PM PDT 24
Peak memory 201908 kb
Host smart-315e2a05-2a0d-432d-a1c7-9d6329365d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169241391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.169241391
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3971939066
Short name T27
Test name
Test status
Simulation time 9913186141 ps
CPU time 10.91 seconds
Started Aug 13 06:08:06 PM PDT 24
Finished Aug 13 06:08:17 PM PDT 24
Peak memory 210488 kb
Host smart-69fd1411-f4a3-4392-abc2-e50ce7d1a689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971939066 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3971939066
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2366957582
Short name T457
Test name
Test status
Simulation time 447522248 ps
CPU time 0.87 seconds
Started Aug 13 06:08:14 PM PDT 24
Finished Aug 13 06:08:15 PM PDT 24
Peak memory 201896 kb
Host smart-b7e226b0-b1ad-4ba7-9115-ee144639b67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366957582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2366957582
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.478122668
Short name T194
Test name
Test status
Simulation time 176779987173 ps
CPU time 101.72 seconds
Started Aug 13 06:08:15 PM PDT 24
Finished Aug 13 06:09:56 PM PDT 24
Peak memory 202112 kb
Host smart-c2894454-590e-4158-bcd6-14dfdd6a0e8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478122668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.478122668
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1998957819
Short name T529
Test name
Test status
Simulation time 172514694534 ps
CPU time 106.61 seconds
Started Aug 13 06:08:14 PM PDT 24
Finished Aug 13 06:10:01 PM PDT 24
Peak memory 202196 kb
Host smart-cadf754b-7f32-4fe6-b4bf-8fc2302ab8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998957819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1998957819
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.618802913
Short name T144
Test name
Test status
Simulation time 169747260944 ps
CPU time 194.27 seconds
Started Aug 13 06:08:07 PM PDT 24
Finished Aug 13 06:11:21 PM PDT 24
Peak memory 202160 kb
Host smart-f639107d-7bd5-448f-a9ee-3e1929f19e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618802913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.618802913
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1141930148
Short name T640
Test name
Test status
Simulation time 483908576104 ps
CPU time 280.52 seconds
Started Aug 13 06:08:06 PM PDT 24
Finished Aug 13 06:12:47 PM PDT 24
Peak memory 202156 kb
Host smart-6a17c80a-7ed0-465e-b359-8db03a2b24fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141930148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1141930148
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.829074306
Short name T99
Test name
Test status
Simulation time 490988950071 ps
CPU time 569.32 seconds
Started Aug 13 06:08:07 PM PDT 24
Finished Aug 13 06:17:37 PM PDT 24
Peak memory 202136 kb
Host smart-b70b63b1-2b32-4690-af8a-ff4b867e2e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829074306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.829074306
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1200452723
Short name T734
Test name
Test status
Simulation time 166260256048 ps
CPU time 337.98 seconds
Started Aug 13 06:08:05 PM PDT 24
Finished Aug 13 06:13:43 PM PDT 24
Peak memory 202120 kb
Host smart-c7e1de3f-9721-4b87-bef2-424cd77f4ebf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200452723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1200452723
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.774428066
Short name T226
Test name
Test status
Simulation time 531999935371 ps
CPU time 307.9 seconds
Started Aug 13 06:08:12 PM PDT 24
Finished Aug 13 06:13:20 PM PDT 24
Peak memory 202156 kb
Host smart-4e1f22fb-a68d-4f90-a319-9ba334482155
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774428066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.774428066
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1415693452
Short name T445
Test name
Test status
Simulation time 404364452264 ps
CPU time 231.88 seconds
Started Aug 13 06:08:13 PM PDT 24
Finished Aug 13 06:12:05 PM PDT 24
Peak memory 202160 kb
Host smart-38969f07-6817-4d07-9ec5-5966bdde5393
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415693452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1415693452
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2895361180
Short name T234
Test name
Test status
Simulation time 123082191821 ps
CPU time 658.96 seconds
Started Aug 13 06:08:14 PM PDT 24
Finished Aug 13 06:19:13 PM PDT 24
Peak memory 202392 kb
Host smart-e3f0378f-6029-4ae8-b975-6b02dc67f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895361180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2895361180
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.4163064744
Short name T721
Test name
Test status
Simulation time 35159251207 ps
CPU time 37.28 seconds
Started Aug 13 06:08:12 PM PDT 24
Finished Aug 13 06:08:49 PM PDT 24
Peak memory 201844 kb
Host smart-351b3b66-f867-480e-a4fb-44b93800485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163064744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.4163064744
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1942309265
Short name T628
Test name
Test status
Simulation time 2888742272 ps
CPU time 7.37 seconds
Started Aug 13 06:08:14 PM PDT 24
Finished Aug 13 06:08:21 PM PDT 24
Peak memory 201964 kb
Host smart-25b46770-e96f-4d5f-966c-e61395adcb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942309265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1942309265
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1236650520
Short name T206
Test name
Test status
Simulation time 5489575343 ps
CPU time 12.78 seconds
Started Aug 13 06:08:11 PM PDT 24
Finished Aug 13 06:08:24 PM PDT 24
Peak memory 201976 kb
Host smart-6b2d10e4-089a-49ca-a7d6-5830cc215676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236650520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1236650520
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1246951814
Short name T37
Test name
Test status
Simulation time 414868358514 ps
CPU time 875.15 seconds
Started Aug 13 06:08:13 PM PDT 24
Finished Aug 13 06:22:48 PM PDT 24
Peak memory 210672 kb
Host smart-ef511459-b673-4bf6-9775-6a3ea472d307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246951814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1246951814
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1729999519
Short name T24
Test name
Test status
Simulation time 12430515951 ps
CPU time 20.37 seconds
Started Aug 13 06:08:14 PM PDT 24
Finished Aug 13 06:08:34 PM PDT 24
Peak memory 210660 kb
Host smart-bbb80d50-d6af-42e2-8a85-31b52ed323af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729999519 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1729999519
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3773041303
Short name T605
Test name
Test status
Simulation time 531683115 ps
CPU time 1.24 seconds
Started Aug 13 06:08:32 PM PDT 24
Finished Aug 13 06:08:33 PM PDT 24
Peak memory 201852 kb
Host smart-b007b314-91ea-43e9-82d0-bf48e6c3f92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773041303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3773041303
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.777228641
Short name T770
Test name
Test status
Simulation time 161763369526 ps
CPU time 95.45 seconds
Started Aug 13 06:08:28 PM PDT 24
Finished Aug 13 06:10:03 PM PDT 24
Peak memory 202136 kb
Host smart-5eaf1733-b872-41e9-ac6b-d4e9617d3f56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777228641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.777228641
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2521318450
Short name T283
Test name
Test status
Simulation time 322287032952 ps
CPU time 708.64 seconds
Started Aug 13 06:08:28 PM PDT 24
Finished Aug 13 06:20:16 PM PDT 24
Peak memory 202148 kb
Host smart-faf50fdc-cd89-47d6-b219-44b6c2697bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521318450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2521318450
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1000858626
Short name T369
Test name
Test status
Simulation time 490328046311 ps
CPU time 1065.82 seconds
Started Aug 13 06:08:22 PM PDT 24
Finished Aug 13 06:26:08 PM PDT 24
Peak memory 202204 kb
Host smart-5a05ff3e-d5fe-4e22-87cd-bcd8a8a5b6ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000858626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1000858626
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.905133920
Short name T36
Test name
Test status
Simulation time 328183849861 ps
CPU time 171.52 seconds
Started Aug 13 06:08:15 PM PDT 24
Finished Aug 13 06:11:07 PM PDT 24
Peak memory 202160 kb
Host smart-68c43c1b-0f28-4c9c-a65b-0f5a6588fe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905133920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.905133920
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.93574013
Short name T177
Test name
Test status
Simulation time 165966557782 ps
CPU time 89.62 seconds
Started Aug 13 06:08:28 PM PDT 24
Finished Aug 13 06:09:57 PM PDT 24
Peak memory 202144 kb
Host smart-a88e81dc-261a-47b3-830a-b67175af2ead
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=93574013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed
.93574013
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.127762060
Short name T155
Test name
Test status
Simulation time 172074375276 ps
CPU time 367.52 seconds
Started Aug 13 06:08:22 PM PDT 24
Finished Aug 13 06:14:29 PM PDT 24
Peak memory 202132 kb
Host smart-39aa926f-bbe3-4713-9be2-d2b30d499d48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127762060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.127762060
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3563962365
Short name T415
Test name
Test status
Simulation time 194793070468 ps
CPU time 404.5 seconds
Started Aug 13 06:08:22 PM PDT 24
Finished Aug 13 06:15:07 PM PDT 24
Peak memory 202168 kb
Host smart-5730f0e0-6075-4942-b316-e7c3e4f15556
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563962365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3563962365
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2714928669
Short name T539
Test name
Test status
Simulation time 93500528186 ps
CPU time 316.59 seconds
Started Aug 13 06:08:23 PM PDT 24
Finished Aug 13 06:13:39 PM PDT 24
Peak memory 202376 kb
Host smart-e1348d8f-ec2e-40c9-8cc9-e6190f98e25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714928669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2714928669
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3729997037
Short name T564
Test name
Test status
Simulation time 39686067586 ps
CPU time 92.48 seconds
Started Aug 13 06:08:19 PM PDT 24
Finished Aug 13 06:09:52 PM PDT 24
Peak memory 201916 kb
Host smart-d5bc21f3-9810-4706-959f-fbfe3a78507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729997037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3729997037
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2942779895
Short name T773
Test name
Test status
Simulation time 3062590756 ps
CPU time 3.18 seconds
Started Aug 13 06:08:23 PM PDT 24
Finished Aug 13 06:08:26 PM PDT 24
Peak memory 201968 kb
Host smart-452a3c19-18ca-4904-82c4-62c09db37da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942779895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2942779895
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3299930559
Short name T40
Test name
Test status
Simulation time 5629755549 ps
CPU time 2.44 seconds
Started Aug 13 06:08:09 PM PDT 24
Finished Aug 13 06:08:12 PM PDT 24
Peak memory 201936 kb
Host smart-37801f5c-c6ee-44b3-9794-df8b7866fb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299930559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3299930559
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.860763282
Short name T776
Test name
Test status
Simulation time 418008873 ps
CPU time 0.68 seconds
Started Aug 13 06:08:41 PM PDT 24
Finished Aug 13 06:08:42 PM PDT 24
Peak memory 201956 kb
Host smart-2fd0a7f4-7ddd-4dba-8693-816801a86593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860763282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.860763282
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2922399707
Short name T303
Test name
Test status
Simulation time 618271263002 ps
CPU time 925.11 seconds
Started Aug 13 06:08:41 PM PDT 24
Finished Aug 13 06:24:06 PM PDT 24
Peak memory 202096 kb
Host smart-245ce59d-f547-4ed0-8bd9-b20bccc35579
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922399707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2922399707
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2208730612
Short name T272
Test name
Test status
Simulation time 182074370406 ps
CPU time 361.12 seconds
Started Aug 13 06:08:40 PM PDT 24
Finished Aug 13 06:14:41 PM PDT 24
Peak memory 202108 kb
Host smart-3dcc914d-54fa-4627-a1d3-b9c794eb105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208730612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2208730612
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.4101548043
Short name T262
Test name
Test status
Simulation time 318180248450 ps
CPU time 731.15 seconds
Started Aug 13 06:08:30 PM PDT 24
Finished Aug 13 06:20:41 PM PDT 24
Peak memory 202164 kb
Host smart-29abffdf-89ec-43ac-b7e0-48b9e7c58967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101548043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.4101548043
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2992126752
Short name T417
Test name
Test status
Simulation time 328360186238 ps
CPU time 736.66 seconds
Started Aug 13 06:08:31 PM PDT 24
Finished Aug 13 06:20:48 PM PDT 24
Peak memory 202100 kb
Host smart-309ca8f6-dfe6-4e98-a361-1e44082ad1bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992126752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2992126752
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3409007454
Short name T611
Test name
Test status
Simulation time 334040967760 ps
CPU time 196.24 seconds
Started Aug 13 06:08:30 PM PDT 24
Finished Aug 13 06:11:47 PM PDT 24
Peak memory 202120 kb
Host smart-8ef0e9fc-8bff-44fe-a809-7d92cc8f2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409007454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3409007454
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3828828811
Short name T624
Test name
Test status
Simulation time 336370393456 ps
CPU time 195.31 seconds
Started Aug 13 06:08:30 PM PDT 24
Finished Aug 13 06:11:46 PM PDT 24
Peak memory 202076 kb
Host smart-56b5f4c4-dfa7-4233-aab7-1ef34c9650cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828828811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3828828811
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3785576478
Short name T147
Test name
Test status
Simulation time 532818361081 ps
CPU time 568.88 seconds
Started Aug 13 06:08:30 PM PDT 24
Finished Aug 13 06:17:59 PM PDT 24
Peak memory 202128 kb
Host smart-69254b1b-b94e-4c3d-8212-613dea43904d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785576478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3785576478
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.48836751
Short name T376
Test name
Test status
Simulation time 395258909085 ps
CPU time 196.84 seconds
Started Aug 13 06:08:33 PM PDT 24
Finished Aug 13 06:11:50 PM PDT 24
Peak memory 202160 kb
Host smart-e6aea162-f996-45e4-b73b-81aea7752956
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48836751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.a
dc_ctrl_filters_wakeup_fixed.48836751
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2322108448
Short name T62
Test name
Test status
Simulation time 71595160350 ps
CPU time 386.34 seconds
Started Aug 13 06:08:41 PM PDT 24
Finished Aug 13 06:15:07 PM PDT 24
Peak memory 202456 kb
Host smart-e6c75827-e585-486d-a545-091c522d690f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322108448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2322108448
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2012381190
Short name T116
Test name
Test status
Simulation time 34186295332 ps
CPU time 20.75 seconds
Started Aug 13 06:08:41 PM PDT 24
Finished Aug 13 06:09:02 PM PDT 24
Peak memory 201988 kb
Host smart-0f8009f2-b29e-4582-b671-2fbbc52c487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012381190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2012381190
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3809563181
Short name T715
Test name
Test status
Simulation time 5119100906 ps
CPU time 6.28 seconds
Started Aug 13 06:08:38 PM PDT 24
Finished Aug 13 06:08:45 PM PDT 24
Peak memory 201944 kb
Host smart-b91ac68f-2cc3-4c38-8b66-3ba519660d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809563181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3809563181
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2718808535
Short name T383
Test name
Test status
Simulation time 5868260791 ps
CPU time 2.19 seconds
Started Aug 13 06:08:31 PM PDT 24
Finished Aug 13 06:08:33 PM PDT 24
Peak memory 201964 kb
Host smart-17ab821b-c51c-4be3-a6de-a7d2f9267ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718808535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2718808535
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2547269621
Short name T596
Test name
Test status
Simulation time 147914563990 ps
CPU time 739.93 seconds
Started Aug 13 06:08:40 PM PDT 24
Finished Aug 13 06:21:00 PM PDT 24
Peak memory 202332 kb
Host smart-736e315a-e6ec-4024-b12d-e5359bf351c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547269621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2547269621
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1315077847
Short name T23
Test name
Test status
Simulation time 70683943828 ps
CPU time 19.65 seconds
Started Aug 13 06:08:42 PM PDT 24
Finished Aug 13 06:09:02 PM PDT 24
Peak memory 218108 kb
Host smart-046e137f-8128-4ce2-8354-a81630758ccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315077847 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1315077847
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.919211325
Short name T448
Test name
Test status
Simulation time 425221904 ps
CPU time 1.6 seconds
Started Aug 13 06:01:14 PM PDT 24
Finished Aug 13 06:01:16 PM PDT 24
Peak memory 201996 kb
Host smart-6840687a-5123-4847-a6cc-62c869d910db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919211325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.919211325
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.23978626
Short name T679
Test name
Test status
Simulation time 163270365922 ps
CPU time 65.43 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:02:10 PM PDT 24
Peak memory 202096 kb
Host smart-f953b59e-973b-4a3b-8b88-1f06db9e037f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23978626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating
.23978626
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.810566257
Short name T122
Test name
Test status
Simulation time 158971643866 ps
CPU time 92.9 seconds
Started Aug 13 06:01:08 PM PDT 24
Finished Aug 13 06:02:41 PM PDT 24
Peak memory 202128 kb
Host smart-f505e82c-9d49-4f41-8f33-a6ce585f723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810566257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.810566257
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3978753215
Short name T360
Test name
Test status
Simulation time 168248265090 ps
CPU time 89.89 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:02:35 PM PDT 24
Peak memory 202268 kb
Host smart-5d98ac6e-0f8e-4b41-839a-ea845eed4262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978753215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3978753215
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4069300171
Short name T571
Test name
Test status
Simulation time 167146743126 ps
CPU time 211.52 seconds
Started Aug 13 06:01:08 PM PDT 24
Finished Aug 13 06:04:40 PM PDT 24
Peak memory 202116 kb
Host smart-33fd7691-e004-4b67-abe5-086a4d0016c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069300171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4069300171
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2515214434
Short name T256
Test name
Test status
Simulation time 327661767972 ps
CPU time 732.92 seconds
Started Aug 13 06:01:07 PM PDT 24
Finished Aug 13 06:13:21 PM PDT 24
Peak memory 202144 kb
Host smart-699694e9-b705-4268-b609-583927f8e182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515214434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2515214434
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3315436194
Short name T595
Test name
Test status
Simulation time 168180469824 ps
CPU time 30.74 seconds
Started Aug 13 06:01:09 PM PDT 24
Finished Aug 13 06:01:39 PM PDT 24
Peak memory 202120 kb
Host smart-c32e9e30-8fe1-41b8-9cdb-85adba3960b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315436194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3315436194
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3341743069
Short name T479
Test name
Test status
Simulation time 588321037917 ps
CPU time 641.14 seconds
Started Aug 13 06:01:07 PM PDT 24
Finished Aug 13 06:11:48 PM PDT 24
Peak memory 202144 kb
Host smart-a0810177-4850-4242-aa30-4e84e07da231
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341743069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3341743069
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.712194359
Short name T559
Test name
Test status
Simulation time 86136704428 ps
CPU time 293.06 seconds
Started Aug 13 06:01:16 PM PDT 24
Finished Aug 13 06:06:09 PM PDT 24
Peak memory 202400 kb
Host smart-dce98bf1-4c8f-4914-93b8-d6d519f6a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712194359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.712194359
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.665166504
Short name T597
Test name
Test status
Simulation time 27781870275 ps
CPU time 16.22 seconds
Started Aug 13 06:01:13 PM PDT 24
Finished Aug 13 06:01:30 PM PDT 24
Peak memory 201964 kb
Host smart-209b6451-af3e-44d2-83ae-77bc19a53d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665166504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.665166504
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.510008350
Short name T422
Test name
Test status
Simulation time 4934221836 ps
CPU time 12.13 seconds
Started Aug 13 06:01:16 PM PDT 24
Finished Aug 13 06:01:28 PM PDT 24
Peak memory 201600 kb
Host smart-465c5037-c35a-434f-bbc8-c74309d4b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510008350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.510008350
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3146481425
Short name T423
Test name
Test status
Simulation time 5903235860 ps
CPU time 3.68 seconds
Started Aug 13 06:01:05 PM PDT 24
Finished Aug 13 06:01:08 PM PDT 24
Peak memory 201992 kb
Host smart-7ae72eb0-a1d0-4b10-88ea-fac79fc8b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146481425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3146481425
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2405461537
Short name T339
Test name
Test status
Simulation time 173178595981 ps
CPU time 108.34 seconds
Started Aug 13 06:01:16 PM PDT 24
Finished Aug 13 06:03:04 PM PDT 24
Peak memory 201916 kb
Host smart-7efd3b59-8236-454a-8ad7-1f00fa051584
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405461537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2405461537
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.769920255
Short name T685
Test name
Test status
Simulation time 2823561413 ps
CPU time 7.11 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:01:23 PM PDT 24
Peak memory 210932 kb
Host smart-e087c885-f9a7-4940-9c83-4c6c5915090e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769920255 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.769920255
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.392035108
Short name T424
Test name
Test status
Simulation time 535833407 ps
CPU time 0.88 seconds
Started Aug 13 06:01:17 PM PDT 24
Finished Aug 13 06:01:18 PM PDT 24
Peak memory 201956 kb
Host smart-260c1335-48fc-4383-8bda-b9068f0494be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392035108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.392035108
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1260562318
Short name T169
Test name
Test status
Simulation time 498765974421 ps
CPU time 1112.28 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:19:48 PM PDT 24
Peak memory 202148 kb
Host smart-98c544d5-197a-4280-bd7a-4bd341968ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260562318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1260562318
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3304875535
Short name T2
Test name
Test status
Simulation time 162183890126 ps
CPU time 88.86 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:02:44 PM PDT 24
Peak memory 202128 kb
Host smart-1dee98b9-d53b-40f2-89df-34c7e5c1c210
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304875535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3304875535
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3490689648
Short name T337
Test name
Test status
Simulation time 503641168853 ps
CPU time 573.3 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:10:49 PM PDT 24
Peak memory 202104 kb
Host smart-47fbf41e-7549-4dfe-a5ac-4c92241c7cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490689648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3490689648
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.494619747
Short name T591
Test name
Test status
Simulation time 330960837582 ps
CPU time 707.53 seconds
Started Aug 13 06:01:14 PM PDT 24
Finished Aug 13 06:13:02 PM PDT 24
Peak memory 202080 kb
Host smart-00c904bf-f85b-4d6e-a994-73647390389d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=494619747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.494619747
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3832465722
Short name T583
Test name
Test status
Simulation time 540917579877 ps
CPU time 1203.8 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:21:19 PM PDT 24
Peak memory 202116 kb
Host smart-4557ba9f-3b8a-49e7-8b14-c67157f4cce0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832465722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3832465722
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4218081553
Short name T373
Test name
Test status
Simulation time 614144318495 ps
CPU time 329.89 seconds
Started Aug 13 06:01:13 PM PDT 24
Finished Aug 13 06:06:43 PM PDT 24
Peak memory 202184 kb
Host smart-284b6e4d-0bfa-42a0-9cb1-671db1c34ab6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218081553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4218081553
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2244272510
Short name T690
Test name
Test status
Simulation time 114238136115 ps
CPU time 532.98 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:10:08 PM PDT 24
Peak memory 202388 kb
Host smart-f83f72e6-741d-4e8b-aab0-2cadae6cc86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244272510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2244272510
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2419988635
Short name T487
Test name
Test status
Simulation time 31996075498 ps
CPU time 18.53 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:01:34 PM PDT 24
Peak memory 201920 kb
Host smart-cd36c4d0-9063-4732-b5b6-557070b2b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419988635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2419988635
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1675012799
Short name T430
Test name
Test status
Simulation time 5072521121 ps
CPU time 12.24 seconds
Started Aug 13 06:01:14 PM PDT 24
Finished Aug 13 06:01:26 PM PDT 24
Peak memory 201972 kb
Host smart-52233529-406f-40e6-a3c0-8768299aa154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675012799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1675012799
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.177540863
Short name T514
Test name
Test status
Simulation time 5710962805 ps
CPU time 5.2 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:01:21 PM PDT 24
Peak memory 201916 kb
Host smart-d3720034-11c8-4f43-b106-bff9057e244e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177540863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.177540863
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1549459930
Short name T183
Test name
Test status
Simulation time 2886113034 ps
CPU time 6.68 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:01:22 PM PDT 24
Peak memory 201992 kb
Host smart-b6adb916-dcc4-44ff-812c-2c65eb51d53a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549459930 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1549459930
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.857900698
Short name T377
Test name
Test status
Simulation time 421947985 ps
CPU time 0.86 seconds
Started Aug 13 06:01:24 PM PDT 24
Finished Aug 13 06:01:24 PM PDT 24
Peak memory 202008 kb
Host smart-81790099-0482-4517-86b7-c6dbad895637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857900698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.857900698
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2261788278
Short name T310
Test name
Test status
Simulation time 527948879955 ps
CPU time 783.17 seconds
Started Aug 13 06:01:22 PM PDT 24
Finished Aug 13 06:14:25 PM PDT 24
Peak memory 202140 kb
Host smart-51240160-f5b6-4548-bb7e-be3e21742a75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261788278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2261788278
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.4113737326
Short name T686
Test name
Test status
Simulation time 500222956482 ps
CPU time 600.79 seconds
Started Aug 13 06:01:26 PM PDT 24
Finished Aug 13 06:11:27 PM PDT 24
Peak memory 202108 kb
Host smart-630bdaf7-8531-43ba-84cd-4502251245ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113737326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.4113737326
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3498686991
Short name T259
Test name
Test status
Simulation time 320152267662 ps
CPU time 394.35 seconds
Started Aug 13 06:01:13 PM PDT 24
Finished Aug 13 06:07:48 PM PDT 24
Peak memory 202132 kb
Host smart-b8d099f4-808c-434c-8f35-41f68124d443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498686991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3498686991
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.337788406
Short name T524
Test name
Test status
Simulation time 486298374976 ps
CPU time 1074.09 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:19:10 PM PDT 24
Peak memory 202144 kb
Host smart-0c880b23-fbd7-4957-a3e3-f5fbd0d8cf94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=337788406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.337788406
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1647648031
Short name T216
Test name
Test status
Simulation time 328858051111 ps
CPU time 171.81 seconds
Started Aug 13 06:01:17 PM PDT 24
Finished Aug 13 06:04:09 PM PDT 24
Peak memory 202124 kb
Host smart-13358e4d-39af-45c7-a014-de90a3e1801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647648031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1647648031
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.277789751
Short name T525
Test name
Test status
Simulation time 164663038514 ps
CPU time 65.79 seconds
Started Aug 13 06:01:15 PM PDT 24
Finished Aug 13 06:02:21 PM PDT 24
Peak memory 201980 kb
Host smart-90f5e0b3-ce64-4ddd-94f2-5f013ee2c7a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=277789751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.277789751
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.351161606
Short name T200
Test name
Test status
Simulation time 436758114993 ps
CPU time 231.76 seconds
Started Aug 13 06:01:14 PM PDT 24
Finished Aug 13 06:05:06 PM PDT 24
Peak memory 202156 kb
Host smart-7264c9e9-98a4-4c40-8007-e005dab6dd3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351161606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.351161606
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4135376179
Short name T465
Test name
Test status
Simulation time 206986336244 ps
CPU time 490.58 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:09:35 PM PDT 24
Peak memory 202156 kb
Host smart-95a6b6de-de03-4e13-a904-ca6d31dd1741
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135376179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4135376179
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1479729576
Short name T563
Test name
Test status
Simulation time 119571318965 ps
CPU time 428.26 seconds
Started Aug 13 06:01:27 PM PDT 24
Finished Aug 13 06:08:35 PM PDT 24
Peak memory 202396 kb
Host smart-230b55c8-7b78-4198-a6d1-8606e83c5b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479729576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1479729576
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4179616658
Short name T395
Test name
Test status
Simulation time 29472062955 ps
CPU time 6.44 seconds
Started Aug 13 06:01:24 PM PDT 24
Finished Aug 13 06:01:31 PM PDT 24
Peak memory 201876 kb
Host smart-6e851d5c-36af-4e69-b09a-97d392279423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179616658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4179616658
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2528891234
Short name T480
Test name
Test status
Simulation time 4610227678 ps
CPU time 2.59 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:01:28 PM PDT 24
Peak memory 201980 kb
Host smart-73792373-a988-4438-a981-60ceb4cd9c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528891234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2528891234
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2595391283
Short name T584
Test name
Test status
Simulation time 5976503686 ps
CPU time 4.09 seconds
Started Aug 13 06:01:14 PM PDT 24
Finished Aug 13 06:01:18 PM PDT 24
Peak memory 201964 kb
Host smart-6647bb76-a349-439e-93bb-59b60e0c7070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595391283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2595391283
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.78907925
Short name T251
Test name
Test status
Simulation time 419870813546 ps
CPU time 736.92 seconds
Started Aug 13 06:01:22 PM PDT 24
Finished Aug 13 06:13:40 PM PDT 24
Peak memory 218712 kb
Host smart-9bb87d46-a7e9-4182-bc36-0e6e58c6cd19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78907925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.78907925
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2397138658
Short name T607
Test name
Test status
Simulation time 78869516983 ps
CPU time 6.33 seconds
Started Aug 13 06:01:26 PM PDT 24
Finished Aug 13 06:01:32 PM PDT 24
Peak memory 210520 kb
Host smart-1747da6b-eb20-45ca-a6d2-24ae9159656b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397138658 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2397138658
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2425468303
Short name T645
Test name
Test status
Simulation time 533418023 ps
CPU time 1 seconds
Started Aug 13 06:01:24 PM PDT 24
Finished Aug 13 06:01:25 PM PDT 24
Peak memory 201948 kb
Host smart-44d84beb-227c-4e04-ad96-259718d881fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425468303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2425468303
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2903174815
Short name T716
Test name
Test status
Simulation time 533496050519 ps
CPU time 941.32 seconds
Started Aug 13 06:01:26 PM PDT 24
Finished Aug 13 06:17:07 PM PDT 24
Peak memory 202036 kb
Host smart-5d3b0152-d2ca-4979-8099-8368372008e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903174815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2903174815
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2311271519
Short name T512
Test name
Test status
Simulation time 529585265879 ps
CPU time 351.12 seconds
Started Aug 13 06:01:24 PM PDT 24
Finished Aug 13 06:07:15 PM PDT 24
Peak memory 202152 kb
Host smart-1c248138-4cfe-4894-ba91-c19afb82b377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311271519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2311271519
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1367282223
Short name T285
Test name
Test status
Simulation time 331039802292 ps
CPU time 170 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:04:15 PM PDT 24
Peak memory 202160 kb
Host smart-d9410654-3c9f-4668-9c46-597a37f8117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367282223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1367282223
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3563729919
Short name T752
Test name
Test status
Simulation time 327634586622 ps
CPU time 755.66 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:14:01 PM PDT 24
Peak memory 202132 kb
Host smart-3eff9c46-12e1-44dc-845e-1d58539262be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563729919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3563729919
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2082175554
Short name T603
Test name
Test status
Simulation time 318006683469 ps
CPU time 681.81 seconds
Started Aug 13 06:01:28 PM PDT 24
Finished Aug 13 06:12:50 PM PDT 24
Peak memory 202044 kb
Host smart-fb428136-2972-4b69-ace3-818923a2035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082175554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2082175554
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2099277749
Short name T467
Test name
Test status
Simulation time 330864247705 ps
CPU time 303.73 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:06:29 PM PDT 24
Peak memory 202120 kb
Host smart-e08271ce-acb8-4c56-8b62-62849fbf1946
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099277749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2099277749
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1155308769
Short name T33
Test name
Test status
Simulation time 172096967239 ps
CPU time 182.29 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:04:28 PM PDT 24
Peak memory 202128 kb
Host smart-2b916031-5ab1-4989-86ee-6e62b1ee0af3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155308769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1155308769
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1435243135
Short name T187
Test name
Test status
Simulation time 203082887755 ps
CPU time 244.28 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:05:30 PM PDT 24
Peak memory 202108 kb
Host smart-926d4510-6cb0-40a0-945d-6c1ea77077c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435243135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1435243135
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.737693995
Short name T510
Test name
Test status
Simulation time 32469164284 ps
CPU time 72.97 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:02:38 PM PDT 24
Peak memory 201908 kb
Host smart-6307f995-0087-46ae-bdb4-4392309bb899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737693995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.737693995
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1478842049
Short name T437
Test name
Test status
Simulation time 4849275263 ps
CPU time 12.11 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:01:37 PM PDT 24
Peak memory 201972 kb
Host smart-a38b67e2-97ec-4251-83ac-2c7044031954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478842049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1478842049
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1947128277
Short name T674
Test name
Test status
Simulation time 5624034103 ps
CPU time 13.42 seconds
Started Aug 13 06:01:24 PM PDT 24
Finished Aug 13 06:01:38 PM PDT 24
Peak memory 201912 kb
Host smart-47ff1344-00f8-41b4-a4a5-5cde1c84dc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947128277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1947128277
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1150392148
Short name T560
Test name
Test status
Simulation time 549514830343 ps
CPU time 586.63 seconds
Started Aug 13 06:01:26 PM PDT 24
Finished Aug 13 06:11:12 PM PDT 24
Peak memory 202144 kb
Host smart-ab918be4-447d-4520-8721-dece23637428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150392148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1150392148
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.852884138
Short name T648
Test name
Test status
Simulation time 10919454415 ps
CPU time 19.68 seconds
Started Aug 13 06:01:27 PM PDT 24
Finished Aug 13 06:01:46 PM PDT 24
Peak memory 210784 kb
Host smart-632a5ad1-f92f-4a4b-ad0f-862f516c7727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852884138 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.852884138
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1060434134
Short name T366
Test name
Test status
Simulation time 415922960 ps
CPU time 0.73 seconds
Started Aug 13 06:01:34 PM PDT 24
Finished Aug 13 06:01:35 PM PDT 24
Peak memory 201896 kb
Host smart-182c0ee1-b1ed-4fc6-8617-e7b3fdb91b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060434134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1060434134
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.188924300
Short name T263
Test name
Test status
Simulation time 354954055074 ps
CPU time 225.32 seconds
Started Aug 13 06:01:35 PM PDT 24
Finished Aug 13 06:05:20 PM PDT 24
Peak memory 202092 kb
Host smart-fd2a905e-36df-4e3c-89e5-6faf2cbc6ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188924300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.188924300
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3590950861
Short name T255
Test name
Test status
Simulation time 164048391743 ps
CPU time 371.22 seconds
Started Aug 13 06:01:28 PM PDT 24
Finished Aug 13 06:07:39 PM PDT 24
Peak memory 202096 kb
Host smart-731722b4-512f-4caa-9e1a-1c288a401910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590950861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3590950861
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.488681650
Short name T470
Test name
Test status
Simulation time 493151149581 ps
CPU time 590.13 seconds
Started Aug 13 06:01:23 PM PDT 24
Finished Aug 13 06:11:13 PM PDT 24
Peak memory 202124 kb
Host smart-8210debe-af20-479a-a019-91d4f37934f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=488681650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.488681650
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4199343274
Short name T613
Test name
Test status
Simulation time 163412686325 ps
CPU time 180.3 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:04:25 PM PDT 24
Peak memory 202052 kb
Host smart-61ab2e19-07c1-41a2-a62e-8c504244b76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199343274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4199343274
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4078124813
Short name T478
Test name
Test status
Simulation time 164781470178 ps
CPU time 181.29 seconds
Started Aug 13 06:01:26 PM PDT 24
Finished Aug 13 06:04:27 PM PDT 24
Peak memory 202116 kb
Host smart-1d169b12-fac3-44b3-a46a-7aca44cdab81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078124813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.4078124813
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.4037018913
Short name T517
Test name
Test status
Simulation time 178821530104 ps
CPU time 363.33 seconds
Started Aug 13 06:01:23 PM PDT 24
Finished Aug 13 06:07:27 PM PDT 24
Peak memory 202064 kb
Host smart-3756c632-6509-48f2-86be-4cf7db0453c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037018913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.4037018913
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2253361435
Short name T451
Test name
Test status
Simulation time 201103236282 ps
CPU time 486.97 seconds
Started Aug 13 06:01:26 PM PDT 24
Finished Aug 13 06:09:33 PM PDT 24
Peak memory 202160 kb
Host smart-70f1fdcd-2eaf-43ab-980d-d2ad94dc308a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253361435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2253361435
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.554645590
Short name T792
Test name
Test status
Simulation time 84055436531 ps
CPU time 321.29 seconds
Started Aug 13 06:01:36 PM PDT 24
Finished Aug 13 06:06:58 PM PDT 24
Peak memory 202424 kb
Host smart-da47c05e-1835-4979-a2a5-76f77ee7d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554645590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.554645590
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2953930054
Short name T108
Test name
Test status
Simulation time 25919237820 ps
CPU time 14.9 seconds
Started Aug 13 06:01:34 PM PDT 24
Finished Aug 13 06:01:49 PM PDT 24
Peak memory 201968 kb
Host smart-3d86e2d4-3778-4203-95a6-114e1f492c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953930054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2953930054
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3043994770
Short name T412
Test name
Test status
Simulation time 3684754006 ps
CPU time 2.31 seconds
Started Aug 13 06:01:35 PM PDT 24
Finished Aug 13 06:01:37 PM PDT 24
Peak memory 201884 kb
Host smart-deeb11c7-f371-4424-bdc6-62c0586a971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043994770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3043994770
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1270855507
Short name T157
Test name
Test status
Simulation time 5741104337 ps
CPU time 4.05 seconds
Started Aug 13 06:01:25 PM PDT 24
Finished Aug 13 06:01:29 PM PDT 24
Peak memory 201976 kb
Host smart-4e2fcb7f-8a43-4780-8bac-c1b2abd3062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270855507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1270855507
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4192975780
Short name T42
Test name
Test status
Simulation time 13494203998 ps
CPU time 21.05 seconds
Started Aug 13 06:01:35 PM PDT 24
Finished Aug 13 06:01:56 PM PDT 24
Peak memory 217988 kb
Host smart-21691f37-c57b-4699-bc59-ef895a7a7156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192975780 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.4192975780
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%