Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5507	1			T2	10		T7	8		T9	43
testmodes[AdcCtrlTestmodeNormal]	4553	1			T1	1		T2	9		T3	3
testmodes[AdcCtrlTestmodeLowpower]	4761	1			T4	1		T8	1		T9	48
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2861	1			T2	4		T7	6		T9	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1386	1			T2	6		T7	2		T9	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1154	1			T9	12		T47	16		T58	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1371	1			T2	5		T7	1		T9	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1664	1			T2	3		T3	2		T5	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1166	1			T8	1		T9	14		T11	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1162	1			T9	13		T47	18		T58	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1166	1			T9	13		T47	13		T48	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2192	1			T9	22		T47	20		T48	1