Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19179

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3181

1

T6

9

T8

35

T11

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16582

1

T2

19

T6

22

T7

11

auto[1]

5778

1

T1

1

T3

28

T4

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T240	1		T241	1		-	-
values[0]	101	1			T242	9		T243	12		T244	33
values[1]	791	1			T4	28		T48	12		T57	4
values[2]	496	1			T8	35		T27	10		T30	3
values[3]	546	1			T57	1		T30	11		T60	30
values[4]	586	1			T6	22		T8	26		T12	7
values[5]	2865	1			T1	1		T3	28		T5	20
values[6]	492	1			T12	13		T68	2		T154	19
values[7]	591	1			T24	1		T27	8		T28	27
values[8]	815	1			T178	1		T153	1		T152	8
values[9]	1134	1			T6	9		T11	22		T24	1
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	891	1			T4	28		T48	12		T57	4
values[1]	559	1			T8	35		T30	3		T168	11
values[2]	589	1			T8	26		T12	7		T26	11
values[3]	2949	1			T1	1		T3	28		T5	20
values[4]	418	1			T56	20		T27	11		T68	2
values[5]	667	1			T12	13		T178	1		T27	8
values[6]	679	1			T24	1		T153	1		T152	1
values[7]	619	1			T6	9		T178	1		T152	8
values[8]	894	1			T11	22		T24	1		T29	15
values[9]	119	1			T245	9		T240	1		T182	4
minimum	13976	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T4	13		T57	2		T68	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T48	6		T175	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T30	1		T168	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	17		T100	1		T179	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	11		T26	11		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	1		T27	1		T60	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T1	1		T3	3		T5	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	8		T48	12		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T56	11		T189	1		T161	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T27	1		T68	1		T160	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T27	1		T28	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T178	1		T68	1		T154	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T24	1		T152	1		T156	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T153	1		T154	18		T155	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T178	1		T152	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	3		T158	1		T181	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	11		T29	15		T175	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T24	1		T155	1		T168	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T240	1		T182	1		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T245	9		T247	1		T248	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13852	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T249	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	15		T57	2		T68	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T48	6		T160	2		T45	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T30	2		T168	10		T250	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T8	18		T179	13		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	15		T30	10		T182	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	6		T27	9		T60	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T3	25		T5	18		T6	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	10		T167	13		T160	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T56	9		T161	11		T210	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T27	10		T68	1		T160	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	12		T27	7		T28	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T68	1		T154	10		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T161	5		T183	1		T187	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T154	15		T155	20		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T152	7		T252	2		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	6		T224	12		T254	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	11		T99	10		T61	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	1		T168	13		T53	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T182	3		T218	15		T187	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T247	1		T255	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T48	1		T14	1		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T249	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T240	1		T241	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T242	9		T243	12		T103	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T244	15		T185	1		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T4	13		T57	2		T68	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T48	6		T175	1		T45	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	1		T158	1		T253	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T8	17		T27	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T30	1		T168	1		T156	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T57	1		T60	14		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	12		T8	11		T26	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T48	8		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T1	1		T3	3		T5	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	8		T48	4		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	1		T96	1		T245	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T68	1		T154	9		T163	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T24	1		T27	1		T28	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T154	18		T155	21		T164	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T178	1		T152	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T153	1		T181	17		T162	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T11	11		T29	15		T175	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T6	3		T24	1		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T244	18		T256	4		T257	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	15		T57	2		T68	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	6		T45	2		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T30	2		T253	5		T223	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T8	18		T27	9		T160	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	10		T168	10		T250	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T60	16		T99	2		T258	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T6	10		T8	15		T172	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	6		T167	13		T160	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T3	25		T5	18		T10	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	10		T27	10		T68	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	12		T249	10		T259	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T68	1		T154	10		T260	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T27	7		T28	12		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T154	15		T155	20		T164	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T152	7		T252	2		T253	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T251	14		T250	9		T171	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	11		T99	10		T61	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	6		T155	1		T168	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T4	16		T57	3		T68	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T48	7		T175	1		T160	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T30	3		T168	11		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T8	19		T100	1		T179	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	16		T26	1		T30	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	7		T27	10		T60	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T1	1		T3	28		T5	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	11		T48	2		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T56	10		T189	1		T161	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T27	11		T68	2		T160	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	13		T27	8		T28	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T178	1		T68	2		T154	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T24	1		T152	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T153	1		T154	16		T155	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T178	1		T152	8		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	7		T158	1		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	12		T29	1		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T24	1		T155	2		T168	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T240	1		T182	4		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T245	1		T247	2		T248	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13955	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T249	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	12		T57	1		T68	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	5		T45	2		T164	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T41	19		T169	10		T210	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T8	16		T179	8		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	10		T26	10		T156	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T60	13		T261	6		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T6	11		T55	15		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	7		T48	10		T175	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T56	10		T161	5		T245	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T160	14		T163	17		T54	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	14		T29	9		T184	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T154	8		T164	9		T260	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T156	18		T161	8		T170	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T154	17		T155	20		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T181	10		T253	5		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	2		T181	16		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	10		T29	14		T175	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T168	12		T156	6		T193	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T218	15		T264	1		T213	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T245	8		T265	13		T255	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T173	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T240	1		T241	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T242	1		T243	1		T103	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T244	19		T185	1		T256	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	16		T57	3		T68	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	7		T175	1		T45	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T30	3		T158	1		T253	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T8	19		T27	10		T160	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	11		T168	11		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T57	1		T60	17		T99	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	11		T8	16		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	7		T48	1		T167	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T1	1		T3	28		T5	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	11		T48	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	13		T96	1		T245	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T68	2		T154	11		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T24	1		T27	8		T28	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T154	16		T155	21		T164	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T178	1		T152	8		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T153	1		T181	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T11	12		T29	1		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T6	7		T24	1		T155	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T242	8		T243	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T244	14		T257	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	12		T57	1		T68	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T48	5		T45	2		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T253	2		T34	4		T41	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T8	16		T15	1		T266	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T156	8		T184	9		T267	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T60	13		T16	1		T262	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T6	11		T8	10		T26	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T48	7		T175	5		T160	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T55	15		T56	10		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T11	7		T48	3		T160	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T245	9		T259	1		T184	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T154	8		T163	17		T260	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T28	14		T29	9		T156	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T154	17		T155	20		T164	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T253	5		T268	13		T269	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T181	16		T162	12		T169	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T11	10		T29	14		T175	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T6	2		T168	12		T156	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19326

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3034

1

T6

31

T8

26

T48

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16734

1

T2

19

T4

28

T6

9

auto[1]

5626

1

T1

1

T3

28

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T162	9		T99	11		T270	2
values[0]	44	1			T100	1		T180	13		T130	14
values[1]	550	1			T28	27		T29	1		T68	2
values[2]	486	1			T48	4		T178	1		T57	1
values[3]	588	1			T6	9		T12	7		T48	8
values[4]	3047	1			T1	1		T3	28		T5	20
values[5]	702	1			T8	35		T160	27		T157	5
values[6]	561	1			T24	1		T189	1		T156	19
values[7]	647	1			T6	22		T11	18		T12	13
values[8]	603	1			T24	1		T26	11		T30	5
values[9]	1164	1			T4	28		T8	26		T56	20
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	676	1			T28	27		T29	1		T68	2
values[1]	431	1			T6	9		T48	12		T57	1
values[2]	735	1			T12	7		T48	12		T178	1
values[3]	3010	1			T1	1		T3	28		T5	20
values[4]	729	1			T11	22		T24	1		T160	27
values[5]	533	1			T189	1		T156	19		T158	1
values[6]	594	1			T11	18		T12	13		T27	10
values[7]	665	1			T6	22		T24	1		T26	11
values[8]	856	1			T4	28		T8	26		T57	4
values[9]	172	1			T56	20		T30	3		T99	11
minimum	13959	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T28	15		T29	1		T156	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T68	1		T175	15		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T27	1		T161	9		T157	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	3		T48	12		T57	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T48	6		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T29	10		T167	1		T157	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T1	1		T3	3		T5	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T178	1		T154	18		T155	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	11		T24	1		T34	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T160	15		T41	15		T271	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T156	19		T258	1		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T189	1		T158	1		T163	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	8		T12	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T27	1		T156	7		T251	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T26	11		T27	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	12		T24	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	13		T57	2		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T8	11		T154	9		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T272	9		T211	1		T273	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T56	11		T30	1		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13840	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T28	12		T270	10		T274	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T68	1		T15	1		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T27	10		T161	5		T224	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T6	6		T155	1		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	6		T48	6		T168	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T167	13		T253	5		T99	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1100	1			T3	25		T5	18		T8	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T154	15		T155	20		T53	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	11		T171	11		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T160	12		T271	2		T194	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T258	4		T174	19		T184	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T172	5		T210	13		T263	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	10		T12	12		T30	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	9		T251	14		T275	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T27	7		T161	11		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T6	10		T221	10		T276	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	15		T57	2		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	15		T154	10		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T272	8		T273	6		T277	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T56	9		T30	2		T99	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T48	1		T14	1		T82	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T270	1		T23	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T162	9		T99	1		T254	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T100	1		T180	1		T278	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T130	1		T279	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T28	15		T29	1		T181	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T68	1		T175	15		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T178	1		T27	1		T156	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T48	4		T57	1		T29	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T168	1		T157	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	3		T48	8		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T1	1		T3	3		T5	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T178	1		T167	1		T154	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	17		T157	5		T34	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T160	15		T49	1		T41	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T24	1		T156	19		T258	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T189	1		T158	1		T163	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	8		T12	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	12		T27	1		T156	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	11		T30	1		T68	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	1		T162	13		T275	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T4	13		T57	2		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T8	11		T56	11		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T270	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T99	10		T254	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T180	12		T278	4		T280	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T130	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T28	12		T270	10		T274	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T68	1		T15	1		T173	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T27	10		T161	5		T183	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T155	1		T281	35		T182	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T12	6		T168	10		T224	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	6		T164	4		T253	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T3	25		T5	18		T10	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T167	13		T154	15		T155	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	18		T250	10		T223	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T160	12		T271	2		T194	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T258	4		T171	11		T174	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T172	5		T282	11		T244	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	10		T12	12		T152	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	10		T27	9		T251	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	4		T68	19		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T275	12		T221	10		T283	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	15		T57	2		T27	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T8	15		T56	9		T30	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2