Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19177

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3183

1

T4

28

T6

9

T8

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16449

1

T2

19

T6

31

T7

11

auto[1]

5911

1

T1

1

T3

28

T4

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	316	1			T24	1		T168	26		T162	13
values[0]	24	1			T11	22		T152	1		T254	1
values[1]	651	1			T6	22		T24	1		T30	5
values[2]	662	1			T48	4		T26	11		T27	10
values[3]	645	1			T8	35		T11	18		T57	4
values[4]	624	1			T6	9		T30	11		T175	6
values[5]	2965	1			T1	1		T3	28		T5	20
values[6]	403	1			T27	11		T29	15		T160	3
values[7]	631	1			T8	26		T48	12		T167	14
values[8]	562	1			T56	20		T27	8		T152	8
values[9]	936	1			T4	28		T12	13		T48	8
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	648	1			T6	22		T11	22		T48	4
values[1]	629	1			T27	10		T29	1		T68	44
values[2]	738	1			T6	9		T8	35		T11	18
values[3]	3008	1			T1	1		T3	28		T5	20
values[4]	482	1			T12	7		T168	11		T189	1
values[5]	410	1			T48	12		T27	11		T29	15
values[6]	726	1			T8	26		T56	20		T167	14
values[7]	495	1			T27	8		T152	8		T155	41
values[8]	897	1			T4	28		T12	13		T48	8
values[9]	217	1			T168	26		T162	13		T179	22
minimum	14110	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	12		T48	4		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	11		T162	13		T253	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	1		T68	1		T175	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T27	1		T68	23		T189	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	17		T11	8		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T6	3		T57	2		T28	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T1	1		T3	3		T5	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T175	6		T160	17		T157	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T168	1		T189	1		T156	35
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T12	1		T158	1		T281	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T48	6		T29	15		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T27	1		T175	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T56	11		T167	1		T60	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	11		T155	1		T161	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T27	1		T152	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T155	21		T161	9		T41	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T48	8		T178	1		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	13		T12	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T162	13		T281	24		T174	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T168	13		T179	9		T336	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13889	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T152	1		T252	1		T95	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	10		T30	4		T160	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	11		T253	5		T194	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T68	1		T164	9		T253	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T27	9		T68	19		T222	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	18		T11	10		T99	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	6		T57	2		T28	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T3	25		T5	18		T10	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T160	14		T45	2		T200	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T168	10		T184	12		T211	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T12	6		T281	1		T301	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T48	6		T251	14		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T27	10		T160	2		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T56	9		T167	13		T60	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	15		T155	1		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T27	7		T152	7		T52	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T155	20		T161	5		T272	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T68	1		T258	4		T250	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	15		T12	12		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T281	22		T174	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T168	13		T179	13		T125	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T48	1		T14	1		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T252	2		T187	12		T103	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T24	1		T162	13		T170	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T168	13		T179	9		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T254	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T11	11		T152	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	12		T24	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T162	13		T252	1		T253	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T48	4		T26	11		T68	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T27	1		T68	23		T222	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	17		T11	8		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T57	2		T28	15		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	1		T189	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	3		T175	6		T157	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T1	1		T3	3		T5	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	1		T160	17		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	15		T156	19		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T27	1		T160	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	6		T167	1		T154	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	11		T175	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T56	11		T27	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T155	21		T96	1		T41	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T48	8		T178	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	13		T12	1		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T281	22		T174	13		T263	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T168	13		T179	13		T250	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T11	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	10		T30	4		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T252	2		T253	5		T194	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T68	1		T164	9		T253	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T27	9		T68	19		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	18		T11	10		T99	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T57	2		T28	12		T262	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T30	10		T250	9		T171	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	6		T45	2		T200	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T3	25		T5	18		T10	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	6		T160	14		T281	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T251	14		T15	1		T275	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T27	10		T160	2		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	6		T167	13		T154	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	15		T155	1		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T56	9		T27	7		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T155	20		T194	4		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T68	1		T258	4		T52	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	15		T12	12		T30	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	11		T48	1		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	12		T162	1		T253	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T29	1		T68	2		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T27	10		T68	20		T189	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	19		T11	11		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	7		T57	3		T28	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T1	1		T3	28		T5	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T175	1		T160	15		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T168	11		T189	1		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	7		T158	1		T281	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T48	7		T29	1		T251	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T27	11		T175	1		T160	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T56	10		T167	14		T60	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	16		T155	2		T161	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T27	8		T152	8		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T155	21		T161	6		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T48	1		T178	1		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T4	16		T12	13		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T162	1		T281	23		T174	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T168	14		T179	14		T336	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13997	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T152	1		T252	3		T95	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	11		T48	3		T26	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	10		T162	12		T253	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T175	14		T164	9		T253	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T68	22		T163	17		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T8	16		T11	7		T254	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	2		T57	1		T28	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T55	15		T29	9		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T175	5		T160	16		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T156	32		T245	8		T184	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T210	10		T243	18		T296	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T48	5		T29	14		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T41	19		T284	8		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T56	10		T60	13		T154	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	10		T161	5		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T245	8		T52	2		T53	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T155	20		T161	8		T41	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T48	7		T170	11		T261	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	12		T154	8		T157	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T162	12		T281	23		T174	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T168	12		T179	8		T312	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T281	10		T337	11		T313	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T338	7		T43	6		T327	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T24	1		T162	1		T170	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T168	14		T179	14		T250	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T254	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T11	12		T152	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	11		T24	1		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T162	1		T252	3		T253	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	1		T26	1		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T27	10		T68	20		T222	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	19		T11	11		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T57	3		T28	13		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	11		T189	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	7		T175	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T1	1		T3	28		T5	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	7		T160	15		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T29	1		T156	1		T251	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T27	11		T160	3		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	7		T167	14		T154	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	16		T175	1		T155	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T56	10		T27	8		T152	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T155	21		T96	1		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T48	1		T178	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T4	16		T12	13		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T162	12		T170	11		T281	23
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T168	12		T179	8		T172	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T11	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	11		T160	14		T253	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T162	12		T253	2		T298	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T48	3		T26	10		T175	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T68	22		T222	9		T184	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T8	16		T11	7		T304	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T57	1		T28	14		T163	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T181	16		T171	5		T254	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	2		T175	5		T157	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T55	15		T29	9		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T160	16		T210	10		T243	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T29	14		T156	18		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T41	19		T16	1		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T48	5		T154	17		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	10		T161	5		T157	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T56	10		T60	13		T164	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T155	20		T41	14		T169	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T48	7		T261	6		T52	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	12		T154	8		T161	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26