Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19133

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3227

1

T4

28

T6

31

T8

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16832

1

T2

19

T4

28

T7

11

auto[1]

5528

1

T1

1

T3

28

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	242	1			T178	1		T156	9		T163	18
values[0]	20	1			T43	14		T285	5		T303	1
values[1]	688	1			T11	18		T48	4		T168	11
values[2]	518	1			T8	35		T12	7		T48	8
values[3]	658	1			T29	1		T68	42		T152	1
values[4]	563	1			T11	22		T48	12		T26	11
values[5]	627	1			T4	28		T12	13		T57	1
values[6]	565	1			T8	26		T29	10		T68	2
values[7]	579	1			T6	22		T56	20		T57	4
values[8]	788	1			T178	1		T30	11		T154	33
values[9]	3171	1			T1	1		T3	28		T5	20
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	612	1			T11	18		T12	7		T48	4
values[1]	610	1			T8	35		T48	8		T27	10
values[2]	607	1			T48	12		T29	1		T189	1
values[3]	579	1			T11	22		T24	1		T26	11
values[4]	568	1			T4	28		T12	13		T57	1
values[5]	562	1			T8	26		T56	20		T29	10
values[6]	3023	1			T1	1		T3	28		T5	20
values[7]	714	1			T178	1		T29	15		T155	2
values[8]	805	1			T6	9		T178	1		T30	3
values[9]	107	1			T163	18		T95	1		T100	1
minimum	14173	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	8		T12	1		T161	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T48	4		T157	3		T41	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	17		T48	8		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T27	1		T152	1		T301	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	6		T160	17		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	1		T189	1		T156	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T26	11		T175	22		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	11		T24	1		T28	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	1		T68	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	13		T57	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T153	1		T152	1		T156	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	11		T56	11		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T1	1		T3	3		T5	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	12		T24	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T29	15		T155	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T178	1		T168	13		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T30	1		T167	1		T156	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	3		T178	1		T154	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T100	1		T170	13		T210	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T163	18		T95	1		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13909	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T172	8		T185	1		T186	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T11	10		T12	6		T161	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T270	10		T249	7		T174	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	18		T30	4		T68	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T27	9		T301	11		T249	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T48	6		T160	14		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T164	9		T258	4		T250	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T171	7		T254	14		T304	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T11	11		T28	12		T253	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T12	12		T68	1		T252	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	15		T27	10		T68	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T152	7		T45	2		T99	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	15		T56	9		T179	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T3	25		T5	18		T10	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	10		T27	7		T60	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T155	1		T160	2		T194	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T168	13		T160	12		T183	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	2		T167	13		T275	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	6		T154	10		T171	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T210	13		T316	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T271	2		T104	9		T305	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	1		T14	1		T168	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T172	5		T283	7		T339	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T156	9		T275	13		T250	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T178	1		T163	18		T281	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T43	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T285	5		T303	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	8		T168	1		T161	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T48	4		T157	3		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	17		T12	1		T48	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T27	1		T41	16		T301	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T68	23		T155	21		T164	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	1		T152	1		T162	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T48	6		T26	11		T175	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	11		T28	15		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	1		T175	1		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	13		T57	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T68	1		T152	1		T156	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	11		T29	10		T157	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T57	2		T153	1		T45	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	12		T56	11		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T30	1		T155	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T178	1		T154	18		T168	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1658	1			T1	1		T3	3		T5	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	3		T154	9		T160	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T275	12		T250	11		T210	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T281	1		T340	14		T319	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T43	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	10		T168	10		T161	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T172	5		T249	7		T174	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T8	18		T12	6		T30	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T27	9		T301	11		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T68	19		T155	20		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T164	9		T250	9		T194	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T48	6		T160	14		T251	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T11	11		T28	12		T253	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T12	12		T99	2		T173	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	15		T27	10		T68	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T68	1		T152	7		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	15		T179	13		T282	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T57	2		T45	2		T182	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	10		T56	9		T27	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	10		T155	1		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T154	15		T168	13		T173	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T3	25		T5	18		T10	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	6		T154	10		T160	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	11		T12	7		T161	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	1		T157	1		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	19		T48	1		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T27	10		T152	1		T301	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	7		T160	15		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T29	1		T189	1		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T26	1		T175	3		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	12		T24	1		T28	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	13		T68	2		T252	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	16		T57	1		T27	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	1		T152	8		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	16		T56	10		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T1	1		T3	28		T5	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	11		T24	1		T27	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T29	1		T155	2		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T178	1		T168	14		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T30	3		T167	14		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	7		T178	1		T154	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T100	1		T170	1		T210	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T163	1		T95	1		T271	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14030	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T172	6		T185	1		T186	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T11	7		T161	5		T162	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	3		T157	2		T41	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	16		T48	7		T68	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T259	1		T263	11		T244	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	5		T160	16		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T156	18		T162	24		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	10		T175	19		T171	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	10		T28	14		T253	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T242	8		T54	1		T218	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	12		T253	5		T284	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T156	6		T45	2		T41	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	10		T56	10		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T55	15		T57	1		T32	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	11		T60	13		T154	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	14		T245	9		T174	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T168	12		T160	14		T157	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T156	8		T275	12		T200	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	2		T154	8		T171	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T170	12		T210	10		T316	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T163	17		T104	9		T305	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T161	8		T263	9		T296	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T172	7		T283	10		T307	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T156	1		T275	13		T250	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T178	1		T163	1		T281	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T43	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T285	1		T303	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	11		T168	11		T161	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T48	1		T157	1		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	19		T12	7		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	10		T41	1		T301	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T68	20		T155	21		T164	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T29	1		T152	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	7		T26	1		T175	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	12		T28	13		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	13		T175	1		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	16		T57	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T68	2		T152	8		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	16		T29	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T57	3		T153	1		T45	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	11		T56	10		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	11		T155	2		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T178	1		T154	16		T168	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1470	1			T1	1		T3	28		T5	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	7		T154	11		T160	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T156	8		T275	12		T210	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T163	17		T319	5		T19	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T43	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T285	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	7		T161	8		T162	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T48	3		T157	2		T245	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T8	16		T48	7		T161	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T41	15		T259	1		T244	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T68	22		T155	20		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T162	12		T164	9		T169	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	5		T26	10		T175	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T11	10		T28	14		T156	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T242	8		T54	1		T254	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	12		T253	7		T193	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T156	6		T41	14		T222	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	10		T29	9		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T57	1		T45	2		T169	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	11		T56	10		T60	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T245	9		T174	19		T184	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T154	17		T168	12		T157	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T55	15		T29	14		T32	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	2		T154	8		T160	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26