Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19185

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3175

1

T6

9

T8

35

T11

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16608

1

T2

19

T6

22

T7

11

auto[1]

5752

1

T1

1

T3

28

T4

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	237	1			T155	2		T168	26		T189	1
values[0]	75	1			T173	27		T304	15		T243	12
values[1]	787	1			T4	28		T48	12		T57	4
values[2]	515	1			T8	35		T30	3		T160	3
values[3]	607	1			T8	26		T27	10		T30	11
values[4]	554	1			T6	22		T12	7		T48	8
values[5]	2843	1			T1	1		T3	28		T5	20
values[6]	560	1			T12	13		T178	1		T27	8
values[7]	528	1			T24	1		T29	10		T152	1
values[8]	806	1			T178	1		T153	1		T152	8
values[9]	907	1			T6	9		T11	22		T24	1
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	700	1			T4	28		T48	12		T57	4
values[1]	518	1			T8	35		T30	3		T168	11
values[2]	582	1			T8	26		T12	7		T57	1
values[3]	2938	1			T1	1		T3	28		T5	20
values[4]	420	1			T11	18		T56	20		T27	11
values[5]	693	1			T12	13		T178	1		T27	8
values[6]	575	1			T24	1		T153	1		T152	1
values[7]	662	1			T6	9		T178	1		T152	8
values[8]	971	1			T11	22		T24	1		T29	15
values[9]	81	1			T193	10		T245	9		T182	4
minimum	14220	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	13		T57	2		T189	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	6		T175	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T30	1		T168	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	17		T100	1		T179	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	11		T26	11		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	1		T57	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1618	1			T1	1		T3	3		T5	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T48	12		T167	1		T175	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T56	11		T189	1		T161	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	8		T27	1		T68	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T27	1		T28	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T178	1		T68	1		T154	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T24	1		T152	1		T156	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T153	1		T154	18		T155	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T178	1		T152	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	3		T181	17		T162	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T11	11		T29	15		T175	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T24	1		T155	1		T168	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T182	1		T246	1		T341	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T193	10		T245	9		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13933	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T45	4		T342	1		T343	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	15		T57	2		T253	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	6		T160	2		T164	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T30	2		T168	10		T250	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T8	18		T179	13		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	15		T30	10		T301	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	6		T27	9		T60	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T3	25		T5	18		T6	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T167	13		T160	14		T171	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T56	9		T161	11		T210	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T11	10		T27	10		T68	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	12		T27	7		T28	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T68	1		T154	10		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T161	5		T183	1		T187	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T154	15		T155	20		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T152	7		T252	2		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	6		T200	10		T224	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	11		T99	10		T61	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T155	1		T168	13		T53	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T182	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T255	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T48	1		T14	1		T68	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T45	2		T343	12		T344	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T99	1		T52	6		T246	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T155	1		T168	13		T189	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T173	14		T304	7		T243	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T256	1		T345	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	13		T57	2		T68	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	6		T175	1		T45	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	1		T158	1		T253	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	17		T160	1		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	11		T30	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T27	1		T60	14		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	12		T26	11		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	1		T48	8		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T1	1		T3	3		T5	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	8		T48	4		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T27	1		T28	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T178	1		T68	1		T154	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T24	1		T29	10		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T154	18		T155	21		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T178	1		T152	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T153	1		T181	17		T162	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	11		T29	15		T175	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	3		T24	1		T156	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T99	10		T52	2		T122	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T155	1		T168	13		T173	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T173	13		T304	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T256	4		T345	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	15		T57	2		T68	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T48	6		T45	2		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T30	2		T253	5		T223	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T8	18		T160	2		T179	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	15		T30	10		T168	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T27	9		T60	16		T99	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T6	10		T30	4		T172	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	6		T167	13		T160	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T3	25		T5	18		T10	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	10		T27	10		T68	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	12		T27	7		T28	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T68	1		T154	10		T164	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T161	5		T194	4		T340	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T154	15		T155	20		T251	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T152	7		T252	2		T253	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T250	9		T171	11		T281	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	11		T61	10		T180	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	6		T53	2		T223	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	16		T57	3		T189	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	7		T175	1		T160	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	3		T168	11		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	19		T100	1		T179	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	16		T26	1		T30	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	7		T57	1		T27	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T1	1		T3	28		T5	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	2		T167	14		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T56	10		T189	1		T161	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	11		T27	11		T68	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	13		T27	8		T28	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T178	1		T68	2		T154	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T24	1		T152	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T153	1		T154	16		T155	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T178	1		T152	8		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	7		T181	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T11	12		T29	1		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T24	1		T155	2		T168	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T182	4		T246	1		T341	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T193	1		T245	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14019	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T45	4		T342	1		T343	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	12		T57	1		T162	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	5		T164	4		T222	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T41	4		T169	10		T210	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	16		T179	8		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	10		T26	10		T156	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T60	13		T261	6		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T6	11		T55	15		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T48	10		T175	5		T160	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T56	10		T161	5		T210	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T11	7		T160	14		T54	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T28	14		T29	9		T170	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T154	8		T163	17		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T156	18		T161	8		T269	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T154	17		T155	20		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T181	10		T253	5		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	2		T181	16		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	10		T29	14		T175	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T168	12		T156	6		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T264	1		T213	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T193	9		T245	8		T265	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T68	22		T173	13		T304	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T45	2		T204	9		T346	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T99	11		T52	6		T246	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T155	2		T168	14		T189	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T173	14		T304	9		T243	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T256	5		T345	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	16		T57	3		T68	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	7		T175	1		T45	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T30	3		T158	1		T253	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T8	19		T160	3		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	16		T30	11		T168	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T27	10		T60	17		T99	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	11		T26	1		T30	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	7		T48	1		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T1	1		T3	28		T5	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	11		T48	1		T27	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	13		T27	8		T28	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T178	1		T68	2		T154	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T24	1		T29	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T154	16		T155	21		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T178	1		T152	8		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T153	1		T181	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	12		T29	1		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T6	7		T24	1		T156	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T52	2		T122	14		T44	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T168	12		T193	9		T347	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T173	13		T304	6		T243	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	12		T57	1		T68	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	5		T45	2		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T253	2		T41	19		T169	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T8	16		T179	8		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T8	10		T156	8		T34	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T60	13		T262	13		T319	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	11		T26	10		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T48	7		T175	5		T160	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T55	15		T56	10		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	7		T48	3		T160	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T28	14		T245	9		T259	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T154	8		T163	17		T164	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T29	9		T156	18		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T154	17		T155	20		T281	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T253	5		T269	12		T348	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T181	16		T162	12		T41	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	10		T29	14		T175	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	2		T156	6		T170	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26