Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19323

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3037

1

T6

31

T8

26

T48

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16776

1

T2

19

T4

28

T6

9

auto[1]

5584

1

T1

1

T3

28

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	265	1			T4	28		T100	1		T179	22
values[0]	41	1			T180	13		T349	1		T350	27
values[1]	547	1			T28	27		T29	1		T68	2
values[2]	428	1			T48	4		T178	1		T57	1
values[3]	689	1			T6	9		T12	7		T48	20
values[4]	3006	1			T1	1		T3	28		T5	20
values[5]	692	1			T8	35		T160	27		T49	1
values[6]	586	1			T24	1		T189	1		T158	1
values[7]	616	1			T6	22		T11	18		T12	13
values[8]	645	1			T24	1		T26	11		T30	5
values[9]	904	1			T8	26		T56	20		T57	4
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	518	1			T28	27		T29	1		T68	2
values[1]	459	1			T6	9		T12	7		T48	12
values[2]	732	1			T48	12		T29	10		T167	14
values[3]	2969	1			T1	1		T3	28		T5	20
values[4]	763	1			T8	35		T11	22		T24	1
values[5]	555	1			T189	1		T156	19		T158	1
values[6]	699	1			T6	22		T11	18		T12	13
values[7]	539	1			T24	1		T26	11		T27	8
values[8]	906	1			T4	28		T8	26		T57	4
values[9]	112	1			T56	20		T179	22		T169	16
minimum	14108	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T28	15		T29	1		T156	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T68	1		T175	15		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	1		T178	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	3		T48	12		T57	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	6		T175	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T29	10		T167	1		T157	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T1	1		T3	3		T5	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T178	1		T154	18		T155	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	17		T11	11		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T160	15		T41	15		T271	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T156	19		T171	14		T174	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T189	1		T158	1		T163	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	8		T12	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	12		T27	1		T156	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	11		T27	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T24	1		T152	1		T162	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	13		T57	2		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	11		T30	1		T154	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T273	7		T285	6		T265	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T56	11		T179	9		T169	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13852	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T161	1		T214	1		T289	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T28	12		T270	10		T274	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T68	1		T15	1		T173	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T12	6		T27	10		T161	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T6	6		T155	1		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T48	6		T168	10		T171	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T167	13		T253	5		T99	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T3	25		T5	18		T10	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T154	15		T155	20		T53	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	18		T11	11		T68	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T160	12		T271	2		T194	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T171	11		T174	19		T211	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T172	5		T210	13		T282	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	10		T12	12		T30	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	10		T27	9		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T27	7		T161	11		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T200	10		T221	10		T283	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	15		T57	2		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	15		T30	2		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T273	6		T351	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T56	9		T179	13		T345	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	1		T14	1		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T214	7		T289	10		T17	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T4	13		T50	1		T352	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T100	1		T179	9		T169	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T180	1		T349	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T350	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T28	15		T29	1		T156	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T68	1		T175	15		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T178	1		T27	1		T161	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T48	4		T57	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	1		T48	6		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	3		T48	8		T29	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T1	1		T3	3		T5	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T178	1		T167	1		T154	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	17		T34	5		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T160	15		T49	1		T41	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	1		T258	1		T171	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T189	1		T158	1		T163	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	8		T12	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	12		T27	1		T156	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T26	11		T30	1		T68	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T24	1		T162	13		T275	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T57	2		T27	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T8	11		T56	11		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T4	15		T270	1		T311	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T179	13		T254	1		T187	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T180	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T350	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T28	12		T270	10		T274	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T68	1		T15	1		T173	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T27	10		T161	5		T183	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T155	1		T164	4		T281	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	6		T48	6		T168	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	6		T253	5		T99	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T3	25		T5	18		T10	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T167	13		T154	15		T155	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	18		T250	10		T223	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T160	12		T271	2		T194	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T258	4		T171	11		T174	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T172	5		T282	11		T244	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	10		T12	12		T152	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	10		T27	9		T251	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T30	4		T68	19		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T275	12		T221	10		T283	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T57	2		T27	7		T30	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	15		T56	9		T30	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T28	13		T29	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T68	2		T175	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	7		T178	1		T27	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	7		T48	2		T57	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T48	7		T175	1		T168	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T29	1		T167	14		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T1	1		T3	28		T5	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T178	1		T154	16		T155	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	19		T11	12		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T160	13		T41	1		T271	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T156	1		T171	12		T174	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T189	1		T158	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	11		T12	13		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	11		T27	10		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	1		T27	8		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T24	1		T152	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T4	16		T57	3		T30	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	16		T30	3		T154	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T273	7		T285	1		T265	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T56	10		T179	14		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13992	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T161	1		T214	8		T289	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T28	14		T156	8		T181	26
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T175	14		T15	1		T245	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T161	8		T157	2		T162	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	2		T48	10		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	5		T170	12		T171	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T29	9		T157	11		T253	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T55	15		T29	14		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T154	17		T155	20		T170	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	16		T11	10		T34	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T160	14		T41	14		T193	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T156	18		T171	13		T174	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T163	17		T172	7		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	7		T68	22		T175	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T6	11		T156	6		T275	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T26	10		T161	5		T222	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T162	12		T245	8		T200	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	12		T57	1		T160	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	10		T154	8		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T273	6		T285	5		T265	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T56	10		T179	8		T169	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T213	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T289	14		T17	2		T312	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T4	16		T50	1		T352	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T100	1		T179	14		T169	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T180	13		T349	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T350	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T28	13		T29	1		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T68	2		T175	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T178	1		T27	11		T161	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T48	1		T57	1		T155	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	7		T48	7		T168	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	7		T48	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T1	1		T3	28		T5	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T178	1		T167	14		T154	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T8	19		T34	1		T250	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T160	13		T49	1		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T24	1		T258	5		T171	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T189	1		T158	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	11		T12	13		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	11		T27	10		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T26	1		T30	5		T68	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	1		T162	1		T275	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T57	3		T27	8		T30	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	16		T56	10		T30	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T4	12		T353	5		T354	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T179	8		T169	15		T297	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T350	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T28	14		T156	8		T181	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T175	14		T15	1		T245	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T161	8		T162	12		T243	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T48	3		T164	4		T281	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	5		T157	2		T170	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	2		T48	7		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T11	10		T55	15		T29	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T154	17		T155	20		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	16		T34	4		T304	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T160	14		T41	14		T193	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T171	13		T174	19		T218	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T163	17		T172	7		T282	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	7		T175	5		T156	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T6	11		T156	6		T284	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T26	10		T68	22		T161	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T162	12		T275	12		T245	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T57	1		T160	16		T253	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	10		T56	10		T154	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26