CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22360 | 1 | T1 | 1 | T2 | 19 | T3 | 28 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 19195 | 1 | T1 | 1 | T2 | 19 | T3 | 28 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3165 | 1 | T6 | 22 | T8 | 26 | T11 | 40 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16702 | 1 | T2 | 19 | T7 | 11 | T8 | 26 | ||||
auto[1] | 5658 | 1 | T1 | 1 | T3 | 28 | T4 | 28 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18666 | 1 | T1 | 1 | T2 | 19 | T3 | 3 | ||||
auto[1] | 3694 | 1 | T3 | 25 | T4 | 15 | T5 | 18 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 286 | 1 | T56 | 20 | T57 | 4 | T27 | 8 | ||||
values[0] | 67 | 1 | T175 | 15 | T162 | 9 | T247 | 2 | ||||
values[1] | 740 | 1 | T48 | 12 | T29 | 16 | T68 | 42 | ||||
values[2] | 547 | 1 | T12 | 13 | T57 | 1 | T24 | 2 | ||||
values[3] | 478 | 1 | T189 | 1 | T161 | 14 | T158 | 1 | ||||
values[4] | 604 | 1 | T4 | 28 | T27 | 10 | T152 | 1 | ||||
values[5] | 609 | 1 | T6 | 22 | T30 | 3 | T175 | 6 | ||||
values[6] | 676 | 1 | T178 | 1 | T68 | 2 | T154 | 19 | ||||
values[7] | 656 | 1 | T48 | 4 | T27 | 11 | T30 | 5 | ||||
values[8] | 2844 | 1 | T1 | 1 | T3 | 28 | T5 | 20 | ||||
values[9] | 912 | 1 | T6 | 9 | T8 | 61 | T11 | 22 | ||||
minimum | 13941 | 1 | T2 | 19 | T7 | 11 | T9 | 131 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 775 | 1 | T48 | 12 | T29 | 26 | T68 | 42 | ||||
values[1] | 546 | 1 | T12 | 13 | T57 | 1 | T24 | 2 | ||||
values[2] | 528 | 1 | T4 | 28 | T189 | 1 | T160 | 31 | ||||
values[3] | 504 | 1 | T27 | 10 | T152 | 1 | T189 | 1 | ||||
values[4] | 730 | 1 | T6 | 22 | T30 | 3 | T175 | 6 | ||||
values[5] | 579 | 1 | T178 | 1 | T68 | 2 | T154 | 19 | ||||
values[6] | 3026 | 1 | T1 | 1 | T3 | 28 | T5 | 20 | ||||
values[7] | 499 | 1 | T178 | 1 | T26 | 11 | T30 | 11 | ||||
values[8] | 889 | 1 | T6 | 9 | T8 | 35 | T11 | 22 | ||||
values[9] | 171 | 1 | T8 | 26 | T56 | 20 | T57 | 4 | ||||
minimum | 14113 | 1 | T2 | 19 | T7 | 11 | T9 | 131 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18515 | 1 | T1 | 1 | T2 | 19 | T3 | 28 | ||||
auto[1] | 3845 | 1 | T4 | 12 | T6 | 13 | T8 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 194 | 1 | T48 | 6 | T29 | 26 | T46 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 279 | 1 | T68 | 23 | T168 | 13 | T160 | 15 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 149 | 1 | T12 | 1 | T57 | 1 | T24 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 134 | 1 | T24 | 1 | T175 | 1 | T60 | 14 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 178 | 1 | T4 | 13 | T161 | 9 | T157 | 12 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 129 | 1 | T189 | 1 | T160 | 17 | T162 | 13 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 84 | 1 | T27 | 1 | T152 | 1 | T189 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 183 | 1 | T164 | 5 | T253 | 6 | T96 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 296 | 1 | T30 | 1 | T175 | 6 | T156 | 19 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 151 | 1 | T6 | 12 | T164 | 10 | T193 | 10 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 100 | 1 | T155 | 1 | T168 | 1 | T156 | 7 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 222 | 1 | T178 | 1 | T68 | 1 | T154 | 9 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1626 | 1 | T1 | 1 | T3 | 3 | T5 | 2 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 160 | 1 | T11 | 8 | T27 | 1 | T167 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 102 | 1 | T30 | 1 | T152 | 1 | T253 | 3 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T178 | 1 | T26 | 11 | T252 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 265 | 1 | T6 | 3 | T8 | 17 | T12 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 230 | 1 | T11 | 11 | T48 | 8 | T27 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 62 | 1 | T56 | 11 | T57 | 2 | T155 | 21 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 39 | 1 | T8 | 11 | T41 | 15 | T338 | 8 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 13896 | 1 | T2 | 19 | T7 | 11 | T9 | 131 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 35 | 1 | T289 | 15 | T247 | 1 | T225 | 1 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 105 | 1 | T48 | 6 | T15 | 1 | T271 | 2 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 197 | 1 | T68 | 19 | T168 | 13 | T160 | 12 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T12 | 12 | T210 | 13 | T249 | 10 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 111 | 1 | T60 | 16 | T154 | 15 | T222 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 127 | 1 | T4 | 15 | T161 | 5 | T45 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 94 | 1 | T160 | 14 | T180 | 12 | T171 | 7 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 51 | 1 | T27 | 9 | T274 | 11 | T310 | 15 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 186 | 1 | T164 | 4 | T253 | 10 | T194 | 4 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 144 | 1 | T30 | 2 | T161 | 11 | T171 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 139 | 1 | T6 | 10 | T164 | 9 | T301 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 105 | 1 | T155 | 1 | T168 | 10 | T99 | 2 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T68 | 1 | T154 | 10 | T160 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1065 | 1 | T3 | 25 | T5 | 18 | T10 | 23 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T11 | 10 | T27 | 10 | T167 | 13 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 124 | 1 | T30 | 10 | T152 | 7 | T253 | 5 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 121 | 1 | T252 | 2 | T99 | 10 | T274 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 171 | 1 | T6 | 6 | T8 | 18 | T12 | 6 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 223 | 1 | T11 | 11 | T27 | 7 | T253 | 5 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 42 | 1 | T56 | 9 | T57 | 2 | T155 | 20 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 28 | 1 | T8 | 15 | T315 | 9 | T264 | 4 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 157 | 1 | T48 | 1 | T14 | 1 | T82 | 2 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 25 | 1 | T289 | 10 | T247 | 1 | T266 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 2 | 46 | 95.83 | 2 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | -- | -- | 2 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 127 | 1 | T56 | 11 | T57 | 2 | T28 | 15 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 59 | 1 | T27 | 1 | T41 | 15 | T249 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 36 | 1 | T175 | 15 | T162 | 9 | T318 | 12 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 12 | 1 | T247 | 1 | T225 | 1 | T316 | 9 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 168 | 1 | T48 | 6 | T29 | 16 | T46 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 271 | 1 | T68 | 23 | T168 | 13 | T160 | 15 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 135 | 1 | T12 | 1 | T57 | 1 | T24 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 127 | 1 | T24 | 1 | T175 | 1 | T60 | 14 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 189 | 1 | T161 | 9 | T158 | 1 | T181 | 17 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 108 | 1 | T189 | 1 | T162 | 13 | T242 | 9 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 119 | 1 | T4 | 13 | T27 | 1 | T152 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 210 | 1 | T160 | 17 | T164 | 5 | T253 | 6 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 235 | 1 | T30 | 1 | T175 | 6 | T156 | 19 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 133 | 1 | T6 | 12 | T164 | 10 | T169 | 16 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 149 | 1 | T168 | 1 | T156 | 7 | T181 | 11 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 235 | 1 | T178 | 1 | T68 | 1 | T154 | 9 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 192 | 1 | T48 | 4 | T30 | 1 | T68 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 182 | 1 | T27 | 1 | T167 | 1 | T40 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 1557 | 1 | T1 | 1 | T3 | 3 | T5 | 2 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 108 | 1 | T11 | 8 | T178 | 1 | T26 | 11 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 207 | 1 | T6 | 3 | T8 | 17 | T12 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 269 | 1 | T8 | 11 | T11 | 11 | T48 | 8 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 13838 | 1 | T2 | 19 | T7 | 11 | T9 | 131 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 70 | 1 | T56 | 9 | T57 | 2 | T28 | 12 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 30 | 1 | T27 | 7 | T249 | 7 | T106 | 4 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 11 | 1 | T318 | 11 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 8 | 1 | T247 | 1 | T316 | 7 | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 112 | 1 | T48 | 6 | T15 | 1 | T250 | 11 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 189 | 1 | T68 | 19 | T168 | 13 | T160 | 12 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 161 | 1 | T12 | 12 | T271 | 2 | T260 | 5 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 124 | 1 | T60 | 16 | T154 | 15 | T222 | 10 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 112 | 1 | T161 | 5 | T359 | 7 | T286 | 4 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 69 | 1 | T180 | 12 | T171 | 7 | T224 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 84 | 1 | T4 | 15 | T27 | 9 | T45 | 2 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 191 | 1 | T160 | 14 | T164 | 4 | T253 | 10 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 102 | 1 | T30 | 2 | T161 | 11 | T171 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 139 | 1 | T6 | 10 | T164 | 9 | T174 | 13 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 131 | 1 | T168 | 10 | T99 | 2 | T281 | 22 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 161 | 1 | T68 | 1 | T154 | 10 | T160 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 113 | 1 | T30 | 4 | T68 | 1 | T155 | 1 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 169 | 1 | T27 | 10 | T167 | 13 | T275 | 12 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 1075 | 1 | T3 | 25 | T5 | 18 | T10 | 23 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 104 | 1 | T11 | 10 | T252 | 2 | T99 | 10 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 169 | 1 | T6 | 6 | T8 | 18 | T12 | 6 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 267 | 1 | T8 | 15 | T11 | 11 | T253 | 5 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 103 | 1 | T48 | 1 | T14 | 1 | T82 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T48 | 7 | T29 | 3 | T46 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 252 | 1 | T68 | 20 | T168 | 14 | T160 | 13 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 184 | 1 | T12 | 13 | T57 | 1 | T24 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 134 | 1 | T24 | 1 | T175 | 1 | T60 | 17 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 160 | 1 | T4 | 16 | T161 | 6 | T157 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 124 | 1 | T189 | 1 | T160 | 15 | T162 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 75 | 1 | T27 | 10 | T152 | 1 | T189 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 218 | 1 | T164 | 5 | T253 | 11 | T96 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 189 | 1 | T30 | 3 | T175 | 1 | T156 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 166 | 1 | T6 | 11 | T164 | 10 | T193 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 133 | 1 | T155 | 2 | T168 | 11 | T156 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T178 | 1 | T68 | 2 | T154 | 11 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1407 | 1 | T1 | 1 | T3 | 28 | T5 | 20 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 213 | 1 | T11 | 11 | T27 | 11 | T167 | 14 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 150 | 1 | T30 | 11 | T152 | 8 | T253 | 6 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 154 | 1 | T178 | 1 | T26 | 1 | T252 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 232 | 1 | T6 | 7 | T8 | 19 | T12 | 7 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 260 | 1 | T11 | 12 | T48 | 1 | T27 | 8 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 49 | 1 | T56 | 10 | T57 | 3 | T155 | 21 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 33 | 1 | T8 | 16 | T41 | 1 | T338 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 14005 | 1 | T2 | 19 | T7 | 11 | T9 | 131 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 33 | 1 | T289 | 11 | T247 | 2 | T225 | 1 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 147 | 1 | T48 | 5 | T29 | 23 | T15 | 1 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 224 | 1 | T68 | 22 | T168 | 12 | T160 | 14 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 117 | 1 | T181 | 16 | T261 | 6 | T200 | 24 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 111 | 1 | T60 | 13 | T154 | 17 | T284 | 8 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 145 | 1 | T4 | 12 | T161 | 8 | T157 | 11 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 99 | 1 | T160 | 16 | T162 | 12 | T242 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 60 | 1 | T310 | 12 | T360 | 13 | T361 | 10 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 151 | 1 | T164 | 4 | T253 | 5 | T298 | 3 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 251 | 1 | T175 | 5 | T156 | 18 | T161 | 5 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 124 | 1 | T6 | 11 | T164 | 9 | T193 | 9 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 72 | 1 | T156 | 6 | T173 | 13 | T304 | 7 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 182 | 1 | T154 | 8 | T163 | 17 | T170 | 23 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1284 | 1 | T48 | 3 | T55 | 15 | T32 | 6 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 122 | 1 | T11 | 7 | T275 | 12 | T245 | 8 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 76 | 1 | T253 | 2 | T184 | 9 | T320 | 10 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 119 | 1 | T26 | 10 | T263 | 9 | T362 | 5 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 204 | 1 | T6 | 2 | T8 | 16 | T28 | 14 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 193 | 1 | T11 | 10 | T48 | 7 | T253 | 6 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 55 | 1 | T56 | 10 | T57 | 1 | T155 | 20 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 34 | 1 | T8 | 10 | T41 | 14 | T338 | 7 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 48 | 1 | T175 | 14 | T162 | 8 | T219 | 15 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 27 | 1 | T289 | 14 | T266 | 2 | T350 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 3 | 45 | 93.75 | 3 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 89 | 1 | T56 | 10 | T57 | 3 | T28 | 13 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 40 | 1 | T27 | 8 | T41 | 1 | T249 | 8 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 14 | 1 | T175 | 1 | T162 | 1 | T318 | 12 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 12 | 1 | T247 | 2 | T225 | 1 | T316 | 8 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 157 | 1 | T48 | 7 | T29 | 2 | T46 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 231 | 1 | T68 | 20 | T168 | 14 | T160 | 13 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 195 | 1 | T12 | 13 | T57 | 1 | T24 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 161 | 1 | T24 | 1 | T175 | 1 | T60 | 17 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 142 | 1 | T161 | 6 | T158 | 1 | T181 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 89 | 1 | T189 | 1 | T162 | 1 | T242 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 114 | 1 | T4 | 16 | T27 | 10 | T152 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 229 | 1 | T160 | 15 | T164 | 5 | T253 | 11 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 139 | 1 | T30 | 3 | T175 | 1 | T156 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 166 | 1 | T6 | 11 | T164 | 10 | T169 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 167 | 1 | T168 | 11 | T156 | 1 | T181 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 201 | 1 | T178 | 1 | T68 | 2 | T154 | 11 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 148 | 1 | T48 | 1 | T30 | 5 | T68 | 2 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 207 | 1 | T27 | 11 | T167 | 14 | T40 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 1407 | 1 | T1 | 1 | T3 | 28 | T5 | 20 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 134 | 1 | T11 | 11 | T178 | 1 | T26 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 223 | 1 | T6 | 7 | T8 | 19 | T12 | 7 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 309 | 1 | T8 | 16 | T11 | 12 | T48 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 13941 | 1 | T2 | 19 | T7 | 11 | T9 | 131 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 108 | 1 | T56 | 10 | T57 | 1 | T28 | 14 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 49 | 1 | T41 | 14 | T338 | 7 | T106 | 2 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 33 | 1 | T175 | 14 | T162 | 8 | T318 | 11 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 8 | 1 | T316 | 8 | - | - | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 123 | 1 | T48 | 5 | T29 | 14 | T15 | 1 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 229 | 1 | T68 | 22 | T168 | 12 | T160 | 14 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 101 | 1 | T29 | 9 | T260 | 8 | T54 | 1 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 90 | 1 | T60 | 13 | T154 | 17 | T284 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 159 | 1 | T161 | 8 | T181 | 16 | T261 | 6 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 88 | 1 | T162 | 12 | T242 | 8 | T171 | 6 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 89 | 1 | T4 | 12 | T157 | 11 | T45 | 2 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 172 | 1 | T160 | 16 | T164 | 4 | T253 | 5 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 198 | 1 | T175 | 5 | T156 | 18 | T161 | 5 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 106 | 1 | T6 | 11 | T164 | 9 | T169 | 15 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 113 | 1 | T156 | 6 | T181 | 10 | T281 | 23 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T154 | 8 | T163 | 17 | T193 | 9 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 157 | 1 | T48 | 3 | T156 | 8 | T157 | 4 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T275 | 12 | T170 | 12 | T245 | 8 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 1225 | 1 | T55 | 15 | T32 | 6 | T159 | 19 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 78 | 1 | T11 | 7 | T26 | 10 | T259 | 1 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 153 | 1 | T6 | 2 | T8 | 16 | T157 | 2 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 227 | 1 | T8 | 10 | T11 | 10 | T48 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 18515 | 1 | T1 | 1 | T2 | 19 | T3 | 28 | ||||
auto[1] | auto[0] | 3845 | 1 | T4 | 12 | T6 | 13 | T8 | 26 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |