Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19122

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3238

1

T8

26

T11

40

T48

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16687

1

T2

19

T6

9

T7

11

auto[1]

5673

1

T1

1

T3

28

T4

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	185	1			T48	4		T181	17		T52	8
values[0]	69	1			T11	22		T160	31		T321	1
values[1]	797	1			T6	9		T8	26		T27	10
values[2]	2918	1			T1	1		T3	28		T5	20
values[3]	542	1			T57	4		T158	1		T253	8
values[4]	592	1			T6	22		T24	1		T27	11
values[5]	584	1			T48	12		T178	1		T68	42
values[6]	503	1			T11	18		T48	8		T27	8
values[7]	660	1			T12	13		T56	20		T24	1
values[8]	669	1			T4	28		T12	7		T29	15
values[9]	900	1			T8	35		T28	27		T175	7
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	730	1			T6	9		T8	26		T167	14
values[1]	2883	1			T1	1		T3	28		T5	20
values[2]	548	1			T57	4		T30	5		T175	15
values[3]	614	1			T6	22		T24	1		T27	11
values[4]	591	1			T48	12		T178	1		T160	27
values[5]	557	1			T11	18		T48	8		T24	1
values[6]	674	1			T12	13		T56	20		T26	11
values[7]	584	1			T4	28		T8	35		T12	7
values[8]	758	1			T48	4		T28	27		T175	7
values[9]	191	1			T60	30		T329	1		T338	8
minimum	14230	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	3		T152	1		T154	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	11		T167	1		T155	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T1	1		T3	3		T5	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T178	1		T152	1		T242	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T253	10		T194	1		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T57	2		T30	1		T175	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	12		T27	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T24	1		T29	10		T68	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T48	6		T178	1		T160	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T157	3		T222	10		T169	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T27	1		T168	1		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	8		T48	8		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T12	1		T29	15		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T56	11		T26	11		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	13		T8	17		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T68	2		T156	19		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	4		T175	7		T181	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T28	15		T154	18		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T60	14		T329	1		T302	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T338	8		T202	16		T320	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13940	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T11	11		T153	1		T302	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	6		T152	7		T154	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	15		T167	13		T155	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T3	25		T5	18		T10	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T171	7		T223	6		T183	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T253	10		T194	4		T274	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T57	2		T30	4		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	10		T27	10		T155	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T68	19		T179	13		T271	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T48	6		T160	12		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T222	10		T224	12		T304	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T27	7		T168	10		T164	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	10		T30	2		T250	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	12		T30	10		T160	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T56	9		T161	11		T164	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T4	15		T8	18		T12	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T68	2		T252	2		T171	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T99	2		T15	1		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T28	12		T154	15		T52	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T60	16		T302	10		T231	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T202	15		T322	11		T363	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T48	1		T14	1		T27	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T11	11		T302	1		T299	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T48	4		T181	17		T269	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T52	6		T270	1		T202	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T160	17		T321	1		T323	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T11	11		T324	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	3		T27	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	11		T167	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T1	1		T3	3		T5	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T178	1		T152	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T158	1		T253	3		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T57	2		T95	1		T41	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	12		T27	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T24	1		T29	10		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	6		T178	1		T168	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T68	23		T157	3		T34	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T27	1		T189	1		T160	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	8		T48	8		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	1		T168	1		T157	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T56	11		T24	1		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	13		T12	1		T29	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T68	2		T189	1		T156	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	17		T175	7		T60	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T28	15		T154	18		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T299	1		T364	10		T278	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T52	2		T270	10		T202	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T160	14		T323	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T11	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	6		T27	9		T152	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	15		T167	13		T155	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T3	25		T5	18		T10	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T275	12		T223	6		T254	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T253	5		T194	4		T174	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T57	2		T260	5		T171	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	10		T27	10		T155	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T30	4		T179	13		T268	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T48	6		T168	13		T99	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T68	19		T271	2		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T27	7		T160	12		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	10		T30	2		T250	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	12		T168	10		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T56	9		T161	11		T171	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	15		T12	6		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T68	2		T164	9		T252	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	18		T60	16		T99	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	12		T154	15		T173	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	7		T152	8		T154	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	16		T167	14		T155	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T1	1		T3	28		T5	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T178	1		T152	1		T242	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T253	12		T194	5		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T57	3		T30	5		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	11		T27	11		T155	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T24	1		T29	1		T68	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	7		T178	1		T160	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T157	1		T222	11		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T27	8		T168	11		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	11		T48	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	13		T29	1		T30	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T56	10		T26	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	16		T8	19		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T68	4		T156	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	1		T175	2		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T28	13		T154	16		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T60	17		T329	1		T302	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T338	1		T202	16		T320	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14033	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T11	12		T153	1		T302	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	2		T154	8		T169	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	10		T155	20		T181	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T55	15		T32	6		T159	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T242	8		T171	5		T183	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T253	8		T174	19		T310	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T57	1		T175	14		T41	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	11		T168	12		T41	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	9		T68	22		T156	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	5		T160	14		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T157	2		T222	9		T169	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T157	4		T164	4		T245	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	7		T48	7		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T29	14		T253	5		T41	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T56	10		T26	10		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	12		T8	16		T210	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T156	18		T171	6		T304	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T48	3		T175	5		T181	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T28	14		T154	17		T193	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T60	13		T302	10		T231	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T338	7		T202	15		T320	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T160	16		T156	6		T163	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T11	10		T299	8		T317	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T48	1		T181	1		T269	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T52	6		T270	11		T202	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T160	15		T321	1		T323	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T11	12		T324	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	7		T27	10		T152	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	16		T167	14		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T1	1		T3	28		T5	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T178	1		T152	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T158	1		T253	6		T194	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T57	3		T95	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	11		T27	11		T155	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T24	1		T29	1		T30	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	7		T178	1		T168	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T68	20		T157	1		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T27	8		T189	1		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	11		T48	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	13		T168	11		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T56	10		T24	1		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	16		T12	7		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T68	4		T189	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	19		T175	2		T60	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T28	13		T154	16		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T48	3		T181	16		T269	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T52	2		T202	15		T365	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T160	16		T323	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T11	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	2		T154	8		T156	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	10		T155	20		T181	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T55	15		T32	6		T159	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T275	12		T170	11		T183	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T253	2		T174	19		T310	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T57	1		T41	14		T242	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	11		T253	6		T41	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	9		T175	14		T156	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	5		T168	12		T261	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T68	22		T157	2		T34	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T160	14		T45	2		T164	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	7		T48	7		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T157	4		T253	5		T41	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T56	10		T26	10		T161	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	12		T29	14		T210	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T156	18		T164	9		T171	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	16		T175	5		T60	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T28	14		T154	17		T193	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26