Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T28	13		T29	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T68	2		T175	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T27	11		T161	6		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T6	7		T48	2		T57	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	7		T48	7		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T29	1		T167	14		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T1	1		T3	28		T5	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T178	1		T154	16		T155	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	12		T24	1		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T160	13		T41	1		T271	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T156	1		T258	5		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T189	1		T158	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	11		T12	13		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	10		T156	1		T251	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T26	1		T27	8		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	11		T24	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T4	16		T57	3		T30	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	16		T154	11		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T272	9		T211	1		T273	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T56	10		T30	3		T99	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13959	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T28	14		T156	8		T181	26
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T175	14		T15	1		T245	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T161	8		T157	2		T162	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	2		T48	10		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	5		T170	12		T171	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	9		T157	11		T253	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T8	16		T55	15		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T154	17		T155	20		T170	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	10		T34	4		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T160	14		T41	14		T193	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T156	18		T174	19		T184	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T163	17		T172	7		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	7		T68	22		T175	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T156	6		T275	12		T284	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	10		T161	5		T222	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	11		T162	12		T245	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	12		T57	1		T160	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	10		T154	8		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T272	8		T273	6		T285	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T56	10		T169	15		T257	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T270	2		T23	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T162	1		T99	11		T254	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T100	1		T180	13		T278	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T130	14		T279	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T28	13		T29	1		T181	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T68	2		T175	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T178	1		T27	11		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T48	1		T57	1		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	7		T168	11		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	7		T48	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T1	1		T3	28		T5	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T178	1		T167	14		T154	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T8	19		T157	1		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T160	13		T49	1		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	1		T156	1		T258	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T189	1		T158	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	11		T12	13		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	11		T27	10		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T26	1		T30	5		T68	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T24	1		T162	1		T275	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T4	16		T57	3		T27	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T8	16		T56	10		T30	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T162	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T213	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T28	14		T181	26		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T175	14		T15	1		T245	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T156	8		T161	8		T162	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T48	3		T29	9		T281	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T157	2		T170	12		T224	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	2		T48	7		T164	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T11	10		T48	5		T55	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T154	17		T155	20		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	16		T157	4		T34	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T160	14		T41	14		T193	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T156	18		T171	13		T174	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T163	17		T172	7		T282	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	7		T175	5		T184	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T6	11		T156	6		T284	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	10		T68	22		T161	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T162	12		T275	12		T245	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	12		T57	1		T160	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T8	10		T56	10		T154	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26