Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

16599

1

T2

19

T4

28

T7

11

auto[ADC_CTRL_FILTER_COND_OUT]

5761

1

T1

1

T3

28

T5

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16973

1

T2

19

T6

9

T7

11

auto[1]

5387

1

T1

1

T3

28

T4

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	39	1			T161	17		T286	8		T287	14
values[0]	96	1			T288	1		T289	30		T290	8
values[1]	420	1			T6	9		T178	1		T57	4
values[2]	623	1			T12	13		T48	4		T152	1
values[3]	588	1			T4	28		T6	22		T27	10
values[4]	611	1			T8	26		T12	7		T153	1
values[5]	674	1			T8	35		T11	18		T28	27
values[6]	557	1			T27	8		T30	8		T68	2
values[7]	691	1			T26	11		T27	11		T160	3
values[8]	466	1			T178	1		T29	16		T167	14
values[9]	3654	1			T1	1		T3	28		T5	20
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	668	1			T6	9		T178	1		T57	4
values[1]	2985	1			T1	1		T3	28		T5	20
values[2]	554	1			T4	28		T12	7		T27	10
values[3]	648	1			T8	26		T30	11		T152	8
values[4]	701	1			T8	35		T11	18		T27	8
values[5]	567	1			T30	3		T68	2		T160	31
values[6]	543	1			T26	11		T27	11		T29	15
values[7]	540	1			T48	12		T29	1		T167	14
values[8]	1024	1			T11	22		T48	8		T178	1
values[9]	189	1			T41	5		T52	8		T281	46
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T178	1		T152	1		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	3		T57	2		T68	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T48	4		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1636	1			T1	1		T3	3		T5	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	13		T12	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T27	1		T181	17		T261	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	1		T152	1		T161	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	11		T160	15		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	8		T28	15		T157	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T8	17		T27	1		T168	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	1		T158	1		T164	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T68	1		T160	17		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T30	1		T156	9		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T26	11		T27	1		T29	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T48	6		T29	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T175	1		T155	21		T156	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T48	8		T24	2		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T11	11		T178	1		T56	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T41	5		T291	4		T286	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T52	6		T281	24		T200	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T168	10		T194	10		T274	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	6		T57	2		T68	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	12		T15	1		T194	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1052	1			T3	25		T5	18		T6	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	15		T12	6		T179	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T27	9		T223	17		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T30	10		T152	7		T161	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	15		T160	12		T99	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	10		T28	12		T271	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	18		T27	7		T168	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T30	2		T164	4		T253	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T68	1		T160	14		T253	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T30	4		T180	12		T286	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T27	10		T160	2		T45	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	6		T167	13		T258	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T155	20		T99	2		T260	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T154	15		T161	11		T171	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	11		T56	9		T60	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T286	7		T219	12		T292	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T52	2		T281	22		T205	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T161	6		T286	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T287	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T289	18		T290	1		T293	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T288	1		T294	1		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T178	1		T189	1		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	3		T57	2		T68	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T48	4		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T158	1		T162	13		T41	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	13		T161	9		T179	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	12		T27	1		T222	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T153	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	11		T160	15		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	8		T28	15		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	17		T168	13		T252	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T30	2		T158	1		T164	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	1		T68	1		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T156	9		T100	1		T180	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T26	11		T27	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T29	1		T167	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T178	1		T29	15		T175	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T48	14		T24	2		T29	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1906	1			T1	1		T3	3		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T161	11		T286	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T287	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T289	12		T290	7		T293	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T294	8		T216	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T194	10		T130	13		T266	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T6	6		T57	2		T68	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	12		T168	10		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T223	6		T173	1		T259	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	15		T161	5		T179	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T6	10		T27	9		T222	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	6		T152	7		T254	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	15		T160	12		T99	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	10		T28	12		T30	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	18		T168	13		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T30	6		T164	4		T253	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T27	7		T68	1		T160	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T180	12		T263	10		T286	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T27	10		T160	2		T45	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T167	13		T258	4		T270	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T99	2		T260	5		T254	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T48	6		T154	15		T171	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1234	1			T3	25		T5	18		T10	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T178	1		T152	1		T168	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	7		T57	3		T68	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	13		T48	1		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1397	1			T1	1		T3	28		T5	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	16		T12	7		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T27	10		T181	1		T261	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T30	11		T152	8		T161	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	16		T160	13		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	11		T28	13		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	19		T27	8		T168	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	3		T158	1		T164	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T68	2		T160	15		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T30	5		T156	1		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	1		T27	11		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T48	7		T29	1		T167	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T175	1		T155	21		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T48	1		T24	2		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T11	12		T178	1		T56	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T41	1		T291	4		T286	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T52	6		T281	23		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T41	15		T245	9		T295	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	2		T57	1		T68	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	3		T15	1		T169	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1291	1			T6	11		T55	15		T32	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	12		T179	8		T284	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T181	16		T261	6		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T161	8		T162	12		T243	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	10		T160	14		T171	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	7		T28	14		T157	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	16		T168	12		T193	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T164	4		T253	2		T34	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T160	16		T253	6		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T156	8		T245	8		T296	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T26	10		T29	14		T175	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T48	5		T263	11		T268	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T155	20		T156	18		T260	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T48	7		T29	9		T154	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T11	10		T56	10		T60	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T41	4		T219	4		T292	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T52	2		T281	23		T200	24

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T161	12		T286	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T287	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T289	14		T290	8		T293	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T288	1		T294	9		T216	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T178	1		T189	1		T194	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	7		T57	3		T68	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	13		T48	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T158	1		T162	1		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	16		T161	6		T179	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	11		T27	10		T222	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	7		T153	1		T152	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	16		T160	13		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	11		T28	13		T30	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	19		T168	14		T252	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T30	8		T158	1		T164	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T27	8		T68	2		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T156	1		T100	1		T180	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T26	1		T27	11		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	1		T167	14		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T178	1		T29	1		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T48	8		T24	2		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1610	1			T1	1		T3	28		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T161	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T289	16		T293	15		T215	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T295	1		T297	7		T266	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	2		T57	1		T68	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	3		T15	1		T41	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T162	12		T41	14		T259	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	12		T161	8		T179	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	11		T222	9		T261	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T174	19		T298	10		T184	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	10		T160	14		T181	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	7		T28	14		T157	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	16		T168	12		T174	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T164	4		T253	2		T34	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T160	16		T253	6		T193	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T156	8		T170	11		T245	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	10		T45	2		T164	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T268	15		T296	6		T299	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T29	14		T175	14		T156	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T48	12		T29	9		T154	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1530	1			T11	10		T55	15		T56	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26