Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19173

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3187

1

T4

28

T6

31

T8

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16852

1

T2

19

T4

28

T7

11

auto[1]

5508

1

T1

1

T3

28

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T100	1		T295	5		-	-
values[0]	43	1			T209	1		T263	20		T300	20
values[1]	653	1			T11	18		T168	11		T161	14
values[2]	612	1			T8	35		T12	7		T48	12
values[3]	580	1			T26	11		T29	1		T68	42
values[4]	571	1			T11	22		T48	12		T28	27
values[5]	604	1			T4	28		T12	13		T24	1
values[6]	599	1			T8	26		T57	1		T29	10
values[7]	563	1			T6	22		T56	20		T57	4
values[8]	703	1			T178	1		T30	11		T154	33
values[9]	3485	1			T1	1		T3	28		T5	20
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	873	1			T8	35		T11	18		T12	7
values[1]	593	1			T48	8		T27	10		T30	5
values[2]	612	1			T48	12		T29	1		T160	31
values[3]	520	1			T11	22		T24	1		T26	11
values[4]	591	1			T4	28		T12	13		T57	1
values[5]	600	1			T56	20		T29	10		T153	1
values[6]	2979	1			T1	1		T3	28		T5	20
values[7]	685	1			T178	1		T29	15		T155	2
values[8]	837	1			T6	9		T178	1		T30	3
values[9]	108	1			T163	18		T95	1		T100	1
minimum	13962	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	17		T11	8		T12	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T48	4		T157	3		T41	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T48	8		T30	1		T68	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T27	1		T152	1		T245	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T48	6		T160	17		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	1		T156	19		T162	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T26	11		T175	16		T189	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	11		T24	1		T28	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	1		T68	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	13		T57	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T153	1		T152	1		T156	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T56	11		T29	10		T157	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T1	1		T3	3		T5	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	12		T8	11		T57	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T29	15		T155	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T178	1		T168	13		T34	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T30	1		T167	1		T156	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	3		T178	1		T154	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T100	1		T170	13		T210	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T163	18		T95	1		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13850	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T245	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	18		T11	10		T12	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T172	5		T249	7		T274	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T30	4		T68	19		T155	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T27	9		T301	11		T270	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	6		T160	14		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T164	9		T258	4		T250	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T253	5		T171	7		T254	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T11	11		T28	12		T289	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T12	12		T68	1		T252	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	15		T27	10		T68	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	7		T45	2		T99	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T56	9		T260	5		T302	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T3	25		T5	18		T10	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	10		T8	15		T57	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T155	1		T160	2		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T168	13		T194	4		T183	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T30	2		T167	13		T275	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	6		T154	10		T160	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T210	13		T214	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T271	2		T223	11		T299	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T100	1		T295	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T209	1		T263	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T300	9		T186	1		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	8		T168	1		T161	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T51	4		T245	18		T172	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	17		T12	1		T48	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	4		T27	1		T157	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T26	11		T68	23		T155	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T29	1		T152	1		T162	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	6		T175	15		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	11		T28	15		T175	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	1		T175	1		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	13		T24	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T68	1		T152	1		T156	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	11		T57	1		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T153	1		T45	4		T169	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	12		T56	11		T57	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	1		T155	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T178	1		T154	18		T168	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1775	1			T1	1		T3	3		T5	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T6	3		T178	1		T154	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T263	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T300	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	10		T168	10		T161	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T172	5		T249	7		T174	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T8	18		T12	6		T30	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T27	9		T164	9		T301	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T68	19		T155	20		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T250	9		T194	10		T183	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T48	6		T160	14		T251	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	11		T28	12		T253	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T12	12		T253	5		T99	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	15		T27	10		T68	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T68	1		T152	7		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	15		T61	10		T282	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T45	2		T304	10		T182	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	10		T56	9		T57	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T30	10		T155	1		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T154	15		T168	13		T194	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T3	25		T5	18		T10	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	6		T154	10		T160	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T8	19		T11	11		T12	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T48	1		T157	1		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	1		T30	5		T68	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T27	10		T152	1		T245	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	7		T160	15		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T29	1		T156	1		T162	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T26	1		T175	2		T189	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	12		T24	1		T28	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	13		T68	2		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T4	16		T57	1		T27	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T153	1		T152	8		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T56	10		T29	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T1	1		T3	28		T5	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	11		T8	16		T57	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T29	1		T155	2		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T178	1		T168	14		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T30	3		T167	14		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	7		T178	1		T154	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T100	1		T170	1		T210	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T163	1		T95	1		T271	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13942	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	16		T11	7		T161	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T48	3		T157	2		T41	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T48	7		T68	22		T155	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T245	8		T263	11		T244	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	5		T160	16		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T156	18		T162	24		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	10		T175	14		T253	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T11	10		T28	14		T175	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T242	8		T304	7		T218	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	12		T253	11		T193	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T156	6		T45	2		T179	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T56	10		T29	9		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T55	15		T32	6		T159	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	11		T8	10		T57	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T29	14		T245	9		T304	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T168	12		T34	4		T298	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T156	8		T275	12		T200	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	2		T154	8		T160	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T170	12		T210	10		T295	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T163	17		T299	8		T305	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T306	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T245	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T100	1		T295	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T209	1		T263	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T300	12		T186	1		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	11		T168	11		T161	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	4		T245	2		T172	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	19		T12	7		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	1		T27	10		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T26	1		T68	20		T155	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T29	1		T152	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	7		T175	1		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	12		T28	13		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	13		T175	1		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	16		T24	1		T27	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T68	2		T152	8		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	16		T57	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T153	1		T45	4		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	11		T56	10		T57	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	11		T155	2		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T178	1		T154	16		T168	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T1	1		T3	28		T5	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T6	7		T178	1		T154	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T295	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T263	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T300	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	7		T161	8		T162	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T245	16		T172	7		T174	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T8	16		T48	7		T161	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	3		T157	2		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T26	10		T68	22		T155	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T162	12		T262	14		T268	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	5		T175	14		T160	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	10		T28	14		T175	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T253	2		T242	8		T254	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	12		T253	5		T193	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T156	6		T179	8		T41	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	10		T29	9		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T45	2		T169	10		T304	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	11		T56	10		T57	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T245	9		T184	9		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T154	17		T168	12		T157	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T55	15		T29	14		T32	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	2		T154	8		T160	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26