Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19284

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3076

1

T4

28

T6

9

T8

61

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16440

1

T2

19

T6

31

T7

11

auto[1]

5920

1

T1

1

T3

28

T4

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	86	1			T281	46		T276	1		T307	13
values[0]	88	1			T11	22		T152	1		T160	27
values[1]	620	1			T6	22		T24	1		T26	11
values[2]	620	1			T48	4		T27	10		T68	44
values[3]	639	1			T6	9		T8	35		T11	18
values[4]	661	1			T12	7		T30	11		T175	6
values[5]	2949	1			T1	1		T3	28		T5	20
values[6]	401	1			T27	11		T29	15		T160	3
values[7]	714	1			T8	26		T48	12		T167	14
values[8]	509	1			T56	20		T27	8		T152	8
values[9]	1132	1			T4	28		T12	13		T48	8
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	807	1			T6	22		T11	22		T48	4
values[1]	656	1			T29	1		T68	44		T175	15
values[2]	659	1			T6	9		T8	35		T11	18
values[3]	3118	1			T1	1		T3	28		T5	20
values[4]	415	1			T29	10		T168	11		T156	35
values[5]	407	1			T27	11		T29	15		T175	1
values[6]	738	1			T8	26		T48	12		T56	20
values[7]	458	1			T27	8		T167	14		T152	8
values[8]	923	1			T4	28		T12	13		T178	1
values[9]	228	1			T48	8		T178	1		T168	26
minimum	13951	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	12		T48	4		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	11		T27	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T29	1		T68	1		T175	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T68	23		T189	1		T163	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	8		T161	1		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	3		T8	17		T57	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1668	1			T1	1		T3	3		T5	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T175	6		T160	17		T157	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	10		T156	35		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T168	1		T158	1		T301	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	15		T189	1		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T27	1		T175	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T48	6		T56	11		T60	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	11		T155	1		T161	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T152	1		T158	1		T245	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T27	1		T167	1		T155	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T178	1		T24	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	13		T12	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T48	8		T162	13		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T178	1		T168	13		T179	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13840	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	10		T30	4		T160	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	11		T27	9		T253	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T68	1		T164	9		T253	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T68	19		T222	10		T262	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	10		T99	10		T250	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	6		T8	18		T57	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1085	1			T3	25		T5	18		T10	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T160	14		T45	2		T200	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T287	13		T211	5		T308	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T168	10		T301	11		T183	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T251	14		T15	1		T275	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T27	10		T160	2		T281	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	6		T56	9		T60	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	15		T155	1		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T152	7		T52	2		T53	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T27	7		T167	13		T155	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T30	2		T68	1		T250	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	15		T12	12		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T258	4		T174	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T168	13		T179	13		T125	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T48	1		T14	1		T82	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T281	24		T307	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T276	1		T309	1		T257	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T160	15		T194	1		T281	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T11	11		T152	1		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	12		T24	1		T26	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T162	13		T253	3		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	4		T68	1		T175	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T27	1		T68	23		T222	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	8		T29	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	3		T8	17		T57	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T30	1		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T175	6		T45	4		T181	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T1	1		T3	3		T5	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T168	1		T160	17		T157	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T29	15		T251	1		T15	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T27	1		T160	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	6		T154	18		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	11		T167	1		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T56	11		T152	1		T60	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T27	1		T169	16		T170	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T48	8		T178	1		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T4	13		T12	1		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T281	22		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T257	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T160	12		T194	10		T281	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T11	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	10		T30	4		T252	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T253	5		T298	4		T310	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T68	1		T164	9		T253	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T27	9		T68	19		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	10		T99	10		T304	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	6		T8	18		T57	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	6		T30	10		T250	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T45	2		T200	10		T311	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T3	25		T5	18		T10	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T168	10		T160	14		T281	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T251	14		T15	1		T275	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T27	10		T160	2		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T48	6		T154	15		T99	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	15		T167	13		T155	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T56	9		T152	7		T60	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T27	7		T194	4		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T30	2		T68	1		T258	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T4	15		T12	12		T154	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	11		T48	1		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T11	12		T27	10		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T29	1		T68	2		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T68	20		T189	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	11		T161	1		T99	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	7		T8	19		T57	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1433	1			T1	1		T3	28		T5	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T175	1		T160	15		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T29	1		T156	3		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T168	11		T158	1		T301	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T29	1		T189	1		T251	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T27	11		T175	1		T160	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	7		T56	10		T60	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	16		T155	2		T161	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T152	8		T158	1		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T27	8		T167	14		T155	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T178	1		T24	1		T30	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	16		T12	13		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T48	1		T162	1		T258	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T178	1		T168	14		T179	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13951	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	11		T48	3		T26	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	10		T162	12		T253	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T175	14		T164	9		T253	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T68	22		T163	17		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	7		T304	6		T246	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	2		T8	16		T57	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T55	15		T32	6		T159	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T175	5		T160	16		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T29	9		T156	32		T245	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T246	12		T219	4		T296	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T29	14		T15	1		T41	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T41	15		T284	8		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	5		T56	10		T60	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	10		T161	5		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T245	8		T52	2		T53	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T155	20		T161	8		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T281	23		T173	13		T304	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	12		T154	8		T157	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T48	7		T162	12		T174	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T168	12		T179	8		T312	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T281	23		T307	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T276	1		T309	1		T257	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T160	13		T194	11		T281	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T11	12		T152	1		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	11		T24	1		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T162	1		T253	6		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T48	1		T68	2		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T27	10		T68	20		T222	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	11		T29	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	7		T8	19		T57	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	7		T30	11		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T175	1		T45	4		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T1	1		T3	28		T5	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T168	11		T160	15		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T29	1		T251	15		T15	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T27	11		T160	3		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	7		T154	16		T99	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	16		T167	14		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T56	10		T152	8		T60	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T27	8		T169	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T48	1		T178	1		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T4	16		T12	13		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T281	23		T307	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T257	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T160	14		T281	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T11	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	11		T26	10		T253	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T162	12		T253	2		T298	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T48	3		T175	14		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T68	22		T222	9		T184	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	7		T304	6		T289	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	2		T8	16		T57	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T181	16		T162	8		T171	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T175	5		T45	2		T181	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T55	15		T29	9		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T160	16		T157	2		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T29	14		T15	1		T41	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T41	15		T16	1		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	5		T154	17		T169	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	10		T155	20		T161	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T56	10		T60	13		T164	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T169	15		T170	12		T224	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T48	7		T162	12		T52	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T4	12		T154	8		T168	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26