Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19254

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3106

1

T6

22

T8

26

T11

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16718

1

T2

19

T7

11

T8

26

auto[1]

5642

1

T1

1

T3

28

T4

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T158	1		T313	21		T314	3
values[0]	81	1			T175	15		T162	9		T15	4
values[1]	682	1			T48	12		T29	16		T68	42
values[2]	622	1			T12	13		T57	1		T24	2
values[3]	452	1			T189	1		T161	14		T158	1
values[4]	600	1			T4	28		T27	10		T152	1
values[5]	638	1			T6	22		T178	1		T30	3
values[6]	631	1			T68	2		T154	19		T168	11
values[7]	659	1			T48	4		T27	11		T30	5
values[8]	2852	1			T1	1		T3	28		T5	20
values[9]	1172	1			T6	9		T8	61		T11	22
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	917	1			T48	12		T29	26		T68	42
values[1]	522	1			T12	13		T57	1		T24	2
values[2]	510	1			T4	28		T152	1		T175	1
values[3]	548	1			T27	10		T189	1		T164	9
values[4]	712	1			T6	22		T30	3		T175	6
values[5]	624	1			T178	1		T68	2		T154	19
values[6]	3008	1			T1	1		T3	28		T5	20
values[7]	498	1			T11	18		T26	11		T30	11
values[8]	830	1			T6	9		T8	35		T11	22
values[9]	224	1			T8	26		T56	20		T57	4
minimum	13967	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T48	6		T29	26		T175	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T68	23		T168	13		T160	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	1		T57	1		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T24	1		T60	14		T154	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	13		T152	1		T161	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T175	1		T189	1		T160	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T27	1		T189	1		T171	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T164	5		T253	6		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T30	1		T175	6		T156	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	12		T164	10		T193	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T155	1		T168	1		T156	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T178	1		T68	1		T154	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T1	1		T3	3		T5	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T27	1		T167	1		T252	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T30	1		T152	1		T253	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	8		T26	11		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T6	3		T8	17		T11	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	8		T178	1		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T56	11		T57	2		T155	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T8	11		T41	15		T210	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T262	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	6		T15	1		T271	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T68	19		T168	13		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	12		T210	13		T249	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T60	16		T154	15		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T4	15		T161	5		T45	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T160	14		T222	10		T180	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T27	9		T171	11		T224	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T164	4		T253	10		T194	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T30	2		T161	11		T281	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	10		T164	9		T301	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T155	1		T168	10		T99	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T68	1		T154	10		T160	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T3	25		T5	18		T10	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T27	10		T167	13		T252	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T30	10		T152	7		T253	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	10		T99	10		T223	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	6		T8	18		T11	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	7		T253	5		T251	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T56	9		T57	2		T155	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T8	15		T210	13		T315	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T262	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T158	1		T313	13		T314	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T175	15		T162	9		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T225	1		T316	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T48	6		T29	16		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T68	23		T168	13		T160	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	1		T57	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T24	1		T175	1		T60	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T161	9		T158	1		T181	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T189	1		T162	13		T242	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	13		T27	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T160	17		T253	6		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T30	1		T175	6		T156	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	12		T178	1		T164	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T168	1		T156	7		T181	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T68	1		T154	9		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	4		T30	1		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T27	1		T167	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T1	1		T3	3		T5	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T11	8		T178	1		T26	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T6	3		T8	17		T11	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T8	11		T48	8		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T313	8		T314	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T15	1		T317	6		T318	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T316	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	6		T250	11		T174	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T68	19		T168	13		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	12		T271	2		T260	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T60	16		T154	15		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T161	5		T286	4		T319	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T180	12		T171	7		T194	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T4	15		T27	9		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T160	14		T253	10		T298	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T30	2		T161	11		T171	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	10		T164	13		T281	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T168	10		T99	2		T281	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T68	1		T154	10		T160	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T30	4		T68	1		T155	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T27	10		T167	13		T275	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T3	25		T5	18		T10	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	10		T252	2		T99	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	6		T8	18		T11	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T8	15		T27	7		T253	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T48	7		T29	3		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T68	20		T168	14		T160	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	13		T57	1		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T24	1		T60	17		T154	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	16		T152	1		T161	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T175	1		T189	1		T160	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T27	10		T189	1		T171	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T164	5		T253	11		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T30	3		T175	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	11		T164	10		T193	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T155	2		T168	11		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T178	1		T68	2		T154	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T1	1		T3	28		T5	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T27	11		T167	14		T252	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T30	11		T152	8		T253	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	11		T26	1		T99	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	7		T8	19		T11	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	1		T178	1		T27	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T56	10		T57	3		T155	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T8	16		T41	1		T210	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T262	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	5		T29	23		T175	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T68	22		T168	12		T160	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T261	6		T200	24		T54	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T60	13		T154	17		T284	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T4	12		T161	8		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T160	16		T162	12		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T171	13		T224	6		T310	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T164	4		T253	5		T298	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T175	5		T156	18		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T6	11		T164	9		T193	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T156	6		T181	10		T173	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T154	8		T163	17		T170	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T48	3		T55	15		T32	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T275	12		T245	8		T259	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T253	2		T184	9		T320	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T11	7		T26	10		T263	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	2		T8	16		T11	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	7		T253	6		T169	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T56	10		T57	1		T155	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T8	10		T41	14		T210	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T262	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T158	1		T313	9		T314	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T175	1		T162	1		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T225	1		T316	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	7		T29	2		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T68	20		T168	14		T160	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	13		T57	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T24	1		T175	1		T60	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T161	6		T158	1		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T189	1		T162	1		T242	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	16		T27	10		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T160	15		T253	11		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T30	3		T175	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	11		T178	1		T164	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T168	11		T156	1		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T68	2		T154	11		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T30	5		T68	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T27	11		T167	14		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T1	1		T3	28		T5	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	11		T178	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T6	7		T8	19		T11	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T8	16		T48	1		T27	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T313	12		T213	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T175	14		T162	8		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T316	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T48	5		T29	14		T174	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T68	22		T168	12		T160	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	9		T260	8		T261	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T60	13		T154	17		T284	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T161	8		T181	16		T200	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T162	12		T242	8		T171	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T4	12		T157	11		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T160	16		T253	5		T298	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T175	5		T156	18		T161	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T6	11		T164	13		T169	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T156	6		T181	10		T281	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T154	8		T163	17		T193	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	3		T156	8		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T275	12		T170	12		T245	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T55	15		T32	6		T159	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T11	7		T26	10		T259	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T6	2		T8	16		T11	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T8	10		T48	7		T253	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26