Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19125

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3235

1

T8

26

T11

40

T48

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16666

1

T2

19

T6

9

T7

11

auto[1]

5694

1

T1

1

T3

28

T4

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	52	1			T302	21		T202	31		-	-
values[0]	72	1			T11	22		T27	10		T321	1
values[1]	802	1			T6	9		T8	26		T167	14
values[2]	2894	1			T1	1		T3	28		T5	20
values[3]	611	1			T57	4		T152	1		T158	1
values[4]	552	1			T6	22		T24	1		T27	11
values[5]	510	1			T48	12		T178	1		T68	42
values[6]	575	1			T11	18		T48	8		T27	8
values[7]	607	1			T12	13		T56	20		T24	1
values[8]	715	1			T4	28		T12	7		T29	15
values[9]	1029	1			T8	35		T48	4		T28	27
minimum	13941	1			T2	19		T7	11		T9	131

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	999	1			T6	9		T8	26		T11	22
values[1]	2934	1			T1	1		T3	28		T5	20
values[2]	543	1			T57	4		T30	5		T175	15
values[3]	569	1			T6	22		T48	12		T178	1
values[4]	613	1			T11	18		T160	27		T157	3
values[5]	592	1			T12	13		T48	8		T24	1
values[6]	602	1			T56	20		T26	11		T29	1
values[7]	656	1			T4	28		T8	35		T12	7
values[8]	723	1			T48	4		T28	27		T175	7
values[9]	183	1			T321	1		T302	21		T225	1
minimum	13946	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T6	3		T27	1		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T8	11		T11	11		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T1	1		T3	3		T5	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T178	1		T152	1		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T253	10		T194	1		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T57	2		T30	1		T175	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	12		T48	6		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T24	1		T29	10		T68	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T160	15		T45	4		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	8		T157	3		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T27	1		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	8		T24	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T30	1		T253	6		T41	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T56	11		T26	11		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	13		T8	17		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T68	1		T161	1		T252	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	4		T175	7		T60	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T28	15		T154	18		T156	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T302	11		T225	1		T231	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T321	1		T202	16		T320	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13839	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	6		T27	9		T152	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	15		T11	11		T167	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T3	25		T5	18		T10	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T61	10		T171	7		T224	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T253	10		T194	4		T274	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T57	2		T30	4		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	10		T48	6		T27	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T68	19		T179	13		T271	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T160	12		T45	2		T99	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	10		T222	10		T224	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	12		T27	7		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T30	2		T250	20		T171	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T30	10		T253	10		T301	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T56	9		T68	1		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T4	15		T8	18		T12	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T68	1		T252	2		T171	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T60	16		T99	2		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T28	12		T154	15		T52	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T302	10		T231	4		T211	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T202	15		T293	11		T322	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T48	1		T14	1		T82	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T302	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T202	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T27	1		T321	1		T323	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T11	11		T324	1		T325	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	3		T152	1		T154	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	11		T167	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T1	1		T3	3		T5	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T178	1		T158	1		T275	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T158	1		T253	3		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T57	2		T152	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	12		T27	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	1		T29	10		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	6		T178	1		T168	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T68	23		T157	3		T179	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T27	1		T189	1		T160	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	8		T48	8		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	1		T168	1		T157	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T56	11		T24	1		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	13		T12	1		T29	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T68	2		T189	1		T156	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T8	17		T48	4		T175	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T28	15		T154	18		T49	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T302	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T202	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T27	9		T323	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T11	11		T325	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	6		T152	7		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	15		T167	13		T155	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T3	25		T5	18		T10	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T275	12		T223	6		T254	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T253	5		T194	4		T200	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T57	2		T260	5		T171	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	10		T27	10		T155	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T30	4		T224	12		T268	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T48	6		T168	13		T99	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T68	19		T179	13		T271	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T27	7		T160	12		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	10		T30	2		T250	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	12		T168	10		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T56	9		T161	11		T171	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	15		T12	6		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T68	2		T164	9		T252	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	18		T60	16		T99	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T28	12		T154	15		T52	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T6	7		T27	10		T152	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T8	16		T11	12		T167	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T1	1		T3	28		T5	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T178	1		T152	1		T61	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T253	12		T194	5		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T57	3		T30	5		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	11		T48	7		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T24	1		T29	1		T68	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T160	13		T45	4		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	11		T157	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	13		T27	8		T168	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T48	1		T24	1		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	11		T253	11		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T56	10		T26	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	16		T8	19		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T68	2		T161	1		T252	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	1		T175	2		T60	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T28	13		T154	16		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T302	11		T225	1		T231	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T321	1		T202	16		T320	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13946	1			T2	19		T7	11		T9	131
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	2		T154	8		T160	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	10		T11	10		T155	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T55	15		T32	6		T159	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T171	5		T183	7		T262	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T253	8		T174	19		T310	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T57	1		T175	14		T41	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	11		T48	5		T168	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T29	9		T68	22		T156	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T160	14		T45	2		T261	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	7		T157	2		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T157	4		T164	4		T245	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T48	7		T157	11		T34	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T253	5		T41	4		T184	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	10		T26	10		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	12		T8	16		T29	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T171	6		T254	14		T304	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T48	3		T175	5		T60	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T28	14		T154	17		T156	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T302	10		T231	4		T326	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T202	15		T320	10		T293	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T302	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T202	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T27	10		T321	1		T323	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T11	12		T324	1		T325	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	7		T152	8		T154	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	16		T167	14		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T1	1		T3	28		T5	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T178	1		T158	1		T275	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T158	1		T253	6		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T57	3		T152	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	11		T27	11		T155	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T24	1		T29	1		T30	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T48	7		T178	1		T168	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T68	20		T157	1		T179	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T27	8		T189	1		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	11		T48	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	13		T168	11		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T56	10		T24	1		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	16		T12	7		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T68	4		T189	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	19		T48	1		T175	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T28	13		T154	16		T49	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T302	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T202	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T323	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T11	10		T325	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	2		T154	8		T160	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	10		T155	20		T181	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T55	15		T32	6		T159	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T275	12		T170	11		T183	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T253	2		T242	8		T200	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T57	1		T41	14		T260	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	11		T253	6		T41	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	9		T175	14		T156	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T48	5		T168	12		T261	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T68	22		T157	2		T179	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T160	14		T45	2		T164	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T11	7		T48	7		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T157	4		T253	5		T41	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T56	10		T26	10		T161	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	12		T29	14		T210	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T156	18		T164	9		T171	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	16		T48	3		T175	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T28	14		T154	17		T193	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26