Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19145

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3215

1

T4

28

T8

61

T11

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16719

1

T2

19

T4

28

T6

31

auto[1]

5641

1

T1

1

T3

28

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	546	1			T9	14		T47	1		T58	1
values[0]	2	1			T209	1		T324	1		-	-
values[1]	629	1			T4	28		T6	22		T57	4
values[2]	2947	1			T1	1		T3	28		T5	20
values[3]	573	1			T6	9		T8	26		T11	22
values[4]	561	1			T8	35		T56	20		T57	1
values[5]	774	1			T24	1		T27	10		T28	27
values[6]	684	1			T30	3		T68	2		T152	1
values[7]	771	1			T11	18		T12	13		T48	12
values[8]	608	1			T48	8		T27	8		T68	2
values[9]	642	1			T12	7		T178	1		T30	5
minimum	13623	1			T2	19		T7	11		T9	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	520	1			T6	22		T57	4		T29	1
values[1]	2978	1			T1	1		T3	28		T5	20
values[2]	611	1			T8	61		T11	22		T27	11
values[3]	539	1			T56	20		T57	1		T26	11
values[4]	829	1			T24	1		T27	10		T28	27
values[5]	628	1			T30	11		T68	2		T152	1
values[6]	743	1			T11	18		T12	13		T48	12
values[7]	670	1			T48	8		T178	1		T27	8
values[8]	569	1			T12	7		T153	1		T175	6
values[9]	114	1			T182	11		T282	26		T266	5
minimum	14159	1			T2	19		T4	28		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	12		T57	2		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T189	2		T161	9		T157	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T1	1		T3	3		T5	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T222	10		T274	1		T184	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	15		T189	1		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	28		T11	11		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T56	11		T152	1		T155	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T57	1		T26	11		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T27	1		T28	15		T156	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T24	1		T30	1		T154	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T30	1		T68	1		T275	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T152	1		T156	19		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	8		T48	6		T68	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T178	1		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T48	8		T168	13		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T178	1		T27	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T153	1		T175	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T100	1		T194	1		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T282	15		T327	1		T255	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T182	1		T266	3		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13869	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T4	13		T288	1		T329	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T6	10		T57	2		T99	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T161	5		T260	5		T270	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1079	1			T3	25		T5	18		T6	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T222	10		T274	11		T184	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T164	4		T218	15		T296	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	33		T11	11		T27	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T56	9		T152	7		T155	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T179	13		T194	4		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T27	9		T28	12		T164	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T30	2		T154	10		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T30	10		T68	1		T275	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T171	7		T52	2		T172	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	10		T48	6		T68	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	12		T251	14		T274	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T168	13		T61	10		T171	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T27	7		T30	4		T68	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	6		T253	5		T180	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T194	10		T224	4		T254	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T282	11		T327	7		T255	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T182	10		T266	2		T330	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T48	1		T14	1		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T4	15		T174	13		T184	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T9	14		T47	1		T58	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T194	1		T254	15		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T324	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T209	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	12		T57	2		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	13		T189	2		T161	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T1	1		T3	3		T5	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T162	13		T222	10		T274	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	3		T29	15		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	11		T11	11		T29	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T56	11		T46	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	17		T57	1		T26	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T27	1		T28	15		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T24	1		T154	9		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T68	1		T275	13		T210	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T30	1		T152	1		T156	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	8		T48	6		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T178	1		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T48	8		T168	13		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	1		T68	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T153	1		T175	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T178	1		T30	1		T154	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13520	1			T2	19		T7	11		T9	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T282	11		T331	10		T327	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T194	10		T254	14		T182	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T6	10		T57	2		T99	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	15		T161	5		T260	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T3	25		T5	18		T10	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T222	10		T274	11		T184	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T6	6		T164	4		T218	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	15		T11	11		T160	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T56	9		T53	2		T270	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	18		T27	10		T155	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T27	9		T28	12		T152	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T154	10		T160	2		T270	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T68	1		T275	12		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	2		T161	11		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	10		T48	6		T30	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	12		T251	14		T274	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T168	13		T61	10		T171	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T27	7		T68	1		T167	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	6		T253	5		T180	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T30	4		T154	15		T258	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	11		T57	3		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T189	2		T161	6		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T1	1		T3	28		T5	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T222	11		T274	12		T184	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T29	1		T189	1		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	35		T11	12		T27	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T56	10		T152	8		T155	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T57	1		T26	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T27	10		T28	13		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T24	1		T30	3		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T30	11		T68	2		T275	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T152	1		T156	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	11		T48	7		T68	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	13		T178	1		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	1		T168	14		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T178	1		T27	8		T30	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	7		T153	1		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T100	1		T194	11		T224	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T282	12		T327	8		T255	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T182	11		T266	3		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13963	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T4	16		T288	1		T329	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	11		T57	1		T34	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T161	8		T157	2		T162	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T6	2		T48	3		T55	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T222	9		T184	13		T300	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T29	14		T164	4		T41	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	26		T11	10		T29	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T56	10		T155	20		T253	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T26	10		T179	8		T210	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	14		T156	6		T164	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T154	8		T161	5		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T275	12		T200	24		T210	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T156	18		T169	10		T171	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	7		T48	5		T68	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T157	4		T245	8		T298	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T48	7		T168	12		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T175	14		T154	17		T160	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T175	5		T253	6		T41	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T254	14		T304	11		T263	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T282	14		T255	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T266	2		T330	11		T285	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T163	17		T204	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T4	12		T174	11		T184	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T9	14		T47	1		T58	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T194	11		T254	15		T182	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T324	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T209	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	11		T57	3		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	16		T189	2		T161	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T1	1		T3	28		T5	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T162	1		T222	11		T274	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	7		T29	1		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	16		T11	12		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T56	10		T46	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	19		T57	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T27	10		T28	13		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T24	1		T154	11		T160	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T68	2		T275	13		T210	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T30	3		T152	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	11		T48	7		T30	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	13		T178	1		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	1		T168	14		T61	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T27	8		T68	2		T167	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	7		T153	1		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T178	1		T30	5		T154	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13623	1			T2	19		T7	11		T9	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T282	14		T332	11		T331	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T254	14		T269	12		T129	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	11		T57	1		T163	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	12		T161	8		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T48	3		T55	15		T32	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T162	12		T222	9		T184	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	2		T29	14		T162	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	10		T11	10		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T56	10		T41	4		T53	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	16		T26	10		T179	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T28	14		T155	20		T156	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T154	8		T157	11		T170	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T275	12		T210	12		T184	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T156	18		T161	5		T253	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	7		T48	5		T68	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T157	4		T181	16		T245	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T48	7		T168	12		T171	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T175	14		T160	16		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T175	5		T253	6		T41	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T154	17		T181	10		T162	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26