Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22360

1

T1

1

T2

19

T3

28

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19052

1

T1

1

T2

19

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3308

1

T6

22

T8

61

T11

40

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16806

1

T2

19

T4

28

T7

11

auto[1]

5554

1

T1

1

T3

28

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18666

1

T1

1

T2

19

T3

3

auto[1]

3694

1

T3

25

T4

15

T5

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	324	1			T9	14		T47	1		T58	1
values[0]	38	1			T163	18		T209	1		T264	3
values[1]	597	1			T4	28		T6	22		T57	4
values[2]	2963	1			T1	1		T3	28		T5	20
values[3]	497	1			T6	9		T8	26		T11	22
values[4]	617	1			T8	35		T56	20		T57	1
values[5]	782	1			T24	1		T27	10		T28	27
values[6]	624	1			T30	3		T161	17		T252	3
values[7]	783	1			T11	18		T12	13		T48	12
values[8]	632	1			T48	8		T27	8		T68	2
values[9]	880	1			T12	7		T178	1		T30	5
minimum	13623	1			T2	19		T7	11		T9	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	718	1			T4	28		T6	22		T57	4
values[1]	2981	1			T1	1		T3	28		T5	20
values[2]	606	1			T8	61		T11	22		T27	11
values[3]	545	1			T56	20		T57	1		T26	11
values[4]	800	1			T24	1		T27	10		T28	27
values[5]	630	1			T24	1		T68	2		T152	1
values[6]	736	1			T11	18		T12	13		T48	12
values[7]	637	1			T48	8		T27	8		T30	5
values[8]	659	1			T12	7		T178	1		T153	1
values[9]	84	1			T182	11		T282	26		T266	5
minimum	13964	1			T2	19		T7	11		T9	131

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

3845

1

T4

12

T6

13

T8

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	13		T57	2		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	12		T29	1		T189	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T1	1		T3	3		T5	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T48	4		T162	13		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T29	10		T160	15		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	28		T11	11		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T56	11		T152	1		T155	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T57	1		T26	11		T179	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T27	1		T157	12		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T24	1		T28	15		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	1		T68	1		T275	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T152	1		T169	11		T260	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	6		T68	23		T157	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	8		T12	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T48	8		T68	1		T168	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T27	1		T30	1		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T175	6		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T178	1		T153	1		T175	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T182	1		T282	15		T266	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T330	12		T333	4		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13838	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T334	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	15		T57	2		T99	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	10		T161	5		T260	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T3	25		T5	18		T6	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T222	10		T304	8		T184	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T160	12		T164	4		T200	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	33		T11	11		T27	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T56	9		T152	7		T155	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T179	13		T53	2		T194	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	9		T171	7		T173	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T28	12		T30	2		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T68	1		T275	12		T171	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T52	2		T172	5		T335	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	6		T68	19		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	10		T12	12		T30	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T68	1		T168	13		T258	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T27	7		T30	4		T167	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	6		T180	12		T254	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T253	5		T250	9		T194	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T182	10		T282	11		T266	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T330	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T334	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T9	14		T47	1		T58	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T17	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T163	18		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T209	1		T264	1		T213	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	13		T57	2		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	12		T189	2		T161	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T1	1		T3	3		T5	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T48	4		T29	1		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	3		T29	15		T160	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T8	11		T11	11		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T56	11		T29	10		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	17		T57	1		T26	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T27	1		T152	1		T155	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T24	1		T28	15		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T252	1		T275	13		T171	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T30	1		T161	6		T253	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T48	6		T24	1		T68	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	8		T12	1		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T48	8		T68	1		T175	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T27	1		T167	1		T175	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	1		T161	1		T181	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T178	1		T30	1		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13520	1			T2	19		T7	11		T9	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T17	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T264	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T4	15		T57	2		T99	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	10		T161	5		T260	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T3	25		T5	18		T10	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T222	10		T304	8		T184	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T6	6		T160	12		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T8	15		T11	11		T250	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T56	9		T254	1		T304	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	18		T27	10		T155	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T27	9		T152	7		T155	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T28	12		T154	10		T160	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T252	2		T275	12		T171	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T30	2		T161	11		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	6		T68	20		T45	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	10		T12	12		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T68	1		T168	13		T171	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T27	7		T167	13		T168	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	6		T258	4		T180	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T30	4		T154	15		T253	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T14	1		T82	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	16		T57	3		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	11		T29	1		T189	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T1	1		T3	28		T5	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T48	1		T162	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	1		T160	13		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	35		T11	12		T27	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T56	10		T152	8		T155	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T57	1		T26	1		T179	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T27	10		T157	1		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T24	1		T28	13		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T24	1		T68	2		T275	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T152	1		T169	1		T260	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	7		T68	20		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	11		T12	13		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T48	1		T68	2		T168	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T27	8		T30	5		T167	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	7		T175	1		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T178	1		T153	1		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T182	11		T282	12		T266	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T330	12		T333	4		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13941	1			T2	19		T7	11		T9	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T334	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	12		T57	1		T162	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	11		T161	8		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T6	2		T55	15		T29	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	3		T162	12		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T29	9		T160	14		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	26		T11	10		T41	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T56	10		T155	20		T156	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	10		T179	8		T284	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T157	11		T171	5		T173	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T28	14		T154	8		T161	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T275	12		T171	6		T200	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T169	10		T52	2		T172	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T48	5		T68	22		T157	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	7		T156	18		T210	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T48	7		T168	12		T181	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T154	17		T160	16		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T175	5		T41	15		T254	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T175	14		T253	6		T281	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T282	14		T266	2		T285	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T330	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T334	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T9	14		T47	1		T58	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T17	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T163	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T209	1		T264	3		T213	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	16		T57	3		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	11		T189	2		T161	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T1	1		T3	28		T5	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	1		T29	1		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T6	7		T29	1		T160	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	16		T11	12		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T56	10		T29	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	19		T57	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	10		T152	8		T155	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T24	1		T28	13		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T252	3		T275	13		T171	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	3		T161	12		T253	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	7		T24	1		T68	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	11		T12	13		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T48	1		T68	2		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T27	8		T167	14		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T12	7		T161	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T178	1		T30	5		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13623	1			T2	19		T7	11		T9	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T17	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T163	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T213	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	12		T57	1		T245	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	11		T161	8		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T55	15		T32	6		T159	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T48	3		T34	4		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	2		T29	14		T160	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T8	10		T11	10		T162	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T56	10		T29	9		T41	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	16		T26	10		T179	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T155	20		T156	6		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T28	14		T154	8		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T275	12		T171	6		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T161	5		T253	5		T169	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	5		T68	22		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	7		T156	18		T181	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T48	7		T175	5		T168	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T175	14		T160	16		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T181	10		T41	15		T254	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T154	17		T162	8		T253	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18515

1

T1

1

T2

19

T3

28

auto[1]

auto[0]

3845

1

T4

12

T6

13

T8

26