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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.56


Total test records in report: 920
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T794 /workspace/coverage/default/40.adc_ctrl_clock_gating.3139585352 Aug 14 05:21:07 PM PDT 24 Aug 14 05:23:00 PM PDT 24 181032170976 ps
T795 /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1190859656 Aug 14 05:17:59 PM PDT 24 Aug 14 05:24:44 PM PDT 24 171599751331 ps
T796 /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.796927891 Aug 14 05:17:43 PM PDT 24 Aug 14 05:23:54 PM PDT 24 602737370849 ps
T797 /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1773365941 Aug 14 05:17:22 PM PDT 24 Aug 14 05:29:45 PM PDT 24 489580340967 ps
T798 /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3800623615 Aug 14 05:20:48 PM PDT 24 Aug 14 05:36:10 PM PDT 24 395583126606 ps
T69 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3040481239 Aug 14 04:43:16 PM PDT 24 Aug 14 04:43:27 PM PDT 24 8152333043 ps
T73 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2875625343 Aug 14 04:43:28 PM PDT 24 Aug 14 04:43:36 PM PDT 24 529873693 ps
T78 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3263089864 Aug 14 04:43:34 PM PDT 24 Aug 14 04:43:35 PM PDT 24 354885552 ps
T70 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.95671850 Aug 14 04:43:58 PM PDT 24 Aug 14 04:44:10 PM PDT 24 4348806401 ps
T799 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2662520305 Aug 14 04:43:39 PM PDT 24 Aug 14 04:43:41 PM PDT 24 412717313 ps
T71 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2959725921 Aug 14 04:43:40 PM PDT 24 Aug 14 04:43:44 PM PDT 24 4091707168 ps
T144 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.450711840 Aug 14 04:43:21 PM PDT 24 Aug 14 04:43:22 PM PDT 24 529443925 ps
T145 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4027468911 Aug 14 04:43:27 PM PDT 24 Aug 14 04:43:28 PM PDT 24 366059231 ps
T79 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2939375859 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:20 PM PDT 24 573789669 ps
T86 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.340690813 Aug 14 04:43:14 PM PDT 24 Aug 14 04:43:17 PM PDT 24 531063748 ps
T74 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1338579408 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:27 PM PDT 24 4448035915 ps
T81 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3852150122 Aug 14 04:43:28 PM PDT 24 Aug 14 04:43:30 PM PDT 24 820959150 ps
T800 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4008010994 Aug 14 04:43:54 PM PDT 24 Aug 14 04:43:55 PM PDT 24 541641414 ps
T80 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2683951236 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:23 PM PDT 24 512617401 ps
T801 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1246852274 Aug 14 04:43:31 PM PDT 24 Aug 14 04:43:32 PM PDT 24 532333671 ps
T84 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4189156468 Aug 14 04:43:16 PM PDT 24 Aug 14 04:43:18 PM PDT 24 555231643 ps
T802 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4076662629 Aug 14 04:43:30 PM PDT 24 Aug 14 04:43:37 PM PDT 24 4741440893 ps
T803 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3724276915 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:20 PM PDT 24 457842635 ps
T804 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.734880619 Aug 14 04:43:53 PM PDT 24 Aug 14 04:43:54 PM PDT 24 370372959 ps
T65 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.720354663 Aug 14 04:43:22 PM PDT 24 Aug 14 04:43:26 PM PDT 24 4502204866 ps
T805 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.453298560 Aug 14 04:43:24 PM PDT 24 Aug 14 04:43:26 PM PDT 24 530717752 ps
T66 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2570776227 Aug 14 04:43:24 PM PDT 24 Aug 14 04:43:29 PM PDT 24 2197743547 ps
T806 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3163053405 Aug 14 04:43:37 PM PDT 24 Aug 14 04:43:39 PM PDT 24 523064935 ps
T807 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.306892823 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:20 PM PDT 24 428355224 ps
T808 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1950929862 Aug 14 04:43:50 PM PDT 24 Aug 14 04:43:52 PM PDT 24 396040682 ps
T809 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3630097277 Aug 14 04:43:21 PM PDT 24 Aug 14 04:43:24 PM PDT 24 569344505 ps
T810 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3174111652 Aug 14 04:43:51 PM PDT 24 Aug 14 04:43:52 PM PDT 24 410246922 ps
T811 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2378599702 Aug 14 04:43:28 PM PDT 24 Aug 14 04:43:29 PM PDT 24 414537277 ps
T67 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.506852511 Aug 14 04:43:48 PM PDT 24 Aug 14 04:43:53 PM PDT 24 4567741449 ps
T131 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.462494051 Aug 14 04:43:25 PM PDT 24 Aug 14 04:44:41 PM PDT 24 25268070405 ps
T146 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2184332432 Aug 14 04:43:14 PM PDT 24 Aug 14 04:43:22 PM PDT 24 4258617213 ps
T812 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.716525595 Aug 14 04:44:19 PM PDT 24 Aug 14 04:44:21 PM PDT 24 541775979 ps
T813 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1353137356 Aug 14 04:43:26 PM PDT 24 Aug 14 04:43:27 PM PDT 24 549253838 ps
T147 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2287958544 Aug 14 04:43:15 PM PDT 24 Aug 14 04:43:17 PM PDT 24 2316489677 ps
T814 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1857050265 Aug 14 04:43:22 PM PDT 24 Aug 14 04:43:24 PM PDT 24 556098115 ps
T815 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2781850537 Aug 14 04:44:42 PM PDT 24 Aug 14 04:44:50 PM PDT 24 448771907 ps
T816 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.526612296 Aug 14 04:43:39 PM PDT 24 Aug 14 04:43:41 PM PDT 24 376931050 ps
T87 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1334272645 Aug 14 04:43:15 PM PDT 24 Aug 14 04:43:16 PM PDT 24 530975386 ps
T817 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2747831312 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:23 PM PDT 24 541621967 ps
T85 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3761306531 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:22 PM PDT 24 571276661 ps
T366 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3109365187 Aug 14 04:43:39 PM PDT 24 Aug 14 04:43:44 PM PDT 24 4740882259 ps
T818 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2530595916 Aug 14 04:43:31 PM PDT 24 Aug 14 04:43:32 PM PDT 24 556370269 ps
T819 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2200592481 Aug 14 04:43:31 PM PDT 24 Aug 14 04:43:32 PM PDT 24 591300502 ps
T820 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2029949285 Aug 14 04:43:51 PM PDT 24 Aug 14 04:43:53 PM PDT 24 293056948 ps
T148 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2787788813 Aug 14 04:43:25 PM PDT 24 Aug 14 04:43:26 PM PDT 24 360544960 ps
T149 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2841435241 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:10 PM PDT 24 510034029 ps
T132 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1221841140 Aug 14 04:43:45 PM PDT 24 Aug 14 04:43:47 PM PDT 24 343660149 ps
T133 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.948175473 Aug 14 04:43:21 PM PDT 24 Aug 14 04:43:27 PM PDT 24 381972999 ps
T821 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4220972184 Aug 14 04:43:50 PM PDT 24 Aug 14 04:43:51 PM PDT 24 424212827 ps
T822 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.486344503 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:21 PM PDT 24 533072895 ps
T823 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1674647934 Aug 14 04:43:18 PM PDT 24 Aug 14 04:43:20 PM PDT 24 398989299 ps
T824 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2572760167 Aug 14 04:43:39 PM PDT 24 Aug 14 04:43:40 PM PDT 24 286750278 ps
T825 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1075524525 Aug 14 04:43:30 PM PDT 24 Aug 14 04:43:31 PM PDT 24 385610314 ps
T826 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2905628914 Aug 14 04:43:25 PM PDT 24 Aug 14 04:43:27 PM PDT 24 468513115 ps
T827 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.865577996 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:26 PM PDT 24 2180392265 ps
T828 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1714850945 Aug 14 04:43:22 PM PDT 24 Aug 14 04:43:25 PM PDT 24 349127191 ps
T829 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.694143925 Aug 14 04:43:41 PM PDT 24 Aug 14 04:43:42 PM PDT 24 444687543 ps
T830 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1984010844 Aug 14 04:44:46 PM PDT 24 Aug 14 04:44:46 PM PDT 24 410466899 ps
T134 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4138912822 Aug 14 04:43:34 PM PDT 24 Aug 14 04:43:35 PM PDT 24 436590955 ps
T135 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.680439345 Aug 14 04:43:25 PM PDT 24 Aug 14 04:43:28 PM PDT 24 505307951 ps
T831 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.995824983 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:22 PM PDT 24 1015579366 ps
T832 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2762002757 Aug 14 04:44:51 PM PDT 24 Aug 14 04:44:51 PM PDT 24 371012617 ps
T136 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.415994666 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:21 PM PDT 24 404947853 ps
T833 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1515012830 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:20 PM PDT 24 395949784 ps
T834 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.368971239 Aug 14 04:43:33 PM PDT 24 Aug 14 04:43:36 PM PDT 24 679007628 ps
T367 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2733450947 Aug 14 04:43:56 PM PDT 24 Aug 14 04:44:03 PM PDT 24 4546131097 ps
T835 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.950887693 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:23 PM PDT 24 6113087531 ps
T836 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4190170257 Aug 14 04:43:32 PM PDT 24 Aug 14 04:43:36 PM PDT 24 5709052201 ps
T837 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2086686666 Aug 14 04:43:48 PM PDT 24 Aug 14 04:43:49 PM PDT 24 337574528 ps
T838 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3620301500 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:19 PM PDT 24 421357242 ps
T839 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3992393433 Aug 14 04:43:42 PM PDT 24 Aug 14 04:43:44 PM PDT 24 347930479 ps
T840 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3494783287 Aug 14 04:43:26 PM PDT 24 Aug 14 04:43:27 PM PDT 24 735001220 ps
T841 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3824356483 Aug 14 04:43:39 PM PDT 24 Aug 14 04:43:40 PM PDT 24 493230358 ps
T137 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1559003013 Aug 14 04:43:16 PM PDT 24 Aug 14 04:43:19 PM PDT 24 598307084 ps
T842 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3329467114 Aug 14 04:43:42 PM PDT 24 Aug 14 04:43:44 PM PDT 24 521924279 ps
T138 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.475585004 Aug 14 04:43:18 PM PDT 24 Aug 14 04:44:51 PM PDT 24 42053853897 ps
T843 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4125831773 Aug 14 04:43:15 PM PDT 24 Aug 14 04:43:16 PM PDT 24 359598898 ps
T844 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1493276298 Aug 14 04:43:32 PM PDT 24 Aug 14 04:43:42 PM PDT 24 4711803582 ps
T845 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2115625714 Aug 14 04:44:19 PM PDT 24 Aug 14 04:44:20 PM PDT 24 544505134 ps
T846 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3808687526 Aug 14 04:43:33 PM PDT 24 Aug 14 04:43:36 PM PDT 24 4139777746 ps
T847 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3887289024 Aug 14 04:43:30 PM PDT 24 Aug 14 04:43:32 PM PDT 24 434246294 ps
T848 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2807940549 Aug 14 04:43:16 PM PDT 24 Aug 14 04:43:16 PM PDT 24 366696394 ps
T849 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3515202643 Aug 14 04:43:25 PM PDT 24 Aug 14 04:43:26 PM PDT 24 526649665 ps
T850 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2519097442 Aug 14 04:43:16 PM PDT 24 Aug 14 04:43:23 PM PDT 24 3043246670 ps
T851 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.666620407 Aug 14 04:43:26 PM PDT 24 Aug 14 04:43:33 PM PDT 24 360501344 ps
T852 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2625679065 Aug 14 04:43:34 PM PDT 24 Aug 14 04:43:35 PM PDT 24 347623833 ps
T853 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1675966813 Aug 14 04:43:25 PM PDT 24 Aug 14 04:43:30 PM PDT 24 5235852259 ps
T369 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4013885268 Aug 14 04:43:32 PM PDT 24 Aug 14 04:43:35 PM PDT 24 4434204936 ps
T854 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3037520389 Aug 14 04:43:18 PM PDT 24 Aug 14 04:43:19 PM PDT 24 357975515 ps
T855 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3846714729 Aug 14 04:43:21 PM PDT 24 Aug 14 04:43:24 PM PDT 24 4411188529 ps
T856 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.961865816 Aug 14 04:43:11 PM PDT 24 Aug 14 04:43:22 PM PDT 24 4378345665 ps
T857 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4035732428 Aug 14 04:43:26 PM PDT 24 Aug 14 04:43:27 PM PDT 24 353035505 ps
T858 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.646362229 Aug 14 04:43:42 PM PDT 24 Aug 14 04:43:44 PM PDT 24 4351813269 ps
T859 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4087608598 Aug 14 04:43:24 PM PDT 24 Aug 14 04:43:28 PM PDT 24 394864823 ps
T860 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1859599194 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:18 PM PDT 24 352885872 ps
T861 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.114083002 Aug 14 04:43:53 PM PDT 24 Aug 14 04:43:55 PM PDT 24 404451385 ps
T862 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.412302786 Aug 14 04:43:18 PM PDT 24 Aug 14 04:43:19 PM PDT 24 502543583 ps
T863 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3953104640 Aug 14 04:43:40 PM PDT 24 Aug 14 04:43:41 PM PDT 24 375807544 ps
T864 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3460410996 Aug 14 04:43:44 PM PDT 24 Aug 14 04:43:46 PM PDT 24 464441551 ps
T865 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2334434449 Aug 14 04:43:31 PM PDT 24 Aug 14 04:43:33 PM PDT 24 747477598 ps
T866 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3219410162 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:22 PM PDT 24 431448082 ps
T867 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2674480955 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:21 PM PDT 24 304538812 ps
T868 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2535349237 Aug 14 04:43:23 PM PDT 24 Aug 14 04:43:24 PM PDT 24 574627588 ps
T869 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2606438651 Aug 14 04:43:42 PM PDT 24 Aug 14 04:43:43 PM PDT 24 477224796 ps
T870 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3857109966 Aug 14 04:43:18 PM PDT 24 Aug 14 04:43:22 PM PDT 24 4726228705 ps
T871 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.717397607 Aug 14 04:43:35 PM PDT 24 Aug 14 04:43:36 PM PDT 24 665306743 ps
T872 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3582701778 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:18 PM PDT 24 591841789 ps
T873 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1001333742 Aug 14 04:43:34 PM PDT 24 Aug 14 04:43:35 PM PDT 24 432674548 ps
T874 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2947121573 Aug 14 04:43:37 PM PDT 24 Aug 14 04:43:38 PM PDT 24 513881918 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3310335513 Aug 14 04:43:25 PM PDT 24 Aug 14 04:43:26 PM PDT 24 323589741 ps
T876 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3721384018 Aug 14 04:44:43 PM PDT 24 Aug 14 04:44:45 PM PDT 24 516372181 ps
T877 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2767224314 Aug 14 04:43:38 PM PDT 24 Aug 14 04:43:39 PM PDT 24 462284248 ps
T878 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3015192547 Aug 14 04:43:16 PM PDT 24 Aug 14 04:43:17 PM PDT 24 515530497 ps
T879 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1463017236 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:12 PM PDT 24 393047357 ps
T880 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1143964641 Aug 14 04:43:51 PM PDT 24 Aug 14 04:43:52 PM PDT 24 568615080 ps
T88 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2176064644 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:40 PM PDT 24 8226075177 ps
T139 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2080198310 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:20 PM PDT 24 547162899 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3923575984 Aug 14 04:43:31 PM PDT 24 Aug 14 04:43:32 PM PDT 24 584315707 ps
T882 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2294828040 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:30 PM PDT 24 489338405 ps
T368 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2767805983 Aug 14 04:43:34 PM PDT 24 Aug 14 04:43:47 PM PDT 24 8725021303 ps
T883 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.870037318 Aug 14 04:43:32 PM PDT 24 Aug 14 04:43:42 PM PDT 24 2439382208 ps
T140 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3239312584 Aug 14 04:43:17 PM PDT 24 Aug 14 04:44:24 PM PDT 24 17335262768 ps
T884 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1942728694 Aug 14 04:43:35 PM PDT 24 Aug 14 04:43:36 PM PDT 24 387211546 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3240713005 Aug 14 04:43:31 PM PDT 24 Aug 14 04:43:34 PM PDT 24 740528926 ps
T141 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.115848701 Aug 14 04:43:14 PM PDT 24 Aug 14 04:43:59 PM PDT 24 41291516522 ps
T886 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3723030065 Aug 14 04:43:18 PM PDT 24 Aug 14 04:43:29 PM PDT 24 4529779571 ps
T887 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.142852396 Aug 14 04:43:12 PM PDT 24 Aug 14 04:43:15 PM PDT 24 904353860 ps
T888 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3960598267 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:12 PM PDT 24 657782435 ps
T142 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.911449246 Aug 14 04:43:18 PM PDT 24 Aug 14 04:43:20 PM PDT 24 431759921 ps
T889 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4112353526 Aug 14 04:43:18 PM PDT 24 Aug 14 04:43:21 PM PDT 24 519854303 ps
T890 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.875023121 Aug 14 04:43:56 PM PDT 24 Aug 14 04:43:57 PM PDT 24 576984184 ps
T143 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3480154378 Aug 14 04:43:44 PM PDT 24 Aug 14 04:43:45 PM PDT 24 384583637 ps
T891 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.217976696 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:21 PM PDT 24 2555785811 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2349994449 Aug 14 04:43:27 PM PDT 24 Aug 14 04:43:33 PM PDT 24 4208738834 ps
T893 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3165209704 Aug 14 04:43:23 PM PDT 24 Aug 14 04:43:25 PM PDT 24 344930478 ps
T894 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3243787476 Aug 14 04:43:45 PM PDT 24 Aug 14 04:43:46 PM PDT 24 476216047 ps
T370 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3402554116 Aug 14 04:43:30 PM PDT 24 Aug 14 04:43:47 PM PDT 24 8823224188 ps
T895 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3652484269 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:29 PM PDT 24 4666638279 ps
T896 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1954629679 Aug 14 04:43:28 PM PDT 24 Aug 14 04:43:30 PM PDT 24 2116627155 ps
T89 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.490364339 Aug 14 04:43:13 PM PDT 24 Aug 14 04:43:35 PM PDT 24 8401314006 ps
T897 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3594002632 Aug 14 04:43:50 PM PDT 24 Aug 14 04:43:51 PM PDT 24 392040998 ps
T371 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3338292120 Aug 14 04:43:34 PM PDT 24 Aug 14 04:43:57 PM PDT 24 9044050495 ps
T898 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.589841060 Aug 14 04:43:37 PM PDT 24 Aug 14 04:43:48 PM PDT 24 4828580844 ps
T899 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2844484086 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:22 PM PDT 24 926691585 ps
T900 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1015848503 Aug 14 04:43:56 PM PDT 24 Aug 14 04:44:04 PM PDT 24 8551421561 ps
T901 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3344268041 Aug 14 04:44:04 PM PDT 24 Aug 14 04:44:05 PM PDT 24 344097806 ps
T902 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3507811302 Aug 14 04:43:14 PM PDT 24 Aug 14 04:43:26 PM PDT 24 11744883963 ps
T903 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3261456848 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:21 PM PDT 24 5597029559 ps
T904 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.816388125 Aug 14 04:43:24 PM PDT 24 Aug 14 04:43:28 PM PDT 24 4671517141 ps
T905 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2266531377 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:20 PM PDT 24 553180555 ps
T906 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2543186977 Aug 14 04:43:27 PM PDT 24 Aug 14 04:43:31 PM PDT 24 936255571 ps
T907 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2149843612 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:18 PM PDT 24 401765917 ps
T908 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.718017415 Aug 14 04:43:18 PM PDT 24 Aug 14 04:43:20 PM PDT 24 479448329 ps
T909 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.307914201 Aug 14 04:43:10 PM PDT 24 Aug 14 04:43:12 PM PDT 24 878434800 ps
T910 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1050311971 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:21 PM PDT 24 736974671 ps
T911 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3803651530 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:19 PM PDT 24 412596956 ps
T912 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2440552221 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:05 PM PDT 24 381339898 ps
T913 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.370997629 Aug 14 04:45:02 PM PDT 24 Aug 14 04:45:03 PM PDT 24 449403897 ps
T914 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3636287152 Aug 14 04:43:29 PM PDT 24 Aug 14 04:43:31 PM PDT 24 557328546 ps
T915 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3027333516 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:23 PM PDT 24 983515079 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1282387285 Aug 14 04:43:34 PM PDT 24 Aug 14 04:43:37 PM PDT 24 1303296325 ps
T917 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3948545610 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:20 PM PDT 24 694914658 ps
T918 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3442782621 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:11 PM PDT 24 868186090 ps
T919 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1169420056 Aug 14 04:43:22 PM PDT 24 Aug 14 04:43:27 PM PDT 24 4175280141 ps
T920 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2305752389 Aug 14 04:43:45 PM PDT 24 Aug 14 04:43:46 PM PDT 24 457198785 ps

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3602874991
Short name T8
Test name
Test status
Simulation time 335021152785 ps
CPU time 829.47 seconds
Started Aug 14 05:20:08 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 202168 kb
Host smart-5757d064-264e-4e11-bc9a-0d6202a238dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602874991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3602874991
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1639667046
Short name T58
Test name
Test status
Simulation time 95209877233 ps
CPU time 315.46 seconds
Started Aug 14 05:19:08 PM PDT 24
Finished Aug 14 05:24:24 PM PDT 24
Peak memory 202368 kb
Host smart-afceee55-a8a6-4b6d-9d0a-842d9009f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639667046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1639667046
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3825522790
Short name T15
Test name
Test status
Simulation time 15290633899 ps
CPU time 15.23 seconds
Started Aug 14 05:17:30 PM PDT 24
Finished Aug 14 05:17:46 PM PDT 24
Peak memory 211836 kb
Host smart-d0455f4b-ecea-45ed-9883-63d89e4a08cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825522790 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3825522790
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2271690469
Short name T253
Test name
Test status
Simulation time 511980156347 ps
CPU time 616.11 seconds
Started Aug 14 05:19:35 PM PDT 24
Finished Aug 14 05:29:51 PM PDT 24
Peak memory 202156 kb
Host smart-bf60c847-b1df-4474-bfaa-c8104d0e72b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271690469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2271690469
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3775407086
Short name T48
Test name
Test status
Simulation time 573823694988 ps
CPU time 699.18 seconds
Started Aug 14 05:17:35 PM PDT 24
Finished Aug 14 05:29:14 PM PDT 24
Peak memory 202132 kb
Host smart-b9c22394-f1b4-4f74-8d5a-53c2b56e7968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775407086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3775407086
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2432269819
Short name T161
Test name
Test status
Simulation time 489485943377 ps
CPU time 267.11 seconds
Started Aug 14 05:20:21 PM PDT 24
Finished Aug 14 05:24:48 PM PDT 24
Peak memory 202100 kb
Host smart-7102043c-f741-44ae-b0ec-d9986ff994c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432269819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2432269819
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.495200958
Short name T63
Test name
Test status
Simulation time 122189130503 ps
CPU time 400.25 seconds
Started Aug 14 05:17:22 PM PDT 24
Finished Aug 14 05:24:02 PM PDT 24
Peak memory 202384 kb
Host smart-900b9e0a-5a2b-4cd4-adda-dc65c145d72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495200958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.495200958
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3213053352
Short name T6
Test name
Test status
Simulation time 325001633097 ps
CPU time 749 seconds
Started Aug 14 05:17:57 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 202176 kb
Host smart-806892b9-10a5-43a7-87fb-b2a286493e5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213053352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3213053352
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2142302275
Short name T160
Test name
Test status
Simulation time 523096864921 ps
CPU time 302.87 seconds
Started Aug 14 05:22:36 PM PDT 24
Finished Aug 14 05:27:39 PM PDT 24
Peak memory 202148 kb
Host smart-2d62dafa-178e-495a-a178-ce441884b849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142302275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2142302275
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3423425112
Short name T171
Test name
Test status
Simulation time 536326768218 ps
CPU time 316.03 seconds
Started Aug 14 05:18:34 PM PDT 24
Finished Aug 14 05:23:50 PM PDT 24
Peak memory 202096 kb
Host smart-57e4a4ff-134e-4e7c-8f1d-898ee651aac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423425112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3423425112
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2875625343
Short name T73
Test name
Test status
Simulation time 529873693 ps
CPU time 2.37 seconds
Started Aug 14 04:43:28 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 201148 kb
Host smart-71eb9042-7e70-4827-8b9c-2dcb60e470fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875625343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2875625343
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3891706616
Short name T155
Test name
Test status
Simulation time 375700994742 ps
CPU time 74.12 seconds
Started Aug 14 05:17:58 PM PDT 24
Finished Aug 14 05:19:12 PM PDT 24
Peak memory 202100 kb
Host smart-4ea42352-80c4-43db-8e03-6390420e83e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891706616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3891706616
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2407721778
Short name T245
Test name
Test status
Simulation time 560186235007 ps
CPU time 689.71 seconds
Started Aug 14 05:21:08 PM PDT 24
Finished Aug 14 05:32:38 PM PDT 24
Peak memory 202164 kb
Host smart-78ab9645-f73b-4e53-b9d0-f22ef0acb336
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407721778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2407721778
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3601412645
Short name T75
Test name
Test status
Simulation time 3878312018 ps
CPU time 8.76 seconds
Started Aug 14 05:17:05 PM PDT 24
Finished Aug 14 05:17:14 PM PDT 24
Peak memory 217480 kb
Host smart-24826c12-7836-48e0-8266-dedc1a5d2a84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601412645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3601412645
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2518172766
Short name T270
Test name
Test status
Simulation time 491559388689 ps
CPU time 279.78 seconds
Started Aug 14 05:17:34 PM PDT 24
Finished Aug 14 05:22:14 PM PDT 24
Peak memory 202136 kb
Host smart-d6ff7929-4cd4-492e-ab8e-9bd5e2bf24c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518172766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2518172766
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.624183137
Short name T11
Test name
Test status
Simulation time 352778205977 ps
CPU time 58.33 seconds
Started Aug 14 05:17:35 PM PDT 24
Finished Aug 14 05:18:33 PM PDT 24
Peak memory 202120 kb
Host smart-04366370-7ba3-42ac-a9c5-b055b86a46d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624183137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.624183137
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1971212515
Short name T184
Test name
Test status
Simulation time 496668975701 ps
CPU time 309.6 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:22:18 PM PDT 24
Peak memory 202172 kb
Host smart-c3d991b0-eee4-42d1-a821-fa7ebbccc8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971212515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1971212515
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1123936191
Short name T254
Test name
Test status
Simulation time 498537542521 ps
CPU time 190.08 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:21:51 PM PDT 24
Peak memory 202116 kb
Host smart-1c4c9aef-8811-4c9b-83f4-8408ec4d663c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123936191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1123936191
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.462494051
Short name T131
Test name
Test status
Simulation time 25268070405 ps
CPU time 75.9 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:44:41 PM PDT 24
Peak memory 201120 kb
Host smart-94e71092-9bca-4996-9e20-fa43c309bef6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462494051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.462494051
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2061728655
Short name T30
Test name
Test status
Simulation time 487878625358 ps
CPU time 279.68 seconds
Started Aug 14 05:20:23 PM PDT 24
Finished Aug 14 05:25:03 PM PDT 24
Peak memory 202132 kb
Host smart-8674047f-ddbf-41c6-971e-bdc10e47d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061728655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2061728655
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3458132067
Short name T210
Test name
Test status
Simulation time 540116682574 ps
CPU time 1257.49 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:38:30 PM PDT 24
Peak memory 202160 kb
Host smart-1c465d31-8afa-449b-bdee-0e4e9ac97912
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458132067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3458132067
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3736553430
Short name T219
Test name
Test status
Simulation time 362526069562 ps
CPU time 217.39 seconds
Started Aug 14 05:17:22 PM PDT 24
Finished Aug 14 05:20:59 PM PDT 24
Peak memory 202152 kb
Host smart-e0674eca-f99b-41b4-87cf-5415938fdbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736553430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3736553430
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3300327970
Short name T27
Test name
Test status
Simulation time 490378490020 ps
CPU time 1180.89 seconds
Started Aug 14 05:21:59 PM PDT 24
Finished Aug 14 05:41:40 PM PDT 24
Peak memory 202108 kb
Host smart-05a233eb-0c60-4410-91e9-e7d7427e4c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300327970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3300327970
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3244478123
Short name T159
Test name
Test status
Simulation time 407353864938 ps
CPU time 106.22 seconds
Started Aug 14 05:19:17 PM PDT 24
Finished Aug 14 05:21:04 PM PDT 24
Peak memory 202104 kb
Host smart-6da1cce4-b919-4924-80a8-4539644dec64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244478123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3244478123
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1751308804
Short name T316
Test name
Test status
Simulation time 550312897831 ps
CPU time 606.72 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:27:30 PM PDT 24
Peak memory 202144 kb
Host smart-a1ac656b-0c3c-41e8-87e9-e65321697c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751308804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1751308804
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3838884603
Short name T163
Test name
Test status
Simulation time 167025320924 ps
CPU time 195.9 seconds
Started Aug 14 05:20:17 PM PDT 24
Finished Aug 14 05:23:33 PM PDT 24
Peak memory 202128 kb
Host smart-e65a0618-b82f-40a5-a8cb-9fdd25a8476c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838884603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3838884603
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1759271428
Short name T41
Test name
Test status
Simulation time 618412001605 ps
CPU time 1423.74 seconds
Started Aug 14 05:18:32 PM PDT 24
Finished Aug 14 05:42:16 PM PDT 24
Peak memory 202100 kb
Host smart-926d92cd-3828-47d6-8e25-09e9b7973bbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759271428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1759271428
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4209953206
Short name T266
Test name
Test status
Simulation time 168554868041 ps
CPU time 152.98 seconds
Started Aug 14 05:20:49 PM PDT 24
Finished Aug 14 05:23:22 PM PDT 24
Peak memory 202156 kb
Host smart-1146bfea-4da5-457e-96e0-0c1035972f0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209953206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4209953206
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4085054592
Short name T205
Test name
Test status
Simulation time 539751070561 ps
CPU time 116.83 seconds
Started Aug 14 05:18:12 PM PDT 24
Finished Aug 14 05:20:09 PM PDT 24
Peak memory 202080 kb
Host smart-a224aa25-e22c-4f5b-8301-423b7195d02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085054592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4085054592
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2164707157
Short name T60
Test name
Test status
Simulation time 923060301653 ps
CPU time 982.64 seconds
Started Aug 14 05:22:45 PM PDT 24
Finished Aug 14 05:39:08 PM PDT 24
Peak memory 212636 kb
Host smart-46fbd816-2df3-405e-a3fd-cd59904f94da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164707157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2164707157
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1004869165
Short name T213
Test name
Test status
Simulation time 661172215365 ps
CPU time 375.61 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:23:43 PM PDT 24
Peak memory 202196 kb
Host smart-c479c640-a89d-411b-b1d5-0416d84f4d02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004869165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1004869165
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.4011191436
Short name T410
Test name
Test status
Simulation time 336025525 ps
CPU time 0.85 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:17:08 PM PDT 24
Peak memory 201888 kb
Host smart-9992c8c5-9354-42a5-8e19-e2249f6438f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011191436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4011191436
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2814467033
Short name T289
Test name
Test status
Simulation time 358738853434 ps
CPU time 793.99 seconds
Started Aug 14 05:21:33 PM PDT 24
Finished Aug 14 05:34:47 PM PDT 24
Peak memory 202192 kb
Host smart-c21c9192-89b3-4cb4-9fa8-0cfb66fa1908
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814467033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2814467033
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3104850809
Short name T169
Test name
Test status
Simulation time 402610524168 ps
CPU time 444.56 seconds
Started Aug 14 05:19:20 PM PDT 24
Finished Aug 14 05:26:44 PM PDT 24
Peak memory 202156 kb
Host smart-88923f5f-6bd0-4bf5-afb8-04413d6bc2b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104850809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3104850809
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.529814656
Short name T281
Test name
Test status
Simulation time 522894530486 ps
CPU time 719.98 seconds
Started Aug 14 05:20:02 PM PDT 24
Finished Aug 14 05:32:02 PM PDT 24
Peak memory 202116 kb
Host smart-4d2a15fc-134b-4b06-bef7-3c9b3870a5fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529814656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.529814656
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1338579408
Short name T74
Test name
Test status
Simulation time 4448035915 ps
CPU time 9.65 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 201164 kb
Host smart-bc806a8a-66a6-42f0-b11b-848f2dd19844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338579408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1338579408
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.55803842
Short name T173
Test name
Test status
Simulation time 521369721997 ps
CPU time 777.54 seconds
Started Aug 14 05:17:13 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 202052 kb
Host smart-9dfc7186-77f7-42dd-b08e-5588b0a109bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55803842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating
.55803842
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3180568684
Short name T302
Test name
Test status
Simulation time 328922309666 ps
CPU time 331.95 seconds
Started Aug 14 05:19:11 PM PDT 24
Finished Aug 14 05:24:43 PM PDT 24
Peak memory 202156 kb
Host smart-2ff15bba-77df-4de6-b038-7fc83c18f997
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180568684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3180568684
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3934703649
Short name T285
Test name
Test status
Simulation time 615978694586 ps
CPU time 1458.28 seconds
Started Aug 14 05:19:43 PM PDT 24
Finished Aug 14 05:44:01 PM PDT 24
Peak memory 202184 kb
Host smart-2fdbecf4-cc47-4116-bb56-fcc7ec6a49c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934703649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3934703649
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.948765571
Short name T257
Test name
Test status
Simulation time 181944017775 ps
CPU time 368.73 seconds
Started Aug 14 05:22:00 PM PDT 24
Finished Aug 14 05:28:09 PM PDT 24
Peak memory 202128 kb
Host smart-b5056b60-4e71-4e85-8830-4802852f0f4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948765571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.948765571
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.922447873
Short name T295
Test name
Test status
Simulation time 89562437209 ps
CPU time 32.64 seconds
Started Aug 14 05:22:46 PM PDT 24
Finished Aug 14 05:23:19 PM PDT 24
Peak memory 210764 kb
Host smart-072ab136-3917-47b8-9e12-94d64482fc3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922447873 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.922447873
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1330205773
Short name T43
Test name
Test status
Simulation time 538729656763 ps
CPU time 1184.28 seconds
Started Aug 14 05:18:50 PM PDT 24
Finished Aug 14 05:38:35 PM PDT 24
Peak memory 202304 kb
Host smart-ff1b9e85-94e4-4a23-97f5-6d11e222d62a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330205773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1330205773
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.146331427
Short name T99
Test name
Test status
Simulation time 333726323904 ps
CPU time 728.49 seconds
Started Aug 14 05:20:01 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 202028 kb
Host smart-e1c64c1d-c1c9-4cbf-9a36-294946b4f50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146331427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.146331427
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2733073165
Short name T294
Test name
Test status
Simulation time 588048272119 ps
CPU time 595.75 seconds
Started Aug 14 05:17:06 PM PDT 24
Finished Aug 14 05:27:02 PM PDT 24
Peak memory 210588 kb
Host smart-a41b3bf8-bd70-4c7c-a64f-2ca8bef5f5b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733073165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2733073165
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3574693278
Short name T330
Test name
Test status
Simulation time 515132616550 ps
CPU time 520.58 seconds
Started Aug 14 05:18:23 PM PDT 24
Finished Aug 14 05:27:04 PM PDT 24
Peak memory 202148 kb
Host smart-79a29782-43ca-4d98-90e2-07347f2b267b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574693278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3574693278
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2542423982
Short name T202
Test name
Test status
Simulation time 368639468554 ps
CPU time 217.61 seconds
Started Aug 14 05:18:28 PM PDT 24
Finished Aug 14 05:22:05 PM PDT 24
Peak memory 202148 kb
Host smart-30eadaef-59a5-498c-baf1-8efc3009fbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542423982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2542423982
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2971485105
Short name T262
Test name
Test status
Simulation time 372916184665 ps
CPU time 807.47 seconds
Started Aug 14 05:20:50 PM PDT 24
Finished Aug 14 05:34:18 PM PDT 24
Peak memory 202148 kb
Host smart-7ced0e61-cdcf-4069-b56c-5ff133b02eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971485105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2971485105
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2787788813
Short name T148
Test name
Test status
Simulation time 360544960 ps
CPU time 1.14 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 200928 kb
Host smart-45bea3fb-515c-47e0-8376-07c323d2564b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787788813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2787788813
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1546505583
Short name T282
Test name
Test status
Simulation time 164341256957 ps
CPU time 184.51 seconds
Started Aug 14 05:18:06 PM PDT 24
Finished Aug 14 05:21:10 PM PDT 24
Peak memory 202124 kb
Host smart-30ba6673-76be-40dc-b1b4-568e60af474d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546505583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1546505583
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3929647735
Short name T209
Test name
Test status
Simulation time 165879887645 ps
CPU time 400.63 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:26:07 PM PDT 24
Peak memory 202156 kb
Host smart-a15ea9a3-e10a-4921-b64e-ba1eb0b4cbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929647735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3929647735
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2771933346
Short name T175
Test name
Test status
Simulation time 597903436811 ps
CPU time 347.75 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:22:47 PM PDT 24
Peak memory 202144 kb
Host smart-3b989f74-aeeb-4ab5-84b0-2e0232061a3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771933346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2771933346
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1438788704
Short name T130
Test name
Test status
Simulation time 168782184750 ps
CPU time 117.39 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:18:55 PM PDT 24
Peak memory 202128 kb
Host smart-b299048d-94d3-4f63-8e99-83664c146927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438788704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1438788704
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.199542769
Short name T350
Test name
Test status
Simulation time 513044447597 ps
CPU time 1117.1 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:36:36 PM PDT 24
Peak memory 202164 kb
Host smart-aefe23be-43d8-41a5-a560-70e5f3d5e6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199542769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.199542769
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.700395139
Short name T47
Test name
Test status
Simulation time 93335434884 ps
CPU time 302.38 seconds
Started Aug 14 05:21:01 PM PDT 24
Finished Aug 14 05:26:03 PM PDT 24
Peak memory 202384 kb
Host smart-32305901-6169-4ec0-b0e4-f438aef4f2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700395139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.700395139
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.9981878
Short name T4
Test name
Test status
Simulation time 198971625263 ps
CPU time 117.23 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:19:29 PM PDT 24
Peak memory 202196 kb
Host smart-6bbff10b-b506-4524-bfe5-3b6b51d9981d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9981878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.9981878
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3642768325
Short name T324
Test name
Test status
Simulation time 489187016719 ps
CPU time 1105.3 seconds
Started Aug 14 05:19:17 PM PDT 24
Finished Aug 14 05:37:43 PM PDT 24
Peak memory 202132 kb
Host smart-f2024601-584f-49bd-b49a-5a9c4b9f3963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642768325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3642768325
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3431332681
Short name T300
Test name
Test status
Simulation time 168243127928 ps
CPU time 405.68 seconds
Started Aug 14 05:19:38 PM PDT 24
Finished Aug 14 05:26:24 PM PDT 24
Peak memory 202224 kb
Host smart-03f3f186-0f67-4418-88c1-0c64ffd47357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431332681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3431332681
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1926593878
Short name T345
Test name
Test status
Simulation time 161634214891 ps
CPU time 343.19 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:25:09 PM PDT 24
Peak memory 202164 kb
Host smart-744549e5-066f-4ec4-911f-9fe150d50aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926593878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1926593878
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1786371353
Short name T17
Test name
Test status
Simulation time 205814910329 ps
CPU time 42.04 seconds
Started Aug 14 05:17:24 PM PDT 24
Finished Aug 14 05:18:06 PM PDT 24
Peak memory 210708 kb
Host smart-ac8fdf6d-9b5a-4b18-a393-9f914e9f546d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786371353 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1786371353
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2348842063
Short name T180
Test name
Test status
Simulation time 165294062925 ps
CPU time 197.95 seconds
Started Aug 14 05:19:53 PM PDT 24
Finished Aug 14 05:23:11 PM PDT 24
Peak memory 202196 kb
Host smart-9988a968-aed6-4508-ba75-b43f05262514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348842063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2348842063
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1744924725
Short name T287
Test name
Test status
Simulation time 159133171990 ps
CPU time 95.59 seconds
Started Aug 14 05:21:33 PM PDT 24
Finished Aug 14 05:23:09 PM PDT 24
Peak memory 202152 kb
Host smart-b7cfb702-acc4-4447-8aa2-867ea8577837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744924725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1744924725
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.717504949
Short name T334
Test name
Test status
Simulation time 356035892627 ps
CPU time 237.48 seconds
Started Aug 14 05:22:26 PM PDT 24
Finished Aug 14 05:26:24 PM PDT 24
Peak memory 202124 kb
Host smart-c8634317-1f4b-4fca-a8d0-8abb7ad1518d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717504949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.717504949
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2747831312
Short name T817
Test name
Test status
Simulation time 541621967 ps
CPU time 3.02 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 210432 kb
Host smart-1edc2746-7032-4a29-817e-1e60b38d60ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747831312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2747831312
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.906950309
Short name T422
Test name
Test status
Simulation time 163530241360 ps
CPU time 108.66 seconds
Started Aug 14 05:17:00 PM PDT 24
Finished Aug 14 05:18:48 PM PDT 24
Peak memory 202200 kb
Host smart-868b7deb-a034-4622-997e-84230e77e91c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=906950309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.906950309
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1765453729
Short name T242
Test name
Test status
Simulation time 267971118918 ps
CPU time 149.45 seconds
Started Aug 14 05:18:13 PM PDT 24
Finished Aug 14 05:20:43 PM PDT 24
Peak memory 202048 kb
Host smart-4be52417-9efa-4158-9000-f1ea6c871e44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765453729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1765453729
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.162548079
Short name T241
Test name
Test status
Simulation time 336248508884 ps
CPU time 405.38 seconds
Started Aug 14 05:18:25 PM PDT 24
Finished Aug 14 05:25:11 PM PDT 24
Peak memory 202132 kb
Host smart-04e3d43e-fe7c-42be-b748-54ee70164505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162548079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.162548079
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1694425431
Short name T677
Test name
Test status
Simulation time 504299825255 ps
CPU time 326.62 seconds
Started Aug 14 05:18:51 PM PDT 24
Finished Aug 14 05:24:18 PM PDT 24
Peak memory 202144 kb
Host smart-6480c224-6226-40e0-9c29-a57e512b8141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694425431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1694425431
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.4246911767
Short name T249
Test name
Test status
Simulation time 333547791432 ps
CPU time 144.55 seconds
Started Aug 14 05:17:31 PM PDT 24
Finished Aug 14 05:19:56 PM PDT 24
Peak memory 202108 kb
Host smart-2a775d29-dfc0-4e70-b4a8-d01401f4ae31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246911767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.4246911767
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2767805983
Short name T368
Test name
Test status
Simulation time 8725021303 ps
CPU time 12.36 seconds
Started Aug 14 04:43:34 PM PDT 24
Finished Aug 14 04:43:47 PM PDT 24
Peak memory 201112 kb
Host smart-ae024466-7d27-427f-9c1a-2dd6a21b68fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767805983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2767805983
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.958309331
Short name T299
Test name
Test status
Simulation time 534723222276 ps
CPU time 40.77 seconds
Started Aug 14 05:18:13 PM PDT 24
Finished Aug 14 05:18:54 PM PDT 24
Peak memory 202124 kb
Host smart-66cc1916-a1af-496e-af60-02e066d019bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958309331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.958309331
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3632530446
Short name T237
Test name
Test status
Simulation time 133688150584 ps
CPU time 671.18 seconds
Started Aug 14 05:18:25 PM PDT 24
Finished Aug 14 05:29:36 PM PDT 24
Peak memory 202420 kb
Host smart-a2783b23-24de-4cbe-973f-4976f5b6e498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632530446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3632530446
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2738343229
Short name T756
Test name
Test status
Simulation time 93285711136 ps
CPU time 335.86 seconds
Started Aug 14 05:18:42 PM PDT 24
Finished Aug 14 05:24:18 PM PDT 24
Peak memory 202436 kb
Host smart-c44d9f52-fec4-408f-a9ed-9f2ef493e970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738343229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2738343229
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.410056580
Short name T181
Test name
Test status
Simulation time 337368826170 ps
CPU time 808.67 seconds
Started Aug 14 05:18:40 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 202060 kb
Host smart-1837e296-2c4c-4fd2-b8ce-0b918abf668b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410056580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.410056580
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1635029123
Short name T255
Test name
Test status
Simulation time 520699328381 ps
CPU time 90.51 seconds
Started Aug 14 05:19:10 PM PDT 24
Finished Aug 14 05:20:41 PM PDT 24
Peak memory 202156 kb
Host smart-1f7d1996-c310-4190-b13c-c5e5558dc90e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635029123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1635029123
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2714815385
Short name T351
Test name
Test status
Simulation time 562954212040 ps
CPU time 609.85 seconds
Started Aug 14 05:19:18 PM PDT 24
Finished Aug 14 05:29:28 PM PDT 24
Peak memory 202076 kb
Host smart-4126ad6e-6bd5-4fe2-b17f-a98168b81d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714815385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2714815385
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.564473466
Short name T263
Test name
Test status
Simulation time 325038263160 ps
CPU time 96.35 seconds
Started Aug 14 05:20:32 PM PDT 24
Finished Aug 14 05:22:09 PM PDT 24
Peak memory 202128 kb
Host smart-0609ccb2-09f1-416e-8ab8-520d52e87c4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564473466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.564473466
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1730619823
Short name T31
Test name
Test status
Simulation time 94895920356 ps
CPU time 392.99 seconds
Started Aug 14 05:20:34 PM PDT 24
Finished Aug 14 05:27:07 PM PDT 24
Peak memory 202448 kb
Host smart-4d332a5a-fcd6-4ea4-95b7-11d47566f7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730619823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1730619823
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2630076868
Short name T357
Test name
Test status
Simulation time 362096215379 ps
CPU time 200.8 seconds
Started Aug 14 05:20:41 PM PDT 24
Finished Aug 14 05:24:02 PM PDT 24
Peak memory 202128 kb
Host smart-2bccb376-aba1-470c-8e43-fb9b70eec178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630076868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2630076868
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3325947983
Short name T182
Test name
Test status
Simulation time 483635689965 ps
CPU time 1103.14 seconds
Started Aug 14 05:17:41 PM PDT 24
Finished Aug 14 05:36:04 PM PDT 24
Peak memory 202112 kb
Host smart-dfb70255-8b01-48f7-89f8-df0277027748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325947983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3325947983
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3261456848
Short name T903
Test name
Test status
Simulation time 5597029559 ps
CPU time 2.3 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 201188 kb
Host smart-73f0575e-d09c-45db-ab7c-6cc8c9b4c745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261456848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3261456848
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3239373710
Short name T377
Test name
Test status
Simulation time 95795064704 ps
CPU time 482.3 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:25:02 PM PDT 24
Peak memory 202412 kb
Host smart-7a0d2613-f45a-4bdf-bf6a-48a452ac02b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239373710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3239373710
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.498217910
Short name T283
Test name
Test status
Simulation time 169288330126 ps
CPU time 108.5 seconds
Started Aug 14 05:17:49 PM PDT 24
Finished Aug 14 05:19:38 PM PDT 24
Peak memory 202120 kb
Host smart-b930a6c3-82e8-4d7d-a19c-3f99eb32d18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498217910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.498217910
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1807027046
Short name T314
Test name
Test status
Simulation time 487471534149 ps
CPU time 270.76 seconds
Started Aug 14 05:18:06 PM PDT 24
Finished Aug 14 05:22:37 PM PDT 24
Peak memory 202172 kb
Host smart-eab8340d-320f-46ba-a7a7-bed1d8b7e258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807027046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1807027046
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3692382005
Short name T271
Test name
Test status
Simulation time 166828735993 ps
CPU time 390.2 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:24:54 PM PDT 24
Peak memory 202208 kb
Host smart-326b45ae-6901-4b4d-8c54-e7d8c4b42942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692382005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3692382005
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1824636474
Short name T360
Test name
Test status
Simulation time 165395553467 ps
CPU time 159.89 seconds
Started Aug 14 05:18:37 PM PDT 24
Finished Aug 14 05:21:17 PM PDT 24
Peak memory 202148 kb
Host smart-e36bce1b-4e12-475d-b304-e379616fa16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824636474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1824636474
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4279316747
Short name T228
Test name
Test status
Simulation time 90658670802 ps
CPU time 310.55 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:24:11 PM PDT 24
Peak memory 202444 kb
Host smart-7ff88649-f8f5-4429-8df6-4fb67adca59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279316747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4279316747
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3497435691
Short name T258
Test name
Test status
Simulation time 160255810602 ps
CPU time 205.88 seconds
Started Aug 14 05:20:08 PM PDT 24
Finished Aug 14 05:23:34 PM PDT 24
Peak memory 202092 kb
Host smart-9cf5318d-7080-4e4b-8c66-a1010aa9df10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497435691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3497435691
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3474250882
Short name T318
Test name
Test status
Simulation time 179192916132 ps
CPU time 412.58 seconds
Started Aug 14 05:20:58 PM PDT 24
Finished Aug 14 05:27:50 PM PDT 24
Peak memory 202164 kb
Host smart-be672aaa-529a-40c8-859d-9c757523fee2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474250882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3474250882
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1072307056
Short name T306
Test name
Test status
Simulation time 199924701750 ps
CPU time 447.5 seconds
Started Aug 14 05:21:24 PM PDT 24
Finished Aug 14 05:28:52 PM PDT 24
Peak memory 202212 kb
Host smart-89e54c81-ba19-4d4b-b21c-ebafe6788819
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072307056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1072307056
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.60292677
Short name T264
Test name
Test status
Simulation time 736438403308 ps
CPU time 1137.65 seconds
Started Aug 14 05:21:54 PM PDT 24
Finished Aug 14 05:40:51 PM PDT 24
Peak memory 202176 kb
Host smart-f32eb604-4408-479d-b771-78dc5dff14b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60292677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.60292677
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.319887500
Short name T323
Test name
Test status
Simulation time 162921179604 ps
CPU time 353.24 seconds
Started Aug 14 05:22:15 PM PDT 24
Finished Aug 14 05:28:08 PM PDT 24
Peak memory 202196 kb
Host smart-de5da087-7ec1-4578-bf34-fb884f0fdb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319887500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.319887500
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2888800753
Short name T39
Test name
Test status
Simulation time 136080740375 ps
CPU time 739.68 seconds
Started Aug 14 05:22:13 PM PDT 24
Finished Aug 14 05:34:33 PM PDT 24
Peak memory 202392 kb
Host smart-1e1034cf-e24a-4871-9300-c7f86ade8426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888800753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2888800753
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3747222665
Short name T162
Test name
Test status
Simulation time 555773157604 ps
CPU time 133.62 seconds
Started Aug 14 05:22:35 PM PDT 24
Finished Aug 14 05:24:49 PM PDT 24
Peak memory 202148 kb
Host smart-af24e359-637f-4a97-8cc7-87914f25e521
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747222665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3747222665
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3992777362
Short name T372
Test name
Test status
Simulation time 109556000177 ps
CPU time 428.81 seconds
Started Aug 14 05:17:41 PM PDT 24
Finished Aug 14 05:24:50 PM PDT 24
Peak memory 202388 kb
Host smart-23ed43ef-d9e0-4937-a00c-00c87eccb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992777362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3992777362
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3960598267
Short name T888
Test name
Test status
Simulation time 657782435 ps
CPU time 2.76 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 201172 kb
Host smart-a61c47b5-fee2-4a92-9b2e-5edbf83a81b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960598267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3960598267
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.475585004
Short name T138
Test name
Test status
Simulation time 42053853897 ps
CPU time 92.63 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:44:51 PM PDT 24
Peak memory 201264 kb
Host smart-3cc13e16-3a90-45ca-bff9-b52cbfcf1e76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475585004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.475585004
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3494783287
Short name T840
Test name
Test status
Simulation time 735001220 ps
CPU time 1.1 seconds
Started Aug 14 04:43:26 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 200980 kb
Host smart-b2c555c0-1c7b-463c-8e0b-4d8f1e513e8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494783287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3494783287
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.412302786
Short name T862
Test name
Test status
Simulation time 502543583 ps
CPU time 1.22 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 201064 kb
Host smart-7e44bc06-1223-4ae6-a273-0e3b89149e5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412302786 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.412302786
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2807940549
Short name T848
Test name
Test status
Simulation time 366696394 ps
CPU time 0.79 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:16 PM PDT 24
Peak memory 200984 kb
Host smart-266442d1-815f-4cb8-a4e5-c6fd8ea0b537
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807940549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2807940549
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2625679065
Short name T852
Test name
Test status
Simulation time 347623833 ps
CPU time 1.01 seconds
Started Aug 14 04:43:34 PM PDT 24
Finished Aug 14 04:43:35 PM PDT 24
Peak memory 200844 kb
Host smart-48a5ac68-0cb5-49c5-8e07-ea0452b8eeeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625679065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2625679065
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4190170257
Short name T836
Test name
Test status
Simulation time 5709052201 ps
CPU time 4.22 seconds
Started Aug 14 04:43:32 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 201188 kb
Host smart-1a01438f-4ba2-45eb-a7d0-f092d6d9cdee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190170257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.4190170257
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4112353526
Short name T889
Test name
Test status
Simulation time 519854303 ps
CPU time 2.39 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 201228 kb
Host smart-b7fa21cf-e345-4ca6-99e0-c57c2b514ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112353526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4112353526
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2543186977
Short name T906
Test name
Test status
Simulation time 936255571 ps
CPU time 4.08 seconds
Started Aug 14 04:43:27 PM PDT 24
Finished Aug 14 04:43:31 PM PDT 24
Peak memory 201144 kb
Host smart-4257b623-72e7-4f89-8d59-9bc35d89af84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543186977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2543186977
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3442782621
Short name T918
Test name
Test status
Simulation time 868186090 ps
CPU time 2.6 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 200956 kb
Host smart-f8328e7f-66f3-4b76-96d2-eec38d83913a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442782621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3442782621
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1334272645
Short name T87
Test name
Test status
Simulation time 530975386 ps
CPU time 0.96 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:43:16 PM PDT 24
Peak memory 200968 kb
Host smart-9124f225-40be-495b-9ed4-3235850d9afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334272645 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1334272645
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1515012830
Short name T833
Test name
Test status
Simulation time 395949784 ps
CPU time 1.46 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 200912 kb
Host smart-f55c96af-982f-4eb6-a365-d03236d2db0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515012830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1515012830
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2519097442
Short name T850
Test name
Test status
Simulation time 3043246670 ps
CPU time 7.61 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 201136 kb
Host smart-ee9ef4c8-6b5e-4a79-95c0-35c7b39ae171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519097442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2519097442
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.718017415
Short name T908
Test name
Test status
Simulation time 479448329 ps
CPU time 2.1 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 201264 kb
Host smart-a9a7bfd1-3e67-4f1f-ba94-4fc020e50255
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718017415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.718017415
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3219410162
Short name T866
Test name
Test status
Simulation time 431448082 ps
CPU time 1.76 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 201048 kb
Host smart-9d2bb6ac-2c76-45e7-ac99-63233a424afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219410162 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3219410162
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1221841140
Short name T132
Test name
Test status
Simulation time 343660149 ps
CPU time 1.63 seconds
Started Aug 14 04:43:45 PM PDT 24
Finished Aug 14 04:43:47 PM PDT 24
Peak memory 200928 kb
Host smart-c51debe3-9a96-4c6a-a2ed-4f3e4a2bc66d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221841140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1221841140
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4035732428
Short name T857
Test name
Test status
Simulation time 353035505 ps
CPU time 1.42 seconds
Started Aug 14 04:43:26 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 200848 kb
Host smart-727708e9-402f-4c4d-950a-f5133b820c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035732428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4035732428
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.870037318
Short name T883
Test name
Test status
Simulation time 2439382208 ps
CPU time 9.84 seconds
Started Aug 14 04:43:32 PM PDT 24
Finished Aug 14 04:43:42 PM PDT 24
Peak memory 201020 kb
Host smart-c1426de1-e049-4f8e-86b8-c920a530b3d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870037318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.870037318
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2334434449
Short name T865
Test name
Test status
Simulation time 747477598 ps
CPU time 1.7 seconds
Started Aug 14 04:43:31 PM PDT 24
Finished Aug 14 04:43:33 PM PDT 24
Peak memory 201168 kb
Host smart-632c6b41-5be4-4b1e-915c-b6e90c23bcd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334434449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2334434449
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1015848503
Short name T900
Test name
Test status
Simulation time 8551421561 ps
CPU time 7.46 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:44:04 PM PDT 24
Peak memory 201224 kb
Host smart-62fc6282-edc3-4761-b461-37998da47899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015848503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1015848503
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.306892823
Short name T807
Test name
Test status
Simulation time 428355224 ps
CPU time 1.17 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 201000 kb
Host smart-2523d091-7880-4ed1-8c81-0c2ab5ca6eea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306892823 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.306892823
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4138912822
Short name T134
Test name
Test status
Simulation time 436590955 ps
CPU time 0.78 seconds
Started Aug 14 04:43:34 PM PDT 24
Finished Aug 14 04:43:35 PM PDT 24
Peak memory 200988 kb
Host smart-714b4330-928b-4fdb-b7e0-1f35f9825ab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138912822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.4138912822
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2662520305
Short name T799
Test name
Test status
Simulation time 412717313 ps
CPU time 1.56 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:43:41 PM PDT 24
Peak memory 200804 kb
Host smart-3fc2e803-5765-46d5-9f33-fddc955b0229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662520305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2662520305
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.720354663
Short name T65
Test name
Test status
Simulation time 4502204866 ps
CPU time 3.54 seconds
Started Aug 14 04:43:22 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 201120 kb
Host smart-9e530af0-08ef-4296-9ec5-11e1d3428f00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720354663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.720354663
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3852150122
Short name T81
Test name
Test status
Simulation time 820959150 ps
CPU time 1.84 seconds
Started Aug 14 04:43:28 PM PDT 24
Finished Aug 14 04:43:30 PM PDT 24
Peak memory 201232 kb
Host smart-7aa7d78d-db25-4055-923a-8ce2e46dc8d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852150122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3852150122
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3402554116
Short name T370
Test name
Test status
Simulation time 8823224188 ps
CPU time 16.34 seconds
Started Aug 14 04:43:30 PM PDT 24
Finished Aug 14 04:43:47 PM PDT 24
Peak memory 201236 kb
Host smart-78c4216a-43c1-4f36-9a63-2f20d2e05300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402554116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3402554116
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2200592481
Short name T819
Test name
Test status
Simulation time 591300502 ps
CPU time 1.17 seconds
Started Aug 14 04:43:31 PM PDT 24
Finished Aug 14 04:43:32 PM PDT 24
Peak memory 201048 kb
Host smart-aed1434a-4043-4367-94e3-43391889d43c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200592481 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2200592481
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3480154378
Short name T143
Test name
Test status
Simulation time 384583637 ps
CPU time 0.89 seconds
Started Aug 14 04:43:44 PM PDT 24
Finished Aug 14 04:43:45 PM PDT 24
Peak memory 200916 kb
Host smart-1a2472a1-1359-4b95-8ddb-93d5497de1f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480154378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3480154378
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1674647934
Short name T823
Test name
Test status
Simulation time 398989299 ps
CPU time 1.15 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 200828 kb
Host smart-d7ebdef0-7018-4baa-a485-19e7fb069618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674647934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1674647934
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.589841060
Short name T898
Test name
Test status
Simulation time 4828580844 ps
CPU time 11.14 seconds
Started Aug 14 04:43:37 PM PDT 24
Finished Aug 14 04:43:48 PM PDT 24
Peak memory 201172 kb
Host smart-c9e4b38a-f685-4233-847f-9a381a5c8d73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589841060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.589841060
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2959725921
Short name T71
Test name
Test status
Simulation time 4091707168 ps
CPU time 4.13 seconds
Started Aug 14 04:43:40 PM PDT 24
Finished Aug 14 04:43:44 PM PDT 24
Peak memory 201196 kb
Host smart-ac736933-7fbb-4dac-8c7c-23f22627a648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959725921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2959725921
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3163053405
Short name T806
Test name
Test status
Simulation time 523064935 ps
CPU time 1.44 seconds
Started Aug 14 04:43:37 PM PDT 24
Finished Aug 14 04:43:39 PM PDT 24
Peak memory 201028 kb
Host smart-4f66fa0c-d59b-4719-be79-bf94f31b15fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163053405 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3163053405
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3165209704
Short name T893
Test name
Test status
Simulation time 344930478 ps
CPU time 1.53 seconds
Started Aug 14 04:43:23 PM PDT 24
Finished Aug 14 04:43:25 PM PDT 24
Peak memory 200908 kb
Host smart-ea1963a3-1f2b-46cc-9583-1d57ca263d0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165209704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3165209704
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2294828040
Short name T882
Test name
Test status
Simulation time 489338405 ps
CPU time 0.68 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:30 PM PDT 24
Peak memory 200856 kb
Host smart-32215cd9-4b3d-4e95-acb5-640938f9371a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294828040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2294828040
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.950887693
Short name T835
Test name
Test status
Simulation time 6113087531 ps
CPU time 4.17 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 201172 kb
Host smart-59f6973a-b549-4c7f-995b-7afd64f494b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950887693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.950887693
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3460410996
Short name T864
Test name
Test status
Simulation time 464441551 ps
CPU time 2.36 seconds
Started Aug 14 04:43:44 PM PDT 24
Finished Aug 14 04:43:46 PM PDT 24
Peak memory 201412 kb
Host smart-182c91d5-9a67-4793-b04d-69f6f4a99845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460410996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3460410996
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4076662629
Short name T802
Test name
Test status
Simulation time 4741440893 ps
CPU time 6.9 seconds
Started Aug 14 04:43:30 PM PDT 24
Finished Aug 14 04:43:37 PM PDT 24
Peak memory 201188 kb
Host smart-d3ad3ade-04e1-4f85-a556-206d72d53dc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076662629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.4076662629
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.717397607
Short name T871
Test name
Test status
Simulation time 665306743 ps
CPU time 1.41 seconds
Started Aug 14 04:43:35 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 200852 kb
Host smart-1d3cec95-6044-42be-bebc-52c2d932c577
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717397607 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.717397607
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.415994666
Short name T136
Test name
Test status
Simulation time 404947853 ps
CPU time 1.85 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 200928 kb
Host smart-c8a8460d-0f3f-40a7-8426-a6311184a0bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415994666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.415994666
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1353137356
Short name T813
Test name
Test status
Simulation time 549253838 ps
CPU time 0.94 seconds
Started Aug 14 04:43:26 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 200896 kb
Host smart-13d67126-0c85-4c4e-8cf9-9c1f060f106d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353137356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1353137356
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.506852511
Short name T67
Test name
Test status
Simulation time 4567741449 ps
CPU time 4.65 seconds
Started Aug 14 04:43:48 PM PDT 24
Finished Aug 14 04:43:53 PM PDT 24
Peak memory 201208 kb
Host smart-ead6b629-5149-4d8a-b0d2-b7d158585082
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506852511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.506852511
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3761306531
Short name T85
Test name
Test status
Simulation time 571276661 ps
CPU time 2.31 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 209408 kb
Host smart-eb524a01-87d7-4b8e-86c2-6c87ec81b5fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761306531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3761306531
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4013885268
Short name T369
Test name
Test status
Simulation time 4434204936 ps
CPU time 3.14 seconds
Started Aug 14 04:43:32 PM PDT 24
Finished Aug 14 04:43:35 PM PDT 24
Peak memory 201148 kb
Host smart-e4be9ce0-b503-4045-91ba-9b1d4c270d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013885268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4013885268
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3243787476
Short name T894
Test name
Test status
Simulation time 476216047 ps
CPU time 1.51 seconds
Started Aug 14 04:43:45 PM PDT 24
Finished Aug 14 04:43:46 PM PDT 24
Peak memory 201048 kb
Host smart-db83f863-e622-46db-b61a-188d6528e0cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243787476 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3243787476
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.948175473
Short name T133
Test name
Test status
Simulation time 381972999 ps
CPU time 1.27 seconds
Started Aug 14 04:43:21 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 200984 kb
Host smart-875b6629-20eb-4454-a70d-e8f13ebd36ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948175473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.948175473
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3824356483
Short name T841
Test name
Test status
Simulation time 493230358 ps
CPU time 1.4 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:43:40 PM PDT 24
Peak memory 200816 kb
Host smart-52a500be-79f0-4df7-bd01-95e1b1686cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824356483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3824356483
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1954629679
Short name T896
Test name
Test status
Simulation time 2116627155 ps
CPU time 2.53 seconds
Started Aug 14 04:43:28 PM PDT 24
Finished Aug 14 04:43:30 PM PDT 24
Peak memory 200948 kb
Host smart-a6c0f016-b043-436e-8f1b-608b63bb93bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954629679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1954629679
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.368971239
Short name T834
Test name
Test status
Simulation time 679007628 ps
CPU time 2.6 seconds
Started Aug 14 04:43:33 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 201232 kb
Host smart-5bad8d7e-09f8-43f9-b504-f3f29dedb673
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368971239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.368971239
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3263089864
Short name T78
Test name
Test status
Simulation time 354885552 ps
CPU time 1 seconds
Started Aug 14 04:43:34 PM PDT 24
Finished Aug 14 04:43:35 PM PDT 24
Peak memory 201060 kb
Host smart-e56b8f3d-21c5-416f-9b8f-8386824c150f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263089864 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3263089864
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3953104640
Short name T863
Test name
Test status
Simulation time 375807544 ps
CPU time 1.03 seconds
Started Aug 14 04:43:40 PM PDT 24
Finished Aug 14 04:43:41 PM PDT 24
Peak memory 200972 kb
Host smart-aaf709b2-350f-4659-b12f-d2f787ce855b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953104640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3953104640
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2947121573
Short name T874
Test name
Test status
Simulation time 513881918 ps
CPU time 0.96 seconds
Started Aug 14 04:43:37 PM PDT 24
Finished Aug 14 04:43:38 PM PDT 24
Peak memory 200880 kb
Host smart-517818dc-407d-45c3-b7b8-fe24c7b56111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947121573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2947121573
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.217976696
Short name T891
Test name
Test status
Simulation time 2555785811 ps
CPU time 1.9 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 201024 kb
Host smart-cac3bc5d-7b05-462a-9277-da7d39f3d4b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217976696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.217976696
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3027333516
Short name T915
Test name
Test status
Simulation time 983515079 ps
CPU time 2.92 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 217104 kb
Host smart-e2c56ff2-11fe-40db-a270-11dc1ebfc078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027333516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3027333516
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.95671850
Short name T70
Test name
Test status
Simulation time 4348806401 ps
CPU time 11.7 seconds
Started Aug 14 04:43:58 PM PDT 24
Finished Aug 14 04:44:10 PM PDT 24
Peak memory 201152 kb
Host smart-d810c483-046f-4ab8-b963-dd76f0be8cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95671850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_int
g_err.95671850
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3724276915
Short name T803
Test name
Test status
Simulation time 457842635 ps
CPU time 0.96 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 201048 kb
Host smart-0d3fb4c8-6fb4-4801-90be-0360cd841e8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724276915 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3724276915
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2305752389
Short name T920
Test name
Test status
Simulation time 457198785 ps
CPU time 1.35 seconds
Started Aug 14 04:43:45 PM PDT 24
Finished Aug 14 04:43:46 PM PDT 24
Peak memory 200984 kb
Host smart-2cc174d0-7ca5-4e0e-8c24-f177d43924d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305752389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2305752389
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1246852274
Short name T801
Test name
Test status
Simulation time 532333671 ps
CPU time 0.95 seconds
Started Aug 14 04:43:31 PM PDT 24
Finished Aug 14 04:43:32 PM PDT 24
Peak memory 200896 kb
Host smart-04116eac-6c32-41f6-ae47-be1e7ea0feec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246852274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1246852274
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1675966813
Short name T853
Test name
Test status
Simulation time 5235852259 ps
CPU time 5.55 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:43:30 PM PDT 24
Peak memory 201240 kb
Host smart-6c049cd6-9873-4235-b9e3-da4cafff8a20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675966813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1675966813
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4189156468
Short name T84
Test name
Test status
Simulation time 555231643 ps
CPU time 1.81 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:18 PM PDT 24
Peak memory 201132 kb
Host smart-2cc127fa-6fea-4983-9e7b-7c6cb71164b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189156468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.4189156468
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3109365187
Short name T366
Test name
Test status
Simulation time 4740882259 ps
CPU time 4.21 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:43:44 PM PDT 24
Peak memory 201184 kb
Host smart-bf7408f8-a4b4-4201-99b6-5bb2509d14dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109365187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3109365187
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.453298560
Short name T805
Test name
Test status
Simulation time 530717752 ps
CPU time 1.89 seconds
Started Aug 14 04:43:24 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 201052 kb
Host smart-cd4398ac-6185-4cac-b9e4-828ff925acd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453298560 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.453298560
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.450711840
Short name T144
Test name
Test status
Simulation time 529443925 ps
CPU time 0.99 seconds
Started Aug 14 04:43:21 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 200904 kb
Host smart-0688729d-9642-47ee-9724-c8b04bfa4ece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450711840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.450711840
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2029949285
Short name T820
Test name
Test status
Simulation time 293056948 ps
CPU time 1.27 seconds
Started Aug 14 04:43:51 PM PDT 24
Finished Aug 14 04:43:53 PM PDT 24
Peak memory 200216 kb
Host smart-28b68900-1c3f-4031-ba52-93e5198c2fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029949285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2029949285
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1493276298
Short name T844
Test name
Test status
Simulation time 4711803582 ps
CPU time 10.09 seconds
Started Aug 14 04:43:32 PM PDT 24
Finished Aug 14 04:43:42 PM PDT 24
Peak memory 201132 kb
Host smart-70f76fa0-92fa-4938-bb04-4b305d8f15f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493276298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1493276298
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3630097277
Short name T809
Test name
Test status
Simulation time 569344505 ps
CPU time 3.2 seconds
Started Aug 14 04:43:21 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 217380 kb
Host smart-e071f58a-66ee-499e-8c9b-941925840897
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630097277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3630097277
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3338292120
Short name T371
Test name
Test status
Simulation time 9044050495 ps
CPU time 23.03 seconds
Started Aug 14 04:43:34 PM PDT 24
Finished Aug 14 04:43:57 PM PDT 24
Peak memory 201192 kb
Host smart-e838f67a-5b42-4de6-b331-731e7b404a90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338292120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3338292120
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3636287152
Short name T914
Test name
Test status
Simulation time 557328546 ps
CPU time 1.12 seconds
Started Aug 14 04:43:29 PM PDT 24
Finished Aug 14 04:43:31 PM PDT 24
Peak memory 201068 kb
Host smart-5275b937-e53f-47ba-8860-45476c730ba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636287152 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3636287152
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1143964641
Short name T880
Test name
Test status
Simulation time 568615080 ps
CPU time 1.01 seconds
Started Aug 14 04:43:51 PM PDT 24
Finished Aug 14 04:43:52 PM PDT 24
Peak memory 200912 kb
Host smart-6423c7f4-a8a8-4cf3-81ff-470f5c30be26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143964641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1143964641
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.526612296
Short name T816
Test name
Test status
Simulation time 376931050 ps
CPU time 1.47 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:43:41 PM PDT 24
Peak memory 200840 kb
Host smart-7097eb44-5049-410e-940e-5d67a889b603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526612296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.526612296
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3846714729
Short name T855
Test name
Test status
Simulation time 4411188529 ps
CPU time 3.62 seconds
Started Aug 14 04:43:21 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 201232 kb
Host smart-9dfe12c4-58e5-4636-935d-b1577bd8be2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846714729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3846714729
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1714850945
Short name T828
Test name
Test status
Simulation time 349127191 ps
CPU time 2.66 seconds
Started Aug 14 04:43:22 PM PDT 24
Finished Aug 14 04:43:25 PM PDT 24
Peak memory 201204 kb
Host smart-95ad3e5c-d2bb-470a-a2f3-43d748864cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714850945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1714850945
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3040481239
Short name T69
Test name
Test status
Simulation time 8152333043 ps
CPU time 11.09 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 201144 kb
Host smart-ea01a9b0-4735-49ce-a277-904518faba84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040481239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3040481239
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1559003013
Short name T137
Test name
Test status
Simulation time 598307084 ps
CPU time 2.67 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 201052 kb
Host smart-8f9c290b-a3b9-43f4-a3b9-d0f6d3a5719c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559003013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1559003013
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3507811302
Short name T902
Test name
Test status
Simulation time 11744883963 ps
CPU time 11.72 seconds
Started Aug 14 04:43:14 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 201232 kb
Host smart-8c7c1d96-a3b5-4500-b9eb-4a1f7d17ad5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507811302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3507811302
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.995824983
Short name T831
Test name
Test status
Simulation time 1015579366 ps
CPU time 1.99 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 200984 kb
Host smart-803ec004-75da-4c69-8db1-02d5b32c7867
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995824983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.995824983
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3923575984
Short name T881
Test name
Test status
Simulation time 584315707 ps
CPU time 1.13 seconds
Started Aug 14 04:43:31 PM PDT 24
Finished Aug 14 04:43:32 PM PDT 24
Peak memory 201000 kb
Host smart-6d5de8d6-bb81-4e8c-b589-6ba5f9602866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923575984 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3923575984
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2841435241
Short name T149
Test name
Test status
Simulation time 510034029 ps
CPU time 0.98 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:10 PM PDT 24
Peak memory 200960 kb
Host smart-93e88adb-01da-4cb6-81cb-953d3467cac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841435241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2841435241
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2378599702
Short name T811
Test name
Test status
Simulation time 414537277 ps
CPU time 1.53 seconds
Started Aug 14 04:43:28 PM PDT 24
Finished Aug 14 04:43:29 PM PDT 24
Peak memory 200912 kb
Host smart-9cc58804-f3c1-45a9-8e8d-e6d3a39da090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378599702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2378599702
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2287958544
Short name T147
Test name
Test status
Simulation time 2316489677 ps
CPU time 1.33 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:43:17 PM PDT 24
Peak memory 201004 kb
Host smart-46a50602-5551-44e4-865f-f1d47b90ee18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287958544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2287958544
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1463017236
Short name T879
Test name
Test status
Simulation time 393047357 ps
CPU time 2.66 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 201236 kb
Host smart-0e5d0c9e-20bd-4a09-bcc8-d9b6a75837b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463017236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1463017236
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.816388125
Short name T904
Test name
Test status
Simulation time 4671517141 ps
CPU time 4.06 seconds
Started Aug 14 04:43:24 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 201200 kb
Host smart-706e2539-c43b-40f7-8c42-50e06a8ffb3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816388125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.816388125
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1075524525
Short name T825
Test name
Test status
Simulation time 385610314 ps
CPU time 0.89 seconds
Started Aug 14 04:43:30 PM PDT 24
Finished Aug 14 04:43:31 PM PDT 24
Peak memory 200844 kb
Host smart-59da325a-645f-4367-8380-57c403cce538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075524525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1075524525
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3174111652
Short name T810
Test name
Test status
Simulation time 410246922 ps
CPU time 0.95 seconds
Started Aug 14 04:43:51 PM PDT 24
Finished Aug 14 04:43:52 PM PDT 24
Peak memory 200268 kb
Host smart-9fc750cb-99c2-4d42-9a48-581082779e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174111652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3174111652
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.734880619
Short name T804
Test name
Test status
Simulation time 370372959 ps
CPU time 1.41 seconds
Started Aug 14 04:43:53 PM PDT 24
Finished Aug 14 04:43:54 PM PDT 24
Peak memory 200840 kb
Host smart-b3832f92-5f69-45cc-8a43-520ff9f7f791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734880619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.734880619
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3992393433
Short name T839
Test name
Test status
Simulation time 347930479 ps
CPU time 1.46 seconds
Started Aug 14 04:43:42 PM PDT 24
Finished Aug 14 04:43:44 PM PDT 24
Peak memory 200908 kb
Host smart-6d84b7dc-1d96-4f59-bf89-ab361a628a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992393433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3992393433
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2115625714
Short name T845
Test name
Test status
Simulation time 544505134 ps
CPU time 0.94 seconds
Started Aug 14 04:44:19 PM PDT 24
Finished Aug 14 04:44:20 PM PDT 24
Peak memory 198568 kb
Host smart-bdd8b493-7c91-454b-a435-cacf38da4d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115625714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2115625714
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4008010994
Short name T800
Test name
Test status
Simulation time 541641414 ps
CPU time 0.72 seconds
Started Aug 14 04:43:54 PM PDT 24
Finished Aug 14 04:43:55 PM PDT 24
Peak memory 200820 kb
Host smart-afb68619-fbc6-422a-8657-f9de8c84b193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008010994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.4008010994
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2572760167
Short name T824
Test name
Test status
Simulation time 286750278 ps
CPU time 1.22 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:43:40 PM PDT 24
Peak memory 200816 kb
Host smart-295b9f37-b994-4cf1-847f-b80d51cb1587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572760167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2572760167
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.114083002
Short name T861
Test name
Test status
Simulation time 404451385 ps
CPU time 1.57 seconds
Started Aug 14 04:43:53 PM PDT 24
Finished Aug 14 04:43:55 PM PDT 24
Peak memory 200912 kb
Host smart-e12de968-cc94-45eb-8247-864dfadc0957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114083002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.114083002
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3329467114
Short name T842
Test name
Test status
Simulation time 521924279 ps
CPU time 1.89 seconds
Started Aug 14 04:43:42 PM PDT 24
Finished Aug 14 04:43:44 PM PDT 24
Peak memory 200888 kb
Host smart-a0d4eadd-7c50-4e16-87e9-03c8348bfbb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329467114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3329467114
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2762002757
Short name T832
Test name
Test status
Simulation time 371012617 ps
CPU time 0.82 seconds
Started Aug 14 04:44:51 PM PDT 24
Finished Aug 14 04:44:51 PM PDT 24
Peak memory 200636 kb
Host smart-3926ea33-060e-4c54-b733-437a93d1e933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762002757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2762002757
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.142852396
Short name T887
Test name
Test status
Simulation time 904353860 ps
CPU time 2.54 seconds
Started Aug 14 04:43:12 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 201100 kb
Host smart-c4f2d06a-f84c-4839-bdd2-814f225d4ca4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142852396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.142852396
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3239312584
Short name T140
Test name
Test status
Simulation time 17335262768 ps
CPU time 67.58 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:44:24 PM PDT 24
Peak memory 201236 kb
Host smart-0f9821e3-afa9-4819-9a92-8c0cff2b6807
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239312584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3239312584
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1282387285
Short name T916
Test name
Test status
Simulation time 1303296325 ps
CPU time 3.61 seconds
Started Aug 14 04:43:34 PM PDT 24
Finished Aug 14 04:43:37 PM PDT 24
Peak memory 200972 kb
Host smart-93eece06-e4c1-443f-a4f9-48c24fb8b5d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282387285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1282387285
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.340690813
Short name T86
Test name
Test status
Simulation time 531063748 ps
CPU time 2.1 seconds
Started Aug 14 04:43:14 PM PDT 24
Finished Aug 14 04:43:17 PM PDT 24
Peak memory 201048 kb
Host smart-d73145f6-f3bd-458b-8d44-24d9c078b7ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340690813 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.340690813
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2080198310
Short name T139
Test name
Test status
Simulation time 547162899 ps
CPU time 0.96 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 200988 kb
Host smart-26cdbb4d-ddee-48bb-9491-5167f0411670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080198310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2080198310
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2606438651
Short name T869
Test name
Test status
Simulation time 477224796 ps
CPU time 0.93 seconds
Started Aug 14 04:43:42 PM PDT 24
Finished Aug 14 04:43:43 PM PDT 24
Peak memory 200848 kb
Host smart-7061584b-9883-4a4c-958c-2b86b196c565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606438651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2606438651
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3808687526
Short name T846
Test name
Test status
Simulation time 4139777746 ps
CPU time 3.03 seconds
Started Aug 14 04:43:33 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 201236 kb
Host smart-a7123bcd-b0c4-4272-a458-11f21081252c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808687526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3808687526
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2683951236
Short name T80
Test name
Test status
Simulation time 512617401 ps
CPU time 3.11 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 201188 kb
Host smart-15752eb1-a8ea-4bd6-b208-5209103688fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683951236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2683951236
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3857109966
Short name T870
Test name
Test status
Simulation time 4726228705 ps
CPU time 4.32 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 201224 kb
Host smart-b8813087-e8fe-41c1-9ddb-da6320c95f38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857109966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3857109966
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2767224314
Short name T877
Test name
Test status
Simulation time 462284248 ps
CPU time 0.81 seconds
Started Aug 14 04:43:38 PM PDT 24
Finished Aug 14 04:43:39 PM PDT 24
Peak memory 200856 kb
Host smart-b99e425d-a346-40af-9e3b-0041591937d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767224314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2767224314
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.716525595
Short name T812
Test name
Test status
Simulation time 541775979 ps
CPU time 1.28 seconds
Started Aug 14 04:44:19 PM PDT 24
Finished Aug 14 04:44:21 PM PDT 24
Peak memory 198524 kb
Host smart-e6a57d8c-1161-4216-bbb0-217dd808b4b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716525595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.716525595
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1950929862
Short name T808
Test name
Test status
Simulation time 396040682 ps
CPU time 1.51 seconds
Started Aug 14 04:43:50 PM PDT 24
Finished Aug 14 04:43:52 PM PDT 24
Peak memory 200928 kb
Host smart-8532c6e8-8bdb-43b5-9288-fa582feac4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950929862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1950929862
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3515202643
Short name T849
Test name
Test status
Simulation time 526649665 ps
CPU time 1.23 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 200916 kb
Host smart-52ef8313-3a52-45ac-8845-90f361b0a9a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515202643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3515202643
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3344268041
Short name T901
Test name
Test status
Simulation time 344097806 ps
CPU time 0.86 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 200812 kb
Host smart-46779b7e-beb1-4ae6-84c3-87538d9dec35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344268041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3344268041
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.370997629
Short name T913
Test name
Test status
Simulation time 449403897 ps
CPU time 1.59 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:03 PM PDT 24
Peak memory 200668 kb
Host smart-3f233047-de68-48b7-b87e-c71709b27249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370997629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.370997629
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3887289024
Short name T847
Test name
Test status
Simulation time 434246294 ps
CPU time 0.84 seconds
Started Aug 14 04:43:30 PM PDT 24
Finished Aug 14 04:43:32 PM PDT 24
Peak memory 200912 kb
Host smart-b5b7d2f4-d927-46ad-b64a-489c3df46970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887289024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3887289024
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4220972184
Short name T821
Test name
Test status
Simulation time 424212827 ps
CPU time 0.81 seconds
Started Aug 14 04:43:50 PM PDT 24
Finished Aug 14 04:43:51 PM PDT 24
Peak memory 200916 kb
Host smart-8d1e8d34-ed5d-4d33-952a-bce43ec0f765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220972184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4220972184
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2905628914
Short name T826
Test name
Test status
Simulation time 468513115 ps
CPU time 1.67 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 200896 kb
Host smart-6ce43218-15bd-4e52-b178-7a924547f48e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905628914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2905628914
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3594002632
Short name T897
Test name
Test status
Simulation time 392040998 ps
CPU time 1.05 seconds
Started Aug 14 04:43:50 PM PDT 24
Finished Aug 14 04:43:51 PM PDT 24
Peak memory 200916 kb
Host smart-c309c1c7-e51a-4ed5-ba7c-adf2bcc5579f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594002632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3594002632
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.307914201
Short name T909
Test name
Test status
Simulation time 878434800 ps
CPU time 1.93 seconds
Started Aug 14 04:43:10 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 201008 kb
Host smart-cde1e37a-9a2b-4ea5-b986-dc818900a9f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307914201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.307914201
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.115848701
Short name T141
Test name
Test status
Simulation time 41291516522 ps
CPU time 44.98 seconds
Started Aug 14 04:43:14 PM PDT 24
Finished Aug 14 04:43:59 PM PDT 24
Peak memory 201172 kb
Host smart-a0e411b0-fbb8-470e-9e8c-7836e3bbf368
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115848701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.115848701
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3240713005
Short name T885
Test name
Test status
Simulation time 740528926 ps
CPU time 2.36 seconds
Started Aug 14 04:43:31 PM PDT 24
Finished Aug 14 04:43:34 PM PDT 24
Peak memory 200980 kb
Host smart-2c77923e-699d-4fce-847e-de04afeb2e34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240713005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3240713005
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.486344503
Short name T822
Test name
Test status
Simulation time 533072895 ps
CPU time 1.61 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 200984 kb
Host smart-d83af501-e9c3-40d9-91ad-06aa1f388612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486344503 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.486344503
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.911449246
Short name T142
Test name
Test status
Simulation time 431759921 ps
CPU time 1.78 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 200916 kb
Host smart-75e94c7e-5c0e-4418-bc8b-2c16c2505c13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911449246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.911449246
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2440552221
Short name T912
Test name
Test status
Simulation time 381339898 ps
CPU time 0.84 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:05 PM PDT 24
Peak memory 200880 kb
Host smart-9c4c869b-34a8-4ba1-9f12-fd49db7a56af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440552221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2440552221
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2184332432
Short name T146
Test name
Test status
Simulation time 4258617213 ps
CPU time 7.99 seconds
Started Aug 14 04:43:14 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 201192 kb
Host smart-a21ce79f-9f73-43da-9adc-5cc0223121f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184332432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2184332432
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3948545610
Short name T917
Test name
Test status
Simulation time 694914658 ps
CPU time 2.17 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 201096 kb
Host smart-0a833281-2eb6-46d5-96da-6bc7195aaad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948545610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3948545610
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.490364339
Short name T89
Test name
Test status
Simulation time 8401314006 ps
CPU time 22.08 seconds
Started Aug 14 04:43:13 PM PDT 24
Finished Aug 14 04:43:35 PM PDT 24
Peak memory 201160 kb
Host smart-e2414127-6398-415d-83da-5ae144d80d84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490364339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.490364339
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1984010844
Short name T830
Test name
Test status
Simulation time 410466899 ps
CPU time 0.83 seconds
Started Aug 14 04:44:46 PM PDT 24
Finished Aug 14 04:44:46 PM PDT 24
Peak memory 200640 kb
Host smart-a6ab4186-58b6-48f6-bae5-24453fb0f5f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984010844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1984010844
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.694143925
Short name T829
Test name
Test status
Simulation time 444687543 ps
CPU time 0.76 seconds
Started Aug 14 04:43:41 PM PDT 24
Finished Aug 14 04:43:42 PM PDT 24
Peak memory 200916 kb
Host smart-0c7b94b5-717d-4c08-bd80-ec2d41ea6daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694143925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.694143925
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2781850537
Short name T815
Test name
Test status
Simulation time 448771907 ps
CPU time 0.75 seconds
Started Aug 14 04:44:42 PM PDT 24
Finished Aug 14 04:44:50 PM PDT 24
Peak memory 200636 kb
Host smart-8d481399-4a50-410c-85c1-e3a049915c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781850537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2781850537
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1859599194
Short name T860
Test name
Test status
Simulation time 352885872 ps
CPU time 1.49 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:18 PM PDT 24
Peak memory 200892 kb
Host smart-346df2f2-1cde-4942-876c-5e88c85e8efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859599194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1859599194
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.666620407
Short name T851
Test name
Test status
Simulation time 360501344 ps
CPU time 1.48 seconds
Started Aug 14 04:43:26 PM PDT 24
Finished Aug 14 04:43:33 PM PDT 24
Peak memory 200916 kb
Host smart-fc652121-d40e-4b60-93cf-b8cc7967dcfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666620407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.666620407
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3721384018
Short name T876
Test name
Test status
Simulation time 516372181 ps
CPU time 1.68 seconds
Started Aug 14 04:44:43 PM PDT 24
Finished Aug 14 04:44:45 PM PDT 24
Peak memory 200636 kb
Host smart-71afd840-162f-475c-93a5-fc5939125163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721384018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3721384018
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1942728694
Short name T884
Test name
Test status
Simulation time 387211546 ps
CPU time 1.03 seconds
Started Aug 14 04:43:35 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 200916 kb
Host smart-103fe329-b220-4ee0-9e80-78dea2884f98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942728694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1942728694
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1001333742
Short name T873
Test name
Test status
Simulation time 432674548 ps
CPU time 0.79 seconds
Started Aug 14 04:43:34 PM PDT 24
Finished Aug 14 04:43:35 PM PDT 24
Peak memory 200912 kb
Host smart-b925fa18-9e7e-4cdf-9496-691fa9f2c360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001333742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1001333742
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2266531377
Short name T905
Test name
Test status
Simulation time 553180555 ps
CPU time 0.94 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 200916 kb
Host smart-28726723-2a3c-4df4-82b9-5b6684476c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266531377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2266531377
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3037520389
Short name T854
Test name
Test status
Simulation time 357975515 ps
CPU time 1 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 200888 kb
Host smart-7fa83f7c-dc67-4557-83fa-62aa44e6e49d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037520389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3037520389
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3803651530
Short name T911
Test name
Test status
Simulation time 412596956 ps
CPU time 1.81 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 201004 kb
Host smart-80fac6da-ae6f-4ef1-aeff-b6ba4eef0dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803651530 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3803651530
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3015192547
Short name T878
Test name
Test status
Simulation time 515530497 ps
CPU time 1.07 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:17 PM PDT 24
Peak memory 200896 kb
Host smart-cf7907b6-97c8-4011-ae87-c8812a68e6a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015192547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3015192547
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2530595916
Short name T818
Test name
Test status
Simulation time 556370269 ps
CPU time 0.87 seconds
Started Aug 14 04:43:31 PM PDT 24
Finished Aug 14 04:43:32 PM PDT 24
Peak memory 200792 kb
Host smart-217b23cf-dcca-4e8e-8706-dd161163fba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530595916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2530595916
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3723030065
Short name T886
Test name
Test status
Simulation time 4529779571 ps
CPU time 10.43 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:29 PM PDT 24
Peak memory 201188 kb
Host smart-dc434b54-4b4f-40db-8a0d-5dbb9f53aba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723030065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3723030065
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2176064644
Short name T88
Test name
Test status
Simulation time 8226075177 ps
CPU time 19.66 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:40 PM PDT 24
Peak memory 201236 kb
Host smart-fa1a7adb-bc32-49af-aba9-d0c2f4423475
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176064644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2176064644
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3620301500
Short name T838
Test name
Test status
Simulation time 421357242 ps
CPU time 1.98 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 201016 kb
Host smart-0abe954c-8a6b-4d7d-b921-37a7d9bc68b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620301500 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3620301500
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.680439345
Short name T135
Test name
Test status
Simulation time 505307951 ps
CPU time 1.97 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 200960 kb
Host smart-022a6603-3e7a-41f7-8c24-ea5936a0e56b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680439345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.680439345
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4125831773
Short name T843
Test name
Test status
Simulation time 359598898 ps
CPU time 0.85 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:43:16 PM PDT 24
Peak memory 200884 kb
Host smart-0a8f1bd6-4883-4e0f-8219-443f9cd7cae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125831773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4125831773
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3652484269
Short name T895
Test name
Test status
Simulation time 4666638279 ps
CPU time 10.13 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:29 PM PDT 24
Peak memory 201224 kb
Host smart-7c2561d7-0e08-4344-aaaf-401ef236f47b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652484269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3652484269
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2939375859
Short name T79
Test name
Test status
Simulation time 573789669 ps
CPU time 2.57 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 201200 kb
Host smart-b64d4f84-0dd6-42eb-8df6-bc3e5aede09a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939375859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2939375859
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.961865816
Short name T856
Test name
Test status
Simulation time 4378345665 ps
CPU time 10.93 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 201196 kb
Host smart-9b6ea045-11b2-4fec-bb0f-244087a72fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961865816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.961865816
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1050311971
Short name T910
Test name
Test status
Simulation time 736974671 ps
CPU time 0.94 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 200996 kb
Host smart-51047fa3-4654-4612-a632-cb5b0fd6f809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050311971 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1050311971
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2086686666
Short name T837
Test name
Test status
Simulation time 337574528 ps
CPU time 1.57 seconds
Started Aug 14 04:43:48 PM PDT 24
Finished Aug 14 04:43:49 PM PDT 24
Peak memory 200984 kb
Host smart-3706deed-7ed4-4898-978b-73be11c7e8ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086686666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2086686666
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2674480955
Short name T867
Test name
Test status
Simulation time 304538812 ps
CPU time 1.32 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 200912 kb
Host smart-d1332b5f-f73b-42f8-9e3d-064abf8453de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674480955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2674480955
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.865577996
Short name T827
Test name
Test status
Simulation time 2180392265 ps
CPU time 6.27 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 201020 kb
Host smart-ca324479-96f9-45e7-9dd4-8cfe8c68cd7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865577996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.865577996
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4087608598
Short name T859
Test name
Test status
Simulation time 394864823 ps
CPU time 3.3 seconds
Started Aug 14 04:43:24 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 209312 kb
Host smart-bebacce6-56dc-4c76-88ed-4ee4fff2f09c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087608598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4087608598
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1169420056
Short name T919
Test name
Test status
Simulation time 4175280141 ps
CPU time 4.4 seconds
Started Aug 14 04:43:22 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 201132 kb
Host smart-05c0d88f-48da-47c2-a013-8031ba7de1af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169420056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1169420056
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3310335513
Short name T875
Test name
Test status
Simulation time 323589741 ps
CPU time 1.55 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 201028 kb
Host smart-c770878b-02e0-42d8-a257-0cdce1daf0c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310335513 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3310335513
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4027468911
Short name T145
Test name
Test status
Simulation time 366059231 ps
CPU time 0.99 seconds
Started Aug 14 04:43:27 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 200984 kb
Host smart-fd19af78-7f18-40ef-b7cf-02475a4033f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027468911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4027468911
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2149843612
Short name T907
Test name
Test status
Simulation time 401765917 ps
CPU time 1.09 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:18 PM PDT 24
Peak memory 200912 kb
Host smart-039f974a-af75-4915-befd-df061cabf83f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149843612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2149843612
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.646362229
Short name T858
Test name
Test status
Simulation time 4351813269 ps
CPU time 2.19 seconds
Started Aug 14 04:43:42 PM PDT 24
Finished Aug 14 04:43:44 PM PDT 24
Peak memory 201224 kb
Host smart-c3e1fcf7-8162-4ff4-a5d1-e30c3697e1d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646362229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.646362229
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2844484086
Short name T899
Test name
Test status
Simulation time 926691585 ps
CPU time 1.17 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 201044 kb
Host smart-49ea3cdb-3653-4281-9a75-31a58d402872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844484086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2844484086
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2733450947
Short name T367
Test name
Test status
Simulation time 4546131097 ps
CPU time 6.78 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:44:03 PM PDT 24
Peak memory 201236 kb
Host smart-92c1c17b-36b2-4091-a622-7f3817107dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733450947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2733450947
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1857050265
Short name T814
Test name
Test status
Simulation time 556098115 ps
CPU time 1.17 seconds
Started Aug 14 04:43:22 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 200976 kb
Host smart-af1a559b-e8ca-40e3-b043-4e277aef83a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857050265 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1857050265
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.875023121
Short name T890
Test name
Test status
Simulation time 576984184 ps
CPU time 0.93 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:43:57 PM PDT 24
Peak memory 200960 kb
Host smart-466d5137-dacc-4e9a-b3a7-7de64abac57b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875023121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.875023121
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2535349237
Short name T868
Test name
Test status
Simulation time 574627588 ps
CPU time 0.89 seconds
Started Aug 14 04:43:23 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 201088 kb
Host smart-cda003c7-d165-4983-9fe2-2801fd6ef03f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535349237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2535349237
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2570776227
Short name T66
Test name
Test status
Simulation time 2197743547 ps
CPU time 4.95 seconds
Started Aug 14 04:43:24 PM PDT 24
Finished Aug 14 04:43:29 PM PDT 24
Peak memory 201040 kb
Host smart-78ca3aff-167c-4b4f-b302-91bc36e9c240
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570776227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2570776227
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3582701778
Short name T872
Test name
Test status
Simulation time 591841789 ps
CPU time 1.37 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:18 PM PDT 24
Peak memory 201232 kb
Host smart-9dc04532-a292-4304-be2c-8252ce6fd1f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582701778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3582701778
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2349994449
Short name T892
Test name
Test status
Simulation time 4208738834 ps
CPU time 6.23 seconds
Started Aug 14 04:43:27 PM PDT 24
Finished Aug 14 04:43:33 PM PDT 24
Peak memory 201236 kb
Host smart-40c7b7d0-2fb8-4031-a723-7b6294414b05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349994449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2349994449
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.4139674312
Short name T486
Test name
Test status
Simulation time 306066247 ps
CPU time 0.83 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:17:00 PM PDT 24
Peak memory 202012 kb
Host smart-82e794d8-cf1e-4956-8a8a-e61360880c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139674312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.4139674312
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3007834066
Short name T218
Test name
Test status
Simulation time 323344316191 ps
CPU time 113.61 seconds
Started Aug 14 05:16:57 PM PDT 24
Finished Aug 14 05:18:51 PM PDT 24
Peak memory 202176 kb
Host smart-c890530c-afc6-4a13-987f-07adc76004ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007834066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3007834066
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.514726114
Short name T750
Test name
Test status
Simulation time 162951054427 ps
CPU time 97.71 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:18:37 PM PDT 24
Peak memory 202156 kb
Host smart-5acfb12f-b902-404e-a3b2-aa7987494a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514726114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.514726114
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.647472092
Short name T356
Test name
Test status
Simulation time 493222510274 ps
CPU time 1110.68 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:35:29 PM PDT 24
Peak memory 202148 kb
Host smart-7a5ebca1-0419-4c0e-a765-b0c79fcdd33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647472092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.647472092
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.669749608
Short name T303
Test name
Test status
Simulation time 164711859710 ps
CPU time 189.02 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:20:07 PM PDT 24
Peak memory 202024 kb
Host smart-3b66ec8f-5feb-4450-a90c-68b31814ddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669749608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.669749608
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1110245052
Short name T408
Test name
Test status
Simulation time 334857410523 ps
CPU time 739.21 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:29:17 PM PDT 24
Peak memory 202112 kb
Host smart-e19efdb6-289b-459d-bb89-83b235be7f29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110245052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1110245052
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1127507594
Short name T413
Test name
Test status
Simulation time 605311701286 ps
CPU time 141.54 seconds
Started Aug 14 05:17:01 PM PDT 24
Finished Aug 14 05:19:22 PM PDT 24
Peak memory 202168 kb
Host smart-94852f9a-d6a5-45b9-be8c-5bdac82142f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127507594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1127507594
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3175282376
Short name T498
Test name
Test status
Simulation time 42075611999 ps
CPU time 25.17 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:17:24 PM PDT 24
Peak memory 201968 kb
Host smart-8bc88638-df24-4eba-95ee-0190a3c7a2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175282376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3175282376
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3368810420
Short name T733
Test name
Test status
Simulation time 4315249713 ps
CPU time 2.91 seconds
Started Aug 14 05:16:57 PM PDT 24
Finished Aug 14 05:17:00 PM PDT 24
Peak memory 201972 kb
Host smart-309aced4-f115-48b3-b6d8-5771befc95a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368810420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3368810420
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2039577272
Short name T77
Test name
Test status
Simulation time 4146925100 ps
CPU time 2.82 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:17:01 PM PDT 24
Peak memory 217604 kb
Host smart-bbd830e2-2e41-4954-9dea-50cf3d772c19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039577272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2039577272
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.4021500353
Short name T105
Test name
Test status
Simulation time 6119607673 ps
CPU time 3.9 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:17:02 PM PDT 24
Peak memory 201952 kb
Host smart-6b793752-cce4-4fff-bd5f-c8541a706b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021500353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.4021500353
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1635487466
Short name T438
Test name
Test status
Simulation time 48285659707 ps
CPU time 25.18 seconds
Started Aug 14 05:16:57 PM PDT 24
Finished Aug 14 05:17:22 PM PDT 24
Peak memory 202176 kb
Host smart-d7dd869c-c3a8-44a9-be67-c8e8cf8e2394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635487466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1635487466
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.780170380
Short name T665
Test name
Test status
Simulation time 2090260637 ps
CPU time 6.92 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:17:06 PM PDT 24
Peak memory 211564 kb
Host smart-50268e98-9e0b-42ed-88e1-d9850250e25a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780170380 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.780170380
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1707259556
Short name T599
Test name
Test status
Simulation time 179335218107 ps
CPU time 411.27 seconds
Started Aug 14 05:17:10 PM PDT 24
Finished Aug 14 05:24:01 PM PDT 24
Peak memory 202116 kb
Host smart-a1da7540-ba2b-4cbc-afd7-0f38dfeb2c84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707259556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1707259556
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4088042952
Short name T648
Test name
Test status
Simulation time 494036288520 ps
CPU time 1094.38 seconds
Started Aug 14 05:17:00 PM PDT 24
Finished Aug 14 05:35:14 PM PDT 24
Peak memory 202152 kb
Host smart-10f6dcb2-ef7b-496c-9dd4-e75dfc7ae220
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088042952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.4088042952
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2478109339
Short name T96
Test name
Test status
Simulation time 327918621337 ps
CPU time 124.48 seconds
Started Aug 14 05:17:01 PM PDT 24
Finished Aug 14 05:19:05 PM PDT 24
Peak memory 202176 kb
Host smart-d70f9c87-35fc-46de-81c7-56d838631fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478109339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2478109339
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.681145413
Short name T707
Test name
Test status
Simulation time 330470352068 ps
CPU time 684.39 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:28:23 PM PDT 24
Peak memory 202036 kb
Host smart-a5f9d6bc-1a20-46aa-ad80-6dc296f70940
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=681145413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.681145413
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1029926397
Short name T320
Test name
Test status
Simulation time 359828578913 ps
CPU time 230.56 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:20:58 PM PDT 24
Peak memory 202140 kb
Host smart-18a8f866-f408-4629-bf01-2e5c654d06da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029926397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1029926397
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.696486433
Short name T675
Test name
Test status
Simulation time 206038844989 ps
CPU time 117.08 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:19:06 PM PDT 24
Peak memory 202144 kb
Host smart-3f638be0-dc28-42fa-b54c-1a5290c5d775
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696486433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.696486433
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2402863368
Short name T631
Test name
Test status
Simulation time 110690530323 ps
CPU time 354.5 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:23:01 PM PDT 24
Peak memory 202288 kb
Host smart-5a0a50a7-8198-4759-a9dd-185547079b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402863368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2402863368
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4113391812
Short name T713
Test name
Test status
Simulation time 36750413386 ps
CPU time 90.88 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:18:38 PM PDT 24
Peak memory 201952 kb
Host smart-bb523288-85f8-4515-95b1-268e76272048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113391812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4113391812
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.475018078
Short name T391
Test name
Test status
Simulation time 4631842872 ps
CPU time 10.06 seconds
Started Aug 14 05:17:10 PM PDT 24
Finished Aug 14 05:17:21 PM PDT 24
Peak memory 201968 kb
Host smart-f1872106-a88b-41c9-8c18-37e3b9f7f509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475018078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.475018078
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2862717153
Short name T699
Test name
Test status
Simulation time 5842867512 ps
CPU time 7.48 seconds
Started Aug 14 05:17:02 PM PDT 24
Finished Aug 14 05:17:10 PM PDT 24
Peak memory 201972 kb
Host smart-4e0cc9bf-b76f-4134-83ba-3068c3a08b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862717153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2862717153
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2379909123
Short name T21
Test name
Test status
Simulation time 6388881737 ps
CPU time 4.67 seconds
Started Aug 14 05:17:10 PM PDT 24
Finished Aug 14 05:17:15 PM PDT 24
Peak memory 202304 kb
Host smart-0f66d9be-a4bf-45af-ab8f-e2f910ce8691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379909123 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2379909123
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.544088387
Short name T485
Test name
Test status
Simulation time 517089299 ps
CPU time 0.91 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:18:00 PM PDT 24
Peak memory 201996 kb
Host smart-f266f783-0150-409a-877e-562d05948e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544088387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.544088387
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3809712018
Short name T215
Test name
Test status
Simulation time 331920692544 ps
CPU time 593.06 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:27:52 PM PDT 24
Peak memory 202208 kb
Host smart-ff2740bf-daa4-43e5-84f1-cc9b40017213
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809712018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3809712018
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3052919113
Short name T223
Test name
Test status
Simulation time 319879030574 ps
CPU time 186.25 seconds
Started Aug 14 05:17:57 PM PDT 24
Finished Aug 14 05:21:03 PM PDT 24
Peak memory 202144 kb
Host smart-e0c197a2-9ccd-47d9-b96d-f56e8a11162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052919113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3052919113
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3521878500
Short name T493
Test name
Test status
Simulation time 493985889958 ps
CPU time 579.9 seconds
Started Aug 14 05:17:57 PM PDT 24
Finished Aug 14 05:27:37 PM PDT 24
Peak memory 202176 kb
Host smart-f44ef92a-bb87-490a-94b5-297d89c48941
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521878500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3521878500
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1932219157
Short name T415
Test name
Test status
Simulation time 160336600174 ps
CPU time 331.06 seconds
Started Aug 14 05:17:49 PM PDT 24
Finished Aug 14 05:23:21 PM PDT 24
Peak memory 202144 kb
Host smart-be321931-df78-485a-9205-803bad29ceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932219157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1932219157
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.842290984
Short name T554
Test name
Test status
Simulation time 323450063591 ps
CPU time 710.35 seconds
Started Aug 14 05:17:57 PM PDT 24
Finished Aug 14 05:29:48 PM PDT 24
Peak memory 202092 kb
Host smart-2b744cfd-bac0-485b-b1ad-8c5ded6820f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=842290984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.842290984
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3414203135
Short name T193
Test name
Test status
Simulation time 186472428059 ps
CPU time 35.07 seconds
Started Aug 14 05:17:58 PM PDT 24
Finished Aug 14 05:18:33 PM PDT 24
Peak memory 202168 kb
Host smart-d0b58d93-f1f8-46ec-8a55-c63e502386bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414203135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3414203135
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.992426414
Short name T38
Test name
Test status
Simulation time 610144711324 ps
CPU time 1370.4 seconds
Started Aug 14 05:17:58 PM PDT 24
Finished Aug 14 05:40:49 PM PDT 24
Peak memory 202132 kb
Host smart-5f95ef3b-62e1-4a67-8e79-f58028c5770c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992426414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.992426414
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1955183056
Short name T650
Test name
Test status
Simulation time 101438710935 ps
CPU time 318.28 seconds
Started Aug 14 05:17:49 PM PDT 24
Finished Aug 14 05:23:07 PM PDT 24
Peak memory 202444 kb
Host smart-9b69b2a3-a576-4593-8f06-3697326c9fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955183056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1955183056
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3393955581
Short name T457
Test name
Test status
Simulation time 28489911026 ps
CPU time 66.01 seconds
Started Aug 14 05:17:50 PM PDT 24
Finished Aug 14 05:18:56 PM PDT 24
Peak memory 201956 kb
Host smart-d5eb8f5f-d404-4d35-8264-32ab16a09dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393955581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3393955581
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3668392165
Short name T770
Test name
Test status
Simulation time 5079114439 ps
CPU time 13.39 seconds
Started Aug 14 05:17:57 PM PDT 24
Finished Aug 14 05:18:10 PM PDT 24
Peak memory 201968 kb
Host smart-fbb6e027-b14a-42b3-a314-e073afe0afba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668392165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3668392165
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3413093032
Short name T504
Test name
Test status
Simulation time 5711263106 ps
CPU time 7.4 seconds
Started Aug 14 05:17:57 PM PDT 24
Finished Aug 14 05:18:05 PM PDT 24
Peak memory 201960 kb
Host smart-7861033e-c16f-447f-9144-67c2000e4a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413093032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3413093032
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2100430709
Short name T327
Test name
Test status
Simulation time 375573761961 ps
CPU time 245.22 seconds
Started Aug 14 05:17:49 PM PDT 24
Finished Aug 14 05:21:54 PM PDT 24
Peak memory 201996 kb
Host smart-d72a4ee8-0106-4684-a0df-e4a150c7a7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100430709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2100430709
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3468577674
Short name T18
Test name
Test status
Simulation time 1025165822 ps
CPU time 3.59 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:18:03 PM PDT 24
Peak memory 201968 kb
Host smart-e30db147-3887-4e0c-b340-56b97a078bf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468577674 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3468577674
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.910515153
Short name T406
Test name
Test status
Simulation time 360473858 ps
CPU time 0.83 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:18:00 PM PDT 24
Peak memory 202000 kb
Host smart-fba7a190-a011-44fb-b1e7-1255cc771cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910515153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.910515153
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1978208869
Short name T275
Test name
Test status
Simulation time 167372375686 ps
CPU time 391.85 seconds
Started Aug 14 05:17:56 PM PDT 24
Finished Aug 14 05:24:28 PM PDT 24
Peak memory 202144 kb
Host smart-5979200c-0ca6-4977-ab62-134fccb249e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978208869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1978208869
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.667331713
Short name T652
Test name
Test status
Simulation time 166987228115 ps
CPU time 95.83 seconds
Started Aug 14 05:17:50 PM PDT 24
Finished Aug 14 05:19:26 PM PDT 24
Peak memory 202132 kb
Host smart-8cdb8413-015e-4462-9d69-a29a6083fa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667331713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.667331713
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2643076977
Short name T782
Test name
Test status
Simulation time 324346373978 ps
CPU time 782.71 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:31:01 PM PDT 24
Peak memory 202188 kb
Host smart-c3d50eb6-f72b-4991-8008-ee2cd661f262
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643076977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2643076977
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1951820570
Short name T309
Test name
Test status
Simulation time 325387613202 ps
CPU time 440.45 seconds
Started Aug 14 05:17:56 PM PDT 24
Finished Aug 14 05:25:17 PM PDT 24
Peak memory 202152 kb
Host smart-74618daf-a0d5-4c78-b313-5f051e204347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951820570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1951820570
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1190859656
Short name T795
Test name
Test status
Simulation time 171599751331 ps
CPU time 405.38 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:24:44 PM PDT 24
Peak memory 202212 kb
Host smart-4c727099-bbd7-42fa-b166-c8027c2225ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190859656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1190859656
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.553611939
Short name T261
Test name
Test status
Simulation time 202551156667 ps
CPU time 105.6 seconds
Started Aug 14 05:17:57 PM PDT 24
Finished Aug 14 05:19:43 PM PDT 24
Peak memory 202152 kb
Host smart-91e99fc2-d45f-4953-bc97-c3e962976c1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553611939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.553611939
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1149971685
Short name T442
Test name
Test status
Simulation time 383496644460 ps
CPU time 904.77 seconds
Started Aug 14 05:17:57 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 202152 kb
Host smart-592a7939-d2d4-4b05-9e9f-2a1f27384774
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149971685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1149971685
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4092212862
Short name T238
Test name
Test status
Simulation time 85929541223 ps
CPU time 444.3 seconds
Started Aug 14 05:17:48 PM PDT 24
Finished Aug 14 05:25:13 PM PDT 24
Peak memory 202396 kb
Host smart-75e39c50-b62d-41d2-8f25-d3aac2d694ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092212862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4092212862
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.610282382
Short name T676
Test name
Test status
Simulation time 41783873118 ps
CPU time 27.07 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:18:27 PM PDT 24
Peak memory 201980 kb
Host smart-a8ba6416-f024-46c9-8f4c-50b8a08a318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610282382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.610282382
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.806213295
Short name T577
Test name
Test status
Simulation time 2820609123 ps
CPU time 2.46 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:18:02 PM PDT 24
Peak memory 201972 kb
Host smart-0ed8d0b6-e34b-4325-9f3f-d3bee90fa02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806213295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.806213295
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.4235894037
Short name T383
Test name
Test status
Simulation time 6087521943 ps
CPU time 14.77 seconds
Started Aug 14 05:17:58 PM PDT 24
Finished Aug 14 05:18:12 PM PDT 24
Peak memory 201984 kb
Host smart-6c5f93c5-6460-4951-8fff-9f947fd37e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235894037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.4235894037
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.297806391
Short name T239
Test name
Test status
Simulation time 185907055351 ps
CPU time 442.61 seconds
Started Aug 14 05:18:00 PM PDT 24
Finished Aug 14 05:25:23 PM PDT 24
Peak memory 202276 kb
Host smart-d76a3df0-e508-4f7c-955b-a6416ef15afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297806391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
297806391
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2487234607
Short name T23
Test name
Test status
Simulation time 17499134492 ps
CPU time 35.19 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:18:34 PM PDT 24
Peak memory 210736 kb
Host smart-eefb2e49-0f50-42ef-a179-bb5ae2a0fd8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487234607 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2487234607
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.4147412354
Short name T433
Test name
Test status
Simulation time 352165451 ps
CPU time 1.5 seconds
Started Aug 14 05:17:56 PM PDT 24
Finished Aug 14 05:17:58 PM PDT 24
Peak memory 201980 kb
Host smart-bde8d82d-91dd-4442-b363-5d3df4d3ebed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147412354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.4147412354
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2609646381
Short name T280
Test name
Test status
Simulation time 165546529351 ps
CPU time 295.75 seconds
Started Aug 14 05:18:01 PM PDT 24
Finished Aug 14 05:22:57 PM PDT 24
Peak memory 202196 kb
Host smart-669e4728-0a97-415e-91e8-f0541cc5ab11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609646381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2609646381
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1656337808
Short name T666
Test name
Test status
Simulation time 159163894305 ps
CPU time 352.86 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:23:52 PM PDT 24
Peak memory 202148 kb
Host smart-fc87b2e8-a7ea-4c55-99e0-1a6cc123c923
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656337808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1656337808
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2910186616
Short name T621
Test name
Test status
Simulation time 491708395537 ps
CPU time 1050.15 seconds
Started Aug 14 05:18:00 PM PDT 24
Finished Aug 14 05:35:31 PM PDT 24
Peak memory 202316 kb
Host smart-c921702f-36d2-499a-88f0-0f9754bcac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910186616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2910186616
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2773003299
Short name T461
Test name
Test status
Simulation time 498053258187 ps
CPU time 284.51 seconds
Started Aug 14 05:18:01 PM PDT 24
Finished Aug 14 05:22:45 PM PDT 24
Peak memory 202172 kb
Host smart-436bdfa4-0a7c-4cdd-a03b-a88637179061
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773003299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2773003299
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3810810287
Short name T679
Test name
Test status
Simulation time 178885159198 ps
CPU time 110.71 seconds
Started Aug 14 05:18:00 PM PDT 24
Finished Aug 14 05:19:50 PM PDT 24
Peak memory 202028 kb
Host smart-82188cfc-ae92-42d3-91c1-51c4b10742ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810810287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3810810287
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.11834963
Short name T506
Test name
Test status
Simulation time 201943609337 ps
CPU time 79.81 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:19:19 PM PDT 24
Peak memory 202024 kb
Host smart-f3937f6c-cb14-4313-b0dc-17d75f261867
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11834963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
dc_ctrl_filters_wakeup_fixed.11834963
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.406602236
Short name T584
Test name
Test status
Simulation time 77531338559 ps
CPU time 288.6 seconds
Started Aug 14 05:18:00 PM PDT 24
Finished Aug 14 05:22:49 PM PDT 24
Peak memory 202460 kb
Host smart-75f62719-b1ad-4fd1-9a48-180a41398569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406602236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.406602236
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3831989784
Short name T701
Test name
Test status
Simulation time 29579573009 ps
CPU time 18.08 seconds
Started Aug 14 05:18:00 PM PDT 24
Finished Aug 14 05:18:18 PM PDT 24
Peak memory 201976 kb
Host smart-b12127c8-6c04-4d4e-aa53-6904f7745415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831989784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3831989784
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1910661793
Short name T124
Test name
Test status
Simulation time 4093188781 ps
CPU time 6.52 seconds
Started Aug 14 05:18:01 PM PDT 24
Finished Aug 14 05:18:07 PM PDT 24
Peak memory 202132 kb
Host smart-c652c38b-9680-4e9d-b119-0afaa4357883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910661793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1910661793
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2241833488
Short name T484
Test name
Test status
Simulation time 5837915610 ps
CPU time 14.94 seconds
Started Aug 14 05:18:01 PM PDT 24
Finished Aug 14 05:18:16 PM PDT 24
Peak memory 201876 kb
Host smart-c2ea1a9f-2cc3-4102-9bef-602dd27fd45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241833488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2241833488
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1816561852
Short name T194
Test name
Test status
Simulation time 334595875798 ps
CPU time 744.77 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:30:24 PM PDT 24
Peak memory 202148 kb
Host smart-70add354-5e85-4ac5-8536-fb6371d7b7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816561852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1816561852
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2476762918
Short name T201
Test name
Test status
Simulation time 3332036625 ps
CPU time 4.75 seconds
Started Aug 14 05:18:00 PM PDT 24
Finished Aug 14 05:18:05 PM PDT 24
Peak memory 202036 kb
Host smart-237e10c0-a338-4940-a25a-aa97af8c0f94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476762918 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2476762918
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3203758542
Short name T445
Test name
Test status
Simulation time 511130974 ps
CPU time 0.9 seconds
Started Aug 14 05:18:05 PM PDT 24
Finished Aug 14 05:18:06 PM PDT 24
Peak memory 201972 kb
Host smart-ab15d70b-3208-4b41-883e-ae127f747e10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203758542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3203758542
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2794542810
Short name T315
Test name
Test status
Simulation time 162834392316 ps
CPU time 100.93 seconds
Started Aug 14 05:17:56 PM PDT 24
Finished Aug 14 05:19:37 PM PDT 24
Peak memory 202144 kb
Host smart-8d09b35e-1f9d-45ce-ae8d-c2bc264f07c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794542810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2794542810
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.74276729
Short name T744
Test name
Test status
Simulation time 482622352943 ps
CPU time 484.26 seconds
Started Aug 14 05:18:05 PM PDT 24
Finished Aug 14 05:26:10 PM PDT 24
Peak memory 202128 kb
Host smart-c1b9c2e7-d82e-4682-8272-9ca23c000a5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=74276729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt
_fixed.74276729
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2752697598
Short name T220
Test name
Test status
Simulation time 333532583908 ps
CPU time 147.91 seconds
Started Aug 14 05:17:59 PM PDT 24
Finished Aug 14 05:20:27 PM PDT 24
Peak memory 202112 kb
Host smart-d5ad9733-c7bf-4104-81cf-fdf7e9acf6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752697598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2752697598
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1742602842
Short name T501
Test name
Test status
Simulation time 330174144953 ps
CPU time 176.32 seconds
Started Aug 14 05:17:57 PM PDT 24
Finished Aug 14 05:20:54 PM PDT 24
Peak memory 202116 kb
Host smart-2a2a7cda-cc72-4f7e-890d-016be8245111
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742602842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1742602842
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2618598832
Short name T710
Test name
Test status
Simulation time 596031814231 ps
CPU time 1357.39 seconds
Started Aug 14 05:18:05 PM PDT 24
Finished Aug 14 05:40:43 PM PDT 24
Peak memory 202196 kb
Host smart-c9e415c6-2df6-4623-90c4-61b43de70f99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618598832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2618598832
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2964604560
Short name T737
Test name
Test status
Simulation time 85951613259 ps
CPU time 437.96 seconds
Started Aug 14 05:18:05 PM PDT 24
Finished Aug 14 05:25:23 PM PDT 24
Peak memory 202384 kb
Host smart-ae8ead3c-9143-4735-8d6f-4e6013738077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964604560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2964604560
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1767138248
Short name T760
Test name
Test status
Simulation time 43638237414 ps
CPU time 22.69 seconds
Started Aug 14 05:18:13 PM PDT 24
Finished Aug 14 05:18:36 PM PDT 24
Peak memory 201880 kb
Host smart-87a2c7e2-908e-467a-90ce-bd33e72bb5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767138248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1767138248
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1264486961
Short name T474
Test name
Test status
Simulation time 4773455550 ps
CPU time 3.37 seconds
Started Aug 14 05:18:07 PM PDT 24
Finished Aug 14 05:18:10 PM PDT 24
Peak memory 201996 kb
Host smart-795b1f41-7198-4d0b-ab50-b1a9ee743b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264486961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1264486961
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.655635359
Short name T751
Test name
Test status
Simulation time 5592484932 ps
CPU time 8.18 seconds
Started Aug 14 05:18:00 PM PDT 24
Finished Aug 14 05:18:08 PM PDT 24
Peak memory 201960 kb
Host smart-6ffccb08-df67-4cdf-9a28-89fdfe7993e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655635359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.655635359
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.29928923
Short name T44
Test name
Test status
Simulation time 184880916293 ps
CPU time 110.68 seconds
Started Aug 14 05:18:06 PM PDT 24
Finished Aug 14 05:19:57 PM PDT 24
Peak memory 202124 kb
Host smart-d2dadabf-15bd-4a21-88b0-605f53c684a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29928923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.29928923
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3865834903
Short name T755
Test name
Test status
Simulation time 19585736218 ps
CPU time 13.92 seconds
Started Aug 14 05:18:07 PM PDT 24
Finished Aug 14 05:18:21 PM PDT 24
Peak memory 210476 kb
Host smart-0eac4a2c-f88b-4397-ba0d-9e0e7ae3d0c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865834903 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3865834903
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1220942655
Short name T460
Test name
Test status
Simulation time 435282886 ps
CPU time 0.92 seconds
Started Aug 14 05:18:20 PM PDT 24
Finished Aug 14 05:18:21 PM PDT 24
Peak memory 202036 kb
Host smart-644c158a-f33a-43c9-ab34-3ee5386b8aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220942655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1220942655
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2162048318
Short name T164
Test name
Test status
Simulation time 361687035470 ps
CPU time 715.58 seconds
Started Aug 14 05:18:06 PM PDT 24
Finished Aug 14 05:30:02 PM PDT 24
Peak memory 202144 kb
Host smart-e9fecb53-5cc7-4d74-a217-3d8b0815a17c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162048318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2162048318
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.4286425704
Short name T596
Test name
Test status
Simulation time 166009261010 ps
CPU time 110.05 seconds
Started Aug 14 05:18:13 PM PDT 24
Finished Aug 14 05:20:03 PM PDT 24
Peak memory 202068 kb
Host smart-309e3748-4a26-4a3b-a4c9-bf5117fdb65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286425704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4286425704
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1323622678
Short name T403
Test name
Test status
Simulation time 327333164415 ps
CPU time 406.21 seconds
Started Aug 14 05:18:07 PM PDT 24
Finished Aug 14 05:24:53 PM PDT 24
Peak memory 202156 kb
Host smart-59c91548-a2c2-46c3-a8a9-7a89a5084ccb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323622678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1323622678
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2212229768
Short name T341
Test name
Test status
Simulation time 494090818345 ps
CPU time 1116.61 seconds
Started Aug 14 05:18:11 PM PDT 24
Finished Aug 14 05:36:48 PM PDT 24
Peak memory 202052 kb
Host smart-9bb26469-92be-4ca2-9910-877c6b1cdda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212229768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2212229768
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1029495755
Short name T709
Test name
Test status
Simulation time 333231227682 ps
CPU time 725.2 seconds
Started Aug 14 05:18:06 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 202148 kb
Host smart-d744c206-ec8f-41bd-8870-de80f852f7bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029495755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1029495755
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.123024933
Short name T619
Test name
Test status
Simulation time 197951560617 ps
CPU time 118.62 seconds
Started Aug 14 05:18:05 PM PDT 24
Finished Aug 14 05:20:03 PM PDT 24
Peak memory 202128 kb
Host smart-4a908359-956a-4cac-a71b-c2d0d493e22b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123024933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.123024933
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.252645469
Short name T507
Test name
Test status
Simulation time 197424442124 ps
CPU time 232.22 seconds
Started Aug 14 05:18:06 PM PDT 24
Finished Aug 14 05:21:58 PM PDT 24
Peak memory 202148 kb
Host smart-4d7344b9-8ab7-41ac-91bb-2fd61bc93446
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252645469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.252645469
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.4024933409
Short name T97
Test name
Test status
Simulation time 63029367480 ps
CPU time 241.5 seconds
Started Aug 14 05:18:14 PM PDT 24
Finished Aug 14 05:22:16 PM PDT 24
Peak memory 202384 kb
Host smart-65e0ed39-43fe-49be-b9a3-bea976026b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024933409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.4024933409
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3384956969
Short name T714
Test name
Test status
Simulation time 27972956215 ps
CPU time 15.69 seconds
Started Aug 14 05:18:15 PM PDT 24
Finished Aug 14 05:18:31 PM PDT 24
Peak memory 201948 kb
Host smart-e03624ae-c764-4196-98eb-37ec530f5dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384956969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3384956969
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2068713356
Short name T382
Test name
Test status
Simulation time 5083485762 ps
CPU time 3.86 seconds
Started Aug 14 05:18:14 PM PDT 24
Finished Aug 14 05:18:18 PM PDT 24
Peak memory 201948 kb
Host smart-b12f18b0-f400-4e3d-a19a-68faa8036762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068713356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2068713356
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2535383639
Short name T98
Test name
Test status
Simulation time 5769940924 ps
CPU time 4.29 seconds
Started Aug 14 05:18:06 PM PDT 24
Finished Aug 14 05:18:10 PM PDT 24
Peak memory 201956 kb
Host smart-ad23b61b-e0bc-430b-82d3-0608e038ba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535383639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2535383639
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1908134143
Short name T234
Test name
Test status
Simulation time 109599634280 ps
CPU time 542.11 seconds
Started Aug 14 05:18:13 PM PDT 24
Finished Aug 14 05:27:16 PM PDT 24
Peak memory 210564 kb
Host smart-c4668238-b95f-4953-b95d-0c0504872d75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908134143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1908134143
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4251693217
Short name T207
Test name
Test status
Simulation time 12616704376 ps
CPU time 5.04 seconds
Started Aug 14 05:18:15 PM PDT 24
Finished Aug 14 05:18:20 PM PDT 24
Peak memory 202256 kb
Host smart-6f2a3cf9-a945-4915-8714-93c82d860b63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251693217 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.4251693217
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.212173129
Short name T90
Test name
Test status
Simulation time 539232064 ps
CPU time 1.06 seconds
Started Aug 14 05:18:16 PM PDT 24
Finished Aug 14 05:18:17 PM PDT 24
Peak memory 201988 kb
Host smart-ada59b9d-7033-4aaa-b544-f9f9540b9dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212173129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.212173129
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3637428637
Short name T298
Test name
Test status
Simulation time 349775704982 ps
CPU time 229.66 seconds
Started Aug 14 05:18:16 PM PDT 24
Finished Aug 14 05:22:05 PM PDT 24
Peak memory 202144 kb
Host smart-fea38cc1-8c06-4fc7-aacf-4e6fa4848e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637428637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3637428637
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.858341869
Short name T762
Test name
Test status
Simulation time 494310522458 ps
CPU time 126.78 seconds
Started Aug 14 05:18:13 PM PDT 24
Finished Aug 14 05:20:20 PM PDT 24
Peak memory 202176 kb
Host smart-bf51b63a-8c90-4911-b193-0609acda6f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858341869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.858341869
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.654751281
Short name T535
Test name
Test status
Simulation time 478851476676 ps
CPU time 292.84 seconds
Started Aug 14 05:18:15 PM PDT 24
Finished Aug 14 05:23:08 PM PDT 24
Peak memory 202120 kb
Host smart-b4709435-e5d0-41b5-a4fb-37639e1249fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=654751281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.654751281
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.18383567
Short name T189
Test name
Test status
Simulation time 492049395028 ps
CPU time 206.93 seconds
Started Aug 14 05:18:20 PM PDT 24
Finished Aug 14 05:21:47 PM PDT 24
Peak memory 202212 kb
Host smart-7b4967e5-44a6-427a-8831-e85603463f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18383567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.18383567
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3986557245
Short name T516
Test name
Test status
Simulation time 328396605801 ps
CPU time 691.49 seconds
Started Aug 14 05:18:15 PM PDT 24
Finished Aug 14 05:29:47 PM PDT 24
Peak memory 202108 kb
Host smart-5768a776-2e63-4157-add0-ba5a8869b4d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986557245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3986557245
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.892701900
Short name T34
Test name
Test status
Simulation time 189082551334 ps
CPU time 440.27 seconds
Started Aug 14 05:18:16 PM PDT 24
Finished Aug 14 05:25:37 PM PDT 24
Peak memory 202096 kb
Host smart-283bbcf8-04d2-48c3-80ed-64fe7cb7b90d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892701900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.892701900
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.921835885
Short name T509
Test name
Test status
Simulation time 392148539765 ps
CPU time 813.26 seconds
Started Aug 14 05:18:16 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 202148 kb
Host smart-fda2b2b5-0d4f-42bb-9eb0-ef59e8a9c6bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921835885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.921835885
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1258838274
Short name T376
Test name
Test status
Simulation time 97427862453 ps
CPU time 384.24 seconds
Started Aug 14 05:18:15 PM PDT 24
Finished Aug 14 05:24:39 PM PDT 24
Peak memory 202444 kb
Host smart-01494464-2d45-4520-bda4-2bf9f7c96327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258838274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1258838274
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.916575704
Short name T576
Test name
Test status
Simulation time 33634861904 ps
CPU time 72.86 seconds
Started Aug 14 05:18:15 PM PDT 24
Finished Aug 14 05:19:28 PM PDT 24
Peak memory 201972 kb
Host smart-ac113f27-5295-46dd-97ce-fb38302e7229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916575704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.916575704
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.4085377563
Short name T396
Test name
Test status
Simulation time 4978203750 ps
CPU time 2.21 seconds
Started Aug 14 05:18:14 PM PDT 24
Finished Aug 14 05:18:17 PM PDT 24
Peak memory 201968 kb
Host smart-daa47b32-6239-43a6-957f-bae9bc3965f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085377563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.4085377563
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2839664817
Short name T536
Test name
Test status
Simulation time 5709303881 ps
CPU time 14.44 seconds
Started Aug 14 05:18:13 PM PDT 24
Finished Aug 14 05:18:28 PM PDT 24
Peak memory 201956 kb
Host smart-c366e1ba-3a99-434c-95f9-811d0977c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839664817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2839664817
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2151358070
Short name T364
Test name
Test status
Simulation time 361984426271 ps
CPU time 223.96 seconds
Started Aug 14 05:18:15 PM PDT 24
Finished Aug 14 05:21:59 PM PDT 24
Peak memory 202352 kb
Host smart-2ee75e4e-b024-4b91-81a7-66d4301a1731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151358070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2151358070
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.461790
Short name T606
Test name
Test status
Simulation time 4874682258 ps
CPU time 8.88 seconds
Started Aug 14 05:18:14 PM PDT 24
Finished Aug 14 05:18:23 PM PDT 24
Peak memory 202532 kb
Host smart-d8af41a5-af66-45a0-a8fa-66be47641729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461790 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.461790
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.4279410786
Short name T736
Test name
Test status
Simulation time 492989974 ps
CPU time 0.92 seconds
Started Aug 14 05:18:25 PM PDT 24
Finished Aug 14 05:18:26 PM PDT 24
Peak memory 201996 kb
Host smart-f21865be-03d4-4c76-a39e-df2c2167d2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279410786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.4279410786
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1571502092
Short name T335
Test name
Test status
Simulation time 169502052698 ps
CPU time 208.43 seconds
Started Aug 14 05:18:23 PM PDT 24
Finished Aug 14 05:21:52 PM PDT 24
Peak memory 202052 kb
Host smart-30fe5931-187c-457f-8131-b09cf7251e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571502092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1571502092
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.736920883
Short name T117
Test name
Test status
Simulation time 160572965261 ps
CPU time 376.18 seconds
Started Aug 14 05:18:26 PM PDT 24
Finished Aug 14 05:24:43 PM PDT 24
Peak memory 202152 kb
Host smart-45eb5aa0-cd88-460e-a0c7-dc8edef3f9ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=736920883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.736920883
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1417031843
Short name T753
Test name
Test status
Simulation time 484676992459 ps
CPU time 1002.29 seconds
Started Aug 14 05:18:14 PM PDT 24
Finished Aug 14 05:34:56 PM PDT 24
Peak memory 202000 kb
Host smart-8bc2ea5b-5130-4dd8-86cd-5e8dca438f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417031843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1417031843
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.4226851369
Short name T437
Test name
Test status
Simulation time 325874779325 ps
CPU time 753.13 seconds
Started Aug 14 05:18:14 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 202112 kb
Host smart-1ff0bd07-8fde-4ab8-879d-76d99e0257b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226851369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.4226851369
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2266378951
Short name T353
Test name
Test status
Simulation time 416208777284 ps
CPU time 509.28 seconds
Started Aug 14 05:18:25 PM PDT 24
Finished Aug 14 05:26:55 PM PDT 24
Peak memory 202136 kb
Host smart-efa6cd92-ea7f-4fb0-ae40-f618aab90a27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266378951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2266378951
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2527962393
Short name T483
Test name
Test status
Simulation time 398520583766 ps
CPU time 167.77 seconds
Started Aug 14 05:18:25 PM PDT 24
Finished Aug 14 05:21:13 PM PDT 24
Peak memory 202140 kb
Host smart-00e048b5-1efc-4705-a681-0893c2c0430d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527962393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2527962393
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.938997319
Short name T385
Test name
Test status
Simulation time 25655616330 ps
CPU time 4.78 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:18:29 PM PDT 24
Peak memory 201916 kb
Host smart-f79c931d-1454-49a9-b687-0256b6218108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938997319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.938997319
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.400449856
Short name T625
Test name
Test status
Simulation time 3752923032 ps
CPU time 9.71 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:18:34 PM PDT 24
Peak memory 201960 kb
Host smart-4048002f-40a9-4540-a965-9144b8319b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400449856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.400449856
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3740290511
Short name T630
Test name
Test status
Simulation time 5897425440 ps
CPU time 2.06 seconds
Started Aug 14 05:18:20 PM PDT 24
Finished Aug 14 05:18:22 PM PDT 24
Peak memory 202024 kb
Host smart-b5032048-bc4d-4e0d-9742-364c48ac3487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740290511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3740290511
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1761335778
Short name T546
Test name
Test status
Simulation time 1157534540 ps
CPU time 3.64 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:18:27 PM PDT 24
Peak memory 202052 kb
Host smart-f33967b1-91fc-4b4b-8a4f-dbbb46a7b098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761335778 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1761335778
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2608606205
Short name T511
Test name
Test status
Simulation time 441002497 ps
CPU time 0.69 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:18:25 PM PDT 24
Peak memory 201980 kb
Host smart-9a2a809a-a820-474b-bc6a-ff8438608a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608606205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2608606205
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2964267032
Short name T355
Test name
Test status
Simulation time 545955427051 ps
CPU time 811.04 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:31:55 PM PDT 24
Peak memory 202164 kb
Host smart-a38458d6-9a20-4bc5-af15-10b69d25381f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964267032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2964267032
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1593617902
Short name T651
Test name
Test status
Simulation time 328095609126 ps
CPU time 724.4 seconds
Started Aug 14 05:18:23 PM PDT 24
Finished Aug 14 05:30:28 PM PDT 24
Peak memory 202172 kb
Host smart-1d4b66f1-e25d-4796-889a-42e192fd2d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593617902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1593617902
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2588175345
Short name T726
Test name
Test status
Simulation time 322279400080 ps
CPU time 731.95 seconds
Started Aug 14 05:18:26 PM PDT 24
Finished Aug 14 05:30:38 PM PDT 24
Peak memory 202196 kb
Host smart-742f376f-754c-48e6-979c-16398de5154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588175345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2588175345
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1833371675
Short name T480
Test name
Test status
Simulation time 321730463357 ps
CPU time 102.76 seconds
Started Aug 14 05:18:23 PM PDT 24
Finished Aug 14 05:20:06 PM PDT 24
Peak memory 202156 kb
Host smart-9605185a-b9c8-4b07-bd01-7577c4ca1d93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833371675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1833371675
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3760785497
Short name T586
Test name
Test status
Simulation time 327491339631 ps
CPU time 142.55 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:20:47 PM PDT 24
Peak memory 202152 kb
Host smart-384a8373-1bc1-4b4c-b69f-e44700b7eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760785497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3760785497
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2777652028
Short name T657
Test name
Test status
Simulation time 489885268580 ps
CPU time 554.21 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:27:38 PM PDT 24
Peak memory 202148 kb
Host smart-e332acba-0fb8-4940-a11a-b67c81315e85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777652028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2777652028
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2075870024
Short name T595
Test name
Test status
Simulation time 198989707935 ps
CPU time 112.67 seconds
Started Aug 14 05:18:25 PM PDT 24
Finished Aug 14 05:20:18 PM PDT 24
Peak memory 202096 kb
Host smart-5e2ea81c-9473-44f7-a211-28bbf790d24a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075870024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2075870024
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2088142844
Short name T740
Test name
Test status
Simulation time 406978628067 ps
CPU time 417.51 seconds
Started Aug 14 05:18:27 PM PDT 24
Finished Aug 14 05:25:25 PM PDT 24
Peak memory 202060 kb
Host smart-aff1024f-9a4e-4a39-9ef1-4e89c8d1d182
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088142844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2088142844
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.631117367
Short name T683
Test name
Test status
Simulation time 111507139343 ps
CPU time 630.8 seconds
Started Aug 14 05:18:25 PM PDT 24
Finished Aug 14 05:28:56 PM PDT 24
Peak memory 202432 kb
Host smart-9b56861c-ecd4-4294-99eb-8a30fe2c622d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631117367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.631117367
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3937289986
Short name T514
Test name
Test status
Simulation time 36198464469 ps
CPU time 11.77 seconds
Started Aug 14 05:18:26 PM PDT 24
Finished Aug 14 05:18:38 PM PDT 24
Peak memory 201916 kb
Host smart-88e07490-1fe8-4885-abaf-cdf4e23a7877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937289986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3937289986
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1343117125
Short name T524
Test name
Test status
Simulation time 4116670102 ps
CPU time 3.48 seconds
Started Aug 14 05:18:27 PM PDT 24
Finished Aug 14 05:18:30 PM PDT 24
Peak memory 201980 kb
Host smart-70234037-e4b5-4930-9873-ed00a2055075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343117125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1343117125
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.4011413324
Short name T489
Test name
Test status
Simulation time 5708295356 ps
CPU time 15.68 seconds
Started Aug 14 05:18:25 PM PDT 24
Finished Aug 14 05:18:41 PM PDT 24
Peak memory 201920 kb
Host smart-4c402c13-f7e9-4ed4-b43d-2d9b3191bd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011413324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4011413324
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1219933609
Short name T251
Test name
Test status
Simulation time 202347741219 ps
CPU time 119.84 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:20:24 PM PDT 24
Peak memory 202104 kb
Host smart-9bbb30c6-f32c-47f9-9163-8aa55e0e10e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219933609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1219933609
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2268007753
Short name T757
Test name
Test status
Simulation time 3890895106 ps
CPU time 11.23 seconds
Started Aug 14 05:18:27 PM PDT 24
Finished Aug 14 05:18:38 PM PDT 24
Peak memory 210484 kb
Host smart-324727b1-3b2f-4560-97e7-c667c16d8f1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268007753 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2268007753
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.591234817
Short name T517
Test name
Test status
Simulation time 440069822 ps
CPU time 1.53 seconds
Started Aug 14 05:18:33 PM PDT 24
Finished Aug 14 05:18:35 PM PDT 24
Peak memory 201996 kb
Host smart-45e5183e-8192-4699-b210-8b4559ce4f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591234817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.591234817
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3255996159
Short name T272
Test name
Test status
Simulation time 167333570225 ps
CPU time 96.78 seconds
Started Aug 14 05:18:33 PM PDT 24
Finished Aug 14 05:20:10 PM PDT 24
Peak memory 202148 kb
Host smart-c47c444d-c57c-4075-a920-a997bddd0f3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255996159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3255996159
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.425361264
Short name T343
Test name
Test status
Simulation time 164390801016 ps
CPU time 63.19 seconds
Started Aug 14 05:18:35 PM PDT 24
Finished Aug 14 05:19:38 PM PDT 24
Peak memory 202216 kb
Host smart-41cd8ce2-2554-4201-ab00-ddc7b0c5a569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425361264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.425361264
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3868789891
Short name T616
Test name
Test status
Simulation time 330601019134 ps
CPU time 385.88 seconds
Started Aug 14 05:18:31 PM PDT 24
Finished Aug 14 05:24:57 PM PDT 24
Peak memory 202112 kb
Host smart-d238a793-7019-4dd3-94b7-0c3509487560
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868789891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3868789891
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2517861239
Short name T570
Test name
Test status
Simulation time 504415105765 ps
CPU time 240.44 seconds
Started Aug 14 05:18:34 PM PDT 24
Finished Aug 14 05:22:35 PM PDT 24
Peak memory 202144 kb
Host smart-f8a70cd2-f9e9-4f3d-b928-372ab187884d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517861239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2517861239
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1014530099
Short name T464
Test name
Test status
Simulation time 379430251518 ps
CPU time 413.82 seconds
Started Aug 14 05:18:31 PM PDT 24
Finished Aug 14 05:25:26 PM PDT 24
Peak memory 202084 kb
Host smart-665cc5dc-fab5-4b7b-8308-088b9c85a99b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014530099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1014530099
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1959388876
Short name T571
Test name
Test status
Simulation time 146472544781 ps
CPU time 445.03 seconds
Started Aug 14 05:18:37 PM PDT 24
Finished Aug 14 05:26:02 PM PDT 24
Peak memory 202388 kb
Host smart-9f4ad8cd-fd1d-4c3c-b46e-056e49f67641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959388876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1959388876
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1870709810
Short name T166
Test name
Test status
Simulation time 43764439655 ps
CPU time 53.63 seconds
Started Aug 14 05:18:34 PM PDT 24
Finished Aug 14 05:19:28 PM PDT 24
Peak memory 202024 kb
Host smart-b3138cb3-a1f4-48cb-8bb6-e5a9baae3ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870709810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1870709810
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.888368016
Short name T429
Test name
Test status
Simulation time 4105986470 ps
CPU time 9.43 seconds
Started Aug 14 05:18:36 PM PDT 24
Finished Aug 14 05:18:45 PM PDT 24
Peak memory 201956 kb
Host smart-dbf71f30-acf7-4b51-be05-6f67bd93a3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888368016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.888368016
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.936357537
Short name T36
Test name
Test status
Simulation time 5915783414 ps
CPU time 13.76 seconds
Started Aug 14 05:18:24 PM PDT 24
Finished Aug 14 05:18:38 PM PDT 24
Peak memory 201956 kb
Host smart-32e71e14-9a68-4818-a992-c187a75a6c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936357537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.936357537
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1936048747
Short name T72
Test name
Test status
Simulation time 1322163938 ps
CPU time 8.46 seconds
Started Aug 14 05:18:34 PM PDT 24
Finished Aug 14 05:18:42 PM PDT 24
Peak memory 202048 kb
Host smart-2db029bc-bec6-4c8a-bb1d-8d8b10a86ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936048747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1936048747
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3937996947
Short name T543
Test name
Test status
Simulation time 429140637 ps
CPU time 0.79 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:18:42 PM PDT 24
Peak memory 201992 kb
Host smart-359e36e9-32f0-482b-a5b0-7863338e3d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937996947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3937996947
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.4008927803
Short name T204
Test name
Test status
Simulation time 510856995681 ps
CPU time 1193.85 seconds
Started Aug 14 05:18:40 PM PDT 24
Finished Aug 14 05:38:34 PM PDT 24
Peak memory 202104 kb
Host smart-a7682552-b94f-4e3f-b327-ebb3266544c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008927803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.4008927803
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3670979139
Short name T695
Test name
Test status
Simulation time 208920471526 ps
CPU time 444.11 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:26:06 PM PDT 24
Peak memory 202196 kb
Host smart-7a1f0eff-c894-4584-91e8-835f701a32cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670979139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3670979139
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3499249166
Short name T703
Test name
Test status
Simulation time 314938545849 ps
CPU time 745.13 seconds
Started Aug 14 05:18:33 PM PDT 24
Finished Aug 14 05:30:58 PM PDT 24
Peak memory 202144 kb
Host smart-e8e7b17a-bbb5-417c-a6f6-83bd183ee312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499249166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3499249166
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1285039541
Short name T731
Test name
Test status
Simulation time 488109475151 ps
CPU time 304.77 seconds
Started Aug 14 05:18:31 PM PDT 24
Finished Aug 14 05:23:36 PM PDT 24
Peak memory 202040 kb
Host smart-20a5326a-0d8d-457d-a9bb-f9557c330123
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285039541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1285039541
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.100483786
Short name T279
Test name
Test status
Simulation time 493517839921 ps
CPU time 302.19 seconds
Started Aug 14 05:18:32 PM PDT 24
Finished Aug 14 05:23:35 PM PDT 24
Peak memory 202196 kb
Host smart-54e70b00-db57-498b-809e-107233377e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100483786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.100483786
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3760197161
Short name T478
Test name
Test status
Simulation time 164703558739 ps
CPU time 397 seconds
Started Aug 14 05:18:34 PM PDT 24
Finished Aug 14 05:25:11 PM PDT 24
Peak memory 202112 kb
Host smart-8f25f485-9573-4fd2-b4c1-88143fd564fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760197161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3760197161
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.116553812
Short name T267
Test name
Test status
Simulation time 199090979915 ps
CPU time 124.77 seconds
Started Aug 14 05:18:32 PM PDT 24
Finished Aug 14 05:20:37 PM PDT 24
Peak memory 202168 kb
Host smart-9e15d050-e54b-4ed8-b3fc-ff53711eb748
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116553812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.116553812
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3265379230
Short name T537
Test name
Test status
Simulation time 219365328012 ps
CPU time 507.93 seconds
Started Aug 14 05:18:37 PM PDT 24
Finished Aug 14 05:27:05 PM PDT 24
Peak memory 202124 kb
Host smart-43e7d5f9-4caa-43bb-b02a-59697b3679ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265379230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3265379230
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3501461604
Short name T604
Test name
Test status
Simulation time 28001808948 ps
CPU time 20.7 seconds
Started Aug 14 05:18:42 PM PDT 24
Finished Aug 14 05:19:03 PM PDT 24
Peak memory 201944 kb
Host smart-72d22581-5d52-48b3-a2b9-c2c14f103c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501461604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3501461604
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3514444744
Short name T472
Test name
Test status
Simulation time 3198979330 ps
CPU time 5.59 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:18:46 PM PDT 24
Peak memory 201860 kb
Host smart-bc533c5f-2656-4bc6-823d-0a2130b9eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514444744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3514444744
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.240092954
Short name T522
Test name
Test status
Simulation time 5962668087 ps
CPU time 14.99 seconds
Started Aug 14 05:18:34 PM PDT 24
Finished Aug 14 05:18:49 PM PDT 24
Peak memory 201980 kb
Host smart-ef0825b3-0884-4db0-8b51-4a14d6dc786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240092954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.240092954
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.340769169
Short name T365
Test name
Test status
Simulation time 174646973388 ps
CPU time 110.27 seconds
Started Aug 14 05:18:44 PM PDT 24
Finished Aug 14 05:20:35 PM PDT 24
Peak memory 202128 kb
Host smart-1088897b-e124-495f-9023-c564cf8b7053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340769169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
340769169
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1862626845
Short name T101
Test name
Test status
Simulation time 3027403333 ps
CPU time 16.28 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:18:58 PM PDT 24
Peak memory 210796 kb
Host smart-8fe69a25-70b4-476d-9f6b-6275c22266a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862626845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1862626845
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2815172938
Short name T25
Test name
Test status
Simulation time 512233144 ps
CPU time 1.24 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:17:09 PM PDT 24
Peak memory 201984 kb
Host smart-e62c152c-6b60-4442-b152-e37022975498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815172938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2815172938
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3164789798
Short name T310
Test name
Test status
Simulation time 436144109836 ps
CPU time 902.5 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 202144 kb
Host smart-b2130dec-bbd4-4fc8-b628-0430dc2330fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164789798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3164789798
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1844413500
Short name T276
Test name
Test status
Simulation time 326835214861 ps
CPU time 714.59 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:29:03 PM PDT 24
Peak memory 202204 kb
Host smart-3e55f5b1-2a70-4c65-a603-a7736f83466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844413500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1844413500
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2258263560
Short name T490
Test name
Test status
Simulation time 162653559413 ps
CPU time 197.67 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:20:26 PM PDT 24
Peak memory 202208 kb
Host smart-fac92979-4fa5-4f92-a2a7-1a123a827aaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258263560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2258263560
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.33994899
Short name T669
Test name
Test status
Simulation time 167672795151 ps
CPU time 375.63 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:23:23 PM PDT 24
Peak memory 202144 kb
Host smart-bf60fcb3-99a0-409f-8e21-1e25e8343f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33994899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.33994899
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3248720054
Short name T602
Test name
Test status
Simulation time 496518181890 ps
CPU time 562.6 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:26:30 PM PDT 24
Peak memory 202084 kb
Host smart-8ef8ec18-4b65-4272-800c-583ca3a448de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248720054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3248720054
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.197298762
Short name T243
Test name
Test status
Simulation time 374210027295 ps
CPU time 807.89 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:30:36 PM PDT 24
Peak memory 202132 kb
Host smart-572ed2ce-8fcb-447d-8fc3-de785a60b0e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197298762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.197298762
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2326682035
Short name T404
Test name
Test status
Simulation time 192318558229 ps
CPU time 113.36 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:19:01 PM PDT 24
Peak memory 202184 kb
Host smart-e2ad9cf9-cbbb-49a6-afb2-9fac89b7645f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326682035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2326682035
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2745473206
Short name T636
Test name
Test status
Simulation time 83543684719 ps
CPU time 301.04 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:22:08 PM PDT 24
Peak memory 202408 kb
Host smart-5472fc89-a198-4567-9766-b2c46330a88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745473206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2745473206
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3132772241
Short name T521
Test name
Test status
Simulation time 27204145597 ps
CPU time 17.17 seconds
Started Aug 14 05:17:10 PM PDT 24
Finished Aug 14 05:17:28 PM PDT 24
Peak memory 201976 kb
Host smart-bb99aa70-8eea-468c-97c0-795808ad296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132772241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3132772241
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.4040616123
Short name T428
Test name
Test status
Simulation time 4286530535 ps
CPU time 10.3 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:17:17 PM PDT 24
Peak memory 201960 kb
Host smart-febad0b3-6de6-4df4-80ca-8439a47e7f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040616123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4040616123
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3060216751
Short name T76
Test name
Test status
Simulation time 4280211124 ps
CPU time 9.44 seconds
Started Aug 14 05:17:05 PM PDT 24
Finished Aug 14 05:17:14 PM PDT 24
Peak memory 217448 kb
Host smart-4ed787fd-c21d-40f4-bb39-a7f7d2e246c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060216751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3060216751
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3349592085
Short name T150
Test name
Test status
Simulation time 5626050612 ps
CPU time 13.83 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:17:22 PM PDT 24
Peak memory 201972 kb
Host smart-624b1478-838f-4a50-9165-f6fde850f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349592085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3349592085
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3099972367
Short name T248
Test name
Test status
Simulation time 327060405507 ps
CPU time 210.19 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:20:39 PM PDT 24
Peak memory 202124 kb
Host smart-f88d0fec-ea78-4568-86c0-1be87b2e3ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099972367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3099972367
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.779715343
Short name T50
Test name
Test status
Simulation time 3960430712 ps
CPU time 4.42 seconds
Started Aug 14 05:17:06 PM PDT 24
Finished Aug 14 05:17:11 PM PDT 24
Peak memory 210464 kb
Host smart-a7eed44d-2168-4d57-98cd-ed6516f67166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779715343 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.779715343
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3354437491
Short name T544
Test name
Test status
Simulation time 417118827 ps
CPU time 0.74 seconds
Started Aug 14 05:18:40 PM PDT 24
Finished Aug 14 05:18:41 PM PDT 24
Peak memory 201988 kb
Host smart-5a7f49d0-be3f-4f2f-b9a3-8e93cbc582f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354437491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3354437491
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3237635763
Short name T787
Test name
Test status
Simulation time 173897585145 ps
CPU time 217.38 seconds
Started Aug 14 05:18:42 PM PDT 24
Finished Aug 14 05:22:19 PM PDT 24
Peak memory 202128 kb
Host smart-b58dfe94-ad90-4662-908f-eba1afc45e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237635763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3237635763
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1900542689
Short name T684
Test name
Test status
Simulation time 159236696771 ps
CPU time 58.22 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:19:39 PM PDT 24
Peak memory 202124 kb
Host smart-ae559aa2-9a77-4f18-b01f-7e517a220fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900542689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1900542689
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3022852331
Short name T618
Test name
Test status
Simulation time 325798026900 ps
CPU time 189.44 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:21:50 PM PDT 24
Peak memory 202144 kb
Host smart-cf1ef55e-c573-4937-a366-208372108374
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022852331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3022852331
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2284970014
Short name T668
Test name
Test status
Simulation time 161020304100 ps
CPU time 385.74 seconds
Started Aug 14 05:18:43 PM PDT 24
Finished Aug 14 05:25:09 PM PDT 24
Peak memory 202128 kb
Host smart-7db8a91c-7309-4efb-bf64-b3264c1c76de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284970014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2284970014
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.466404516
Short name T462
Test name
Test status
Simulation time 497275525785 ps
CPU time 1115.86 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:37:17 PM PDT 24
Peak memory 202132 kb
Host smart-2ac3df6d-48c7-4f31-9453-fb8d89927003
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=466404516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.466404516
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2458402056
Short name T622
Test name
Test status
Simulation time 386602213095 ps
CPU time 461.84 seconds
Started Aug 14 05:18:40 PM PDT 24
Finished Aug 14 05:26:22 PM PDT 24
Peak memory 202120 kb
Host smart-7b9dcf8c-1002-4d0e-9505-d94465849797
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458402056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2458402056
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3618759596
Short name T64
Test name
Test status
Simulation time 101150736195 ps
CPU time 323.69 seconds
Started Aug 14 05:18:44 PM PDT 24
Finished Aug 14 05:24:08 PM PDT 24
Peak memory 202436 kb
Host smart-3253c6da-638c-4be4-9e41-d6ce872d5dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618759596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3618759596
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.778286458
Short name T670
Test name
Test status
Simulation time 32910658039 ps
CPU time 17.49 seconds
Started Aug 14 05:18:45 PM PDT 24
Finished Aug 14 05:19:03 PM PDT 24
Peak memory 201956 kb
Host smart-95dc76c9-1a16-4c2b-a565-527f25786d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778286458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.778286458
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2051671559
Short name T177
Test name
Test status
Simulation time 4981508251 ps
CPU time 1.86 seconds
Started Aug 14 05:18:42 PM PDT 24
Finished Aug 14 05:18:44 PM PDT 24
Peak memory 201976 kb
Host smart-0e20d3ad-7991-4e86-9ffe-42cba937e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051671559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2051671559
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.596762116
Short name T632
Test name
Test status
Simulation time 5827040492 ps
CPU time 3.12 seconds
Started Aug 14 05:18:45 PM PDT 24
Finished Aug 14 05:18:49 PM PDT 24
Peak memory 201956 kb
Host smart-821ad5f4-a38b-4b53-b976-f1f4ae57b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596762116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.596762116
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2767119954
Short name T378
Test name
Test status
Simulation time 281573154277 ps
CPU time 666.77 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:29:48 PM PDT 24
Peak memory 202448 kb
Host smart-8882f9ac-d2da-49b5-bd41-183ce8a1b75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767119954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2767119954
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2749781427
Short name T674
Test name
Test status
Simulation time 53743781038 ps
CPU time 15.62 seconds
Started Aug 14 05:18:41 PM PDT 24
Finished Aug 14 05:18:56 PM PDT 24
Peak memory 210488 kb
Host smart-0bf0534e-7f32-46b8-99a3-e30b44008bb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749781427 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2749781427
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3491601187
Short name T776
Test name
Test status
Simulation time 371707640 ps
CPU time 1.09 seconds
Started Aug 14 05:18:51 PM PDT 24
Finished Aug 14 05:18:52 PM PDT 24
Peak memory 201980 kb
Host smart-bfb15294-5a34-48aa-9557-70eb5c9652d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491601187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3491601187
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1957057989
Short name T296
Test name
Test status
Simulation time 531868444501 ps
CPU time 1200.1 seconds
Started Aug 14 05:18:49 PM PDT 24
Finished Aug 14 05:38:50 PM PDT 24
Peak memory 202160 kb
Host smart-881ac2dd-d298-4691-b104-f1647e533828
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957057989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1957057989
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2466241468
Short name T344
Test name
Test status
Simulation time 165072978500 ps
CPU time 211.43 seconds
Started Aug 14 05:18:51 PM PDT 24
Finished Aug 14 05:22:22 PM PDT 24
Peak memory 202148 kb
Host smart-90c21c8b-d5e6-4116-ba56-74d15100722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466241468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2466241468
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2038818577
Short name T465
Test name
Test status
Simulation time 328698471339 ps
CPU time 775.47 seconds
Started Aug 14 05:18:50 PM PDT 24
Finished Aug 14 05:31:45 PM PDT 24
Peak memory 202060 kb
Host smart-ec01cde3-c96e-481c-b262-ca6df692f903
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038818577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2038818577
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2760069063
Short name T212
Test name
Test status
Simulation time 491128547574 ps
CPU time 175.42 seconds
Started Aug 14 05:18:45 PM PDT 24
Finished Aug 14 05:21:41 PM PDT 24
Peak memory 202132 kb
Host smart-45eadadb-e916-4281-be04-2aff9e6c17ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760069063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2760069063
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2497847340
Short name T615
Test name
Test status
Simulation time 162857147469 ps
CPU time 186.42 seconds
Started Aug 14 05:18:45 PM PDT 24
Finished Aug 14 05:21:51 PM PDT 24
Peak memory 202116 kb
Host smart-a00c547b-16dd-4c50-8302-962c77c789c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497847340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2497847340
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.237064673
Short name T156
Test name
Test status
Simulation time 509327667110 ps
CPU time 1135.82 seconds
Started Aug 14 05:18:50 PM PDT 24
Finished Aug 14 05:37:46 PM PDT 24
Peak memory 202108 kb
Host smart-34308eb7-ad46-4dd9-8063-b2219baba7b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237064673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.237064673
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2854064921
Short name T432
Test name
Test status
Simulation time 617359889220 ps
CPU time 747.62 seconds
Started Aug 14 05:18:52 PM PDT 24
Finished Aug 14 05:31:20 PM PDT 24
Peak memory 202148 kb
Host smart-89214721-9269-4eb4-8897-5e90cfc0e386
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854064921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2854064921
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3191297541
Short name T766
Test name
Test status
Simulation time 111862879501 ps
CPU time 591.13 seconds
Started Aug 14 05:18:53 PM PDT 24
Finished Aug 14 05:28:44 PM PDT 24
Peak memory 202376 kb
Host smart-093eb797-8e67-458d-a613-872ccb14d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191297541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3191297541
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4205654313
Short name T761
Test name
Test status
Simulation time 30541570091 ps
CPU time 6.73 seconds
Started Aug 14 05:18:51 PM PDT 24
Finished Aug 14 05:18:58 PM PDT 24
Peak memory 201960 kb
Host smart-4e5aaee6-46bb-496d-84d9-621bb39d9e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205654313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4205654313
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2989699651
Short name T727
Test name
Test status
Simulation time 5128753241 ps
CPU time 6.48 seconds
Started Aug 14 05:18:51 PM PDT 24
Finished Aug 14 05:18:58 PM PDT 24
Peak memory 201972 kb
Host smart-6961d909-5760-49c9-99dd-f4e31437a7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989699651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2989699651
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3874902431
Short name T655
Test name
Test status
Simulation time 5642335849 ps
CPU time 4.25 seconds
Started Aug 14 05:18:48 PM PDT 24
Finished Aug 14 05:18:53 PM PDT 24
Peak memory 201972 kb
Host smart-fc37d8e7-bed8-4737-ab18-456c164930bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874902431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3874902431
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1299071535
Short name T476
Test name
Test status
Simulation time 5780683984 ps
CPU time 13.82 seconds
Started Aug 14 05:18:51 PM PDT 24
Finished Aug 14 05:19:05 PM PDT 24
Peak memory 210468 kb
Host smart-843896d6-da22-4006-8cf8-7ad72150a63b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299071535 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1299071535
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3739141937
Short name T35
Test name
Test status
Simulation time 408135059 ps
CPU time 1.56 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:19:01 PM PDT 24
Peak memory 201904 kb
Host smart-bb205ccd-7b9a-444d-86f0-db90d3eeca14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739141937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3739141937
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1063668675
Short name T28
Test name
Test status
Simulation time 159460903397 ps
CPU time 184.94 seconds
Started Aug 14 05:19:01 PM PDT 24
Finished Aug 14 05:22:06 PM PDT 24
Peak memory 202116 kb
Host smart-2d968e83-b3f7-4058-acae-d2f3253c38a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063668675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1063668675
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1752182073
Short name T319
Test name
Test status
Simulation time 172940971799 ps
CPU time 106.27 seconds
Started Aug 14 05:19:01 PM PDT 24
Finished Aug 14 05:20:47 PM PDT 24
Peak memory 202144 kb
Host smart-5063ae58-309b-4e42-84f4-73b8085c6696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752182073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1752182073
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.4038647608
Short name T203
Test name
Test status
Simulation time 325333503068 ps
CPU time 196.94 seconds
Started Aug 14 05:18:52 PM PDT 24
Finished Aug 14 05:22:09 PM PDT 24
Peak memory 202152 kb
Host smart-14deafde-726a-49a5-8078-03e43e4a9799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038647608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.4038647608
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.295055109
Short name T447
Test name
Test status
Simulation time 321172050148 ps
CPU time 211.89 seconds
Started Aug 14 05:18:52 PM PDT 24
Finished Aug 14 05:22:24 PM PDT 24
Peak memory 202116 kb
Host smart-8022deb1-bf59-4b72-bc27-f244dd6bcddd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=295055109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.295055109
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2609263578
Short name T352
Test name
Test status
Simulation time 166817799775 ps
CPU time 185.76 seconds
Started Aug 14 05:18:50 PM PDT 24
Finished Aug 14 05:21:56 PM PDT 24
Peak memory 202168 kb
Host smart-9adb4d57-3600-4225-97e4-ec93f92d132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609263578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2609263578
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3511535480
Short name T165
Test name
Test status
Simulation time 157548728630 ps
CPU time 369.49 seconds
Started Aug 14 05:18:53 PM PDT 24
Finished Aug 14 05:25:02 PM PDT 24
Peak memory 202132 kb
Host smart-652fb342-c7a1-4c0c-a595-1255f710d1d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511535480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3511535480
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3212705144
Short name T269
Test name
Test status
Simulation time 567655357907 ps
CPU time 304.33 seconds
Started Aug 14 05:18:53 PM PDT 24
Finished Aug 14 05:23:57 PM PDT 24
Peak memory 202128 kb
Host smart-f7e284ad-dac2-47cf-a9e9-15fa1d9065eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212705144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3212705144
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.429964630
Short name T199
Test name
Test status
Simulation time 403657315449 ps
CPU time 459.65 seconds
Started Aug 14 05:18:49 PM PDT 24
Finished Aug 14 05:26:29 PM PDT 24
Peak memory 202124 kb
Host smart-61b6fd07-80d0-4b09-9403-62ad5ee30e8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429964630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.429964630
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3016848422
Short name T610
Test name
Test status
Simulation time 128405933284 ps
CPU time 408.76 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:25:49 PM PDT 24
Peak memory 202428 kb
Host smart-783f4f71-28de-472a-87e1-d26683f50d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016848422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3016848422
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3905472117
Short name T407
Test name
Test status
Simulation time 39771114879 ps
CPU time 22.2 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:19:22 PM PDT 24
Peak memory 201948 kb
Host smart-a45222a4-ba35-4a7e-ba4e-6d1cddedfe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905472117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3905472117
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2025861965
Short name T467
Test name
Test status
Simulation time 3302785577 ps
CPU time 8.02 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:19:08 PM PDT 24
Peak memory 201928 kb
Host smart-a285ef63-eeb8-4128-9fc6-a9315c2f8a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025861965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2025861965
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.670201337
Short name T444
Test name
Test status
Simulation time 6065941094 ps
CPU time 4.39 seconds
Started Aug 14 05:18:51 PM PDT 24
Finished Aug 14 05:18:56 PM PDT 24
Peak memory 201944 kb
Host smart-ea099346-ab73-44c9-bf9f-f1f3d00ab89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670201337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.670201337
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3517292541
Short name T172
Test name
Test status
Simulation time 398412270931 ps
CPU time 480.2 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:27:00 PM PDT 24
Peak memory 202100 kb
Host smart-07c5b286-b2d6-4965-bebe-30d714b2a0c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517292541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3517292541
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2953603572
Short name T550
Test name
Test status
Simulation time 6323248807 ps
CPU time 8.67 seconds
Started Aug 14 05:19:01 PM PDT 24
Finished Aug 14 05:19:09 PM PDT 24
Peak memory 210488 kb
Host smart-76173b6a-6e2b-46bf-b747-02bbe1d1a1e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953603572 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2953603572
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.4270950087
Short name T647
Test name
Test status
Simulation time 475076822 ps
CPU time 1.14 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:19:01 PM PDT 24
Peak memory 202008 kb
Host smart-b2efdecc-f694-4946-a2a7-f650533e4507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270950087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4270950087
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2287242943
Short name T362
Test name
Test status
Simulation time 271986209667 ps
CPU time 157.45 seconds
Started Aug 14 05:19:01 PM PDT 24
Finished Aug 14 05:21:39 PM PDT 24
Peak memory 202132 kb
Host smart-33d2242b-ec96-4d8f-ad8f-a42e228cd11d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287242943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2287242943
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2686569260
Short name T611
Test name
Test status
Simulation time 526084124362 ps
CPU time 1233.64 seconds
Started Aug 14 05:19:03 PM PDT 24
Finished Aug 14 05:39:37 PM PDT 24
Peak memory 202200 kb
Host smart-3c7a045e-8891-4d73-b69e-56e0ecdf9938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686569260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2686569260
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1260644130
Short name T214
Test name
Test status
Simulation time 497169457996 ps
CPU time 351.46 seconds
Started Aug 14 05:18:59 PM PDT 24
Finished Aug 14 05:24:51 PM PDT 24
Peak memory 202216 kb
Host smart-d25b3535-aa3b-409b-aa42-30043cd74633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260644130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1260644130
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1816626393
Short name T643
Test name
Test status
Simulation time 324995056853 ps
CPU time 378.01 seconds
Started Aug 14 05:19:02 PM PDT 24
Finished Aug 14 05:25:20 PM PDT 24
Peak memory 202152 kb
Host smart-34a23a7d-3d33-4e4f-8a28-b042e329f85c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816626393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1816626393
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3398682942
Short name T448
Test name
Test status
Simulation time 329417894733 ps
CPU time 369.23 seconds
Started Aug 14 05:19:03 PM PDT 24
Finished Aug 14 05:25:12 PM PDT 24
Peak memory 202212 kb
Host smart-399d82ab-6539-42b8-8d3a-6cf4f5d0a279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398682942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3398682942
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.221080538
Short name T37
Test name
Test status
Simulation time 326355315171 ps
CPU time 808.87 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 202144 kb
Host smart-dd3f7daa-483d-4043-949e-a2e40773f258
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=221080538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.221080538
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3402399060
Short name T29
Test name
Test status
Simulation time 552142776383 ps
CPU time 830.15 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:32:50 PM PDT 24
Peak memory 202128 kb
Host smart-2dbfd87b-519a-42aa-9a50-83fb4a954fe0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402399060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3402399060
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.748598992
Short name T439
Test name
Test status
Simulation time 201302811736 ps
CPU time 226.77 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:22:46 PM PDT 24
Peak memory 202064 kb
Host smart-5b8f3664-64bf-41ce-98f1-6355bd5b6776
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748598992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.748598992
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2854234621
Short name T427
Test name
Test status
Simulation time 34342244169 ps
CPU time 79.7 seconds
Started Aug 14 05:19:01 PM PDT 24
Finished Aug 14 05:20:21 PM PDT 24
Peak memory 201968 kb
Host smart-10aeadf5-3561-414f-bc2d-ff4778967e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854234621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2854234621
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1271422411
Short name T551
Test name
Test status
Simulation time 4099519203 ps
CPU time 2.48 seconds
Started Aug 14 05:19:03 PM PDT 24
Finished Aug 14 05:19:06 PM PDT 24
Peak memory 201980 kb
Host smart-fa36dd12-ca27-4967-9431-7be016806407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271422411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1271422411
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1192092458
Short name T120
Test name
Test status
Simulation time 5499729123 ps
CPU time 3.76 seconds
Started Aug 14 05:19:02 PM PDT 24
Finished Aug 14 05:19:06 PM PDT 24
Peak memory 201984 kb
Host smart-bdb42ce3-118e-4235-967f-4d9219f12cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192092458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1192092458
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.4233877730
Short name T57
Test name
Test status
Simulation time 400388987347 ps
CPU time 229.01 seconds
Started Aug 14 05:18:58 PM PDT 24
Finished Aug 14 05:22:47 PM PDT 24
Peak memory 202124 kb
Host smart-59c91493-f0a7-4e9f-94dd-6ecd7f6ba301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233877730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.4233877730
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3560789581
Short name T121
Test name
Test status
Simulation time 9428585728 ps
CPU time 13.19 seconds
Started Aug 14 05:19:01 PM PDT 24
Finished Aug 14 05:19:14 PM PDT 24
Peak memory 210500 kb
Host smart-ffb22ea9-e963-49c0-a722-9bbaf6876ab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560789581 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3560789581
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.109634363
Short name T380
Test name
Test status
Simulation time 348160460 ps
CPU time 1.46 seconds
Started Aug 14 05:19:08 PM PDT 24
Finished Aug 14 05:19:10 PM PDT 24
Peak memory 201964 kb
Host smart-c6bd130d-cc7d-4764-87e1-f69f54c0501e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109634363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.109634363
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1044092828
Short name T312
Test name
Test status
Simulation time 370284998364 ps
CPU time 121.44 seconds
Started Aug 14 05:19:12 PM PDT 24
Finished Aug 14 05:21:13 PM PDT 24
Peak memory 202124 kb
Host smart-c0241659-8d73-4132-91d9-617620a7c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044092828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1044092828
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3127681784
Short name T311
Test name
Test status
Simulation time 165341699399 ps
CPU time 384.69 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:25:25 PM PDT 24
Peak memory 202148 kb
Host smart-6682f7d4-0573-46bd-87d6-46a07493a7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127681784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3127681784
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1559019682
Short name T496
Test name
Test status
Simulation time 495420261137 ps
CPU time 302.04 seconds
Started Aug 14 05:19:08 PM PDT 24
Finished Aug 14 05:24:10 PM PDT 24
Peak memory 202132 kb
Host smart-a4bb6f6c-1f03-4a22-bde6-f1a1a2dba218
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559019682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1559019682
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.775060561
Short name T706
Test name
Test status
Simulation time 165483483075 ps
CPU time 89.78 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:20:30 PM PDT 24
Peak memory 202148 kb
Host smart-280eed87-b3e9-4c8d-8eff-06c280077d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775060561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.775060561
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2516989821
Short name T548
Test name
Test status
Simulation time 497852822200 ps
CPU time 1099.61 seconds
Started Aug 14 05:19:01 PM PDT 24
Finished Aug 14 05:37:21 PM PDT 24
Peak memory 202144 kb
Host smart-6912582b-43c7-4d76-b24b-b57a5afadb4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516989821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2516989821
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2394636360
Short name T297
Test name
Test status
Simulation time 261234428976 ps
CPU time 85.4 seconds
Started Aug 14 05:19:07 PM PDT 24
Finished Aug 14 05:20:33 PM PDT 24
Peak memory 202132 kb
Host smart-64c43f78-451c-466b-a705-e376bc6afb00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394636360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2394636360
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3732904007
Short name T419
Test name
Test status
Simulation time 624565085040 ps
CPU time 361.09 seconds
Started Aug 14 05:19:09 PM PDT 24
Finished Aug 14 05:25:10 PM PDT 24
Peak memory 202132 kb
Host smart-a4ce21e7-884f-401e-836a-eb0bf3a40a11
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732904007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3732904007
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.454702295
Short name T678
Test name
Test status
Simulation time 37768510022 ps
CPU time 22.48 seconds
Started Aug 14 05:19:08 PM PDT 24
Finished Aug 14 05:19:31 PM PDT 24
Peak memory 201980 kb
Host smart-93d56ec1-108d-4e93-afe7-358655bd7382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454702295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.454702295
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2725122032
Short name T94
Test name
Test status
Simulation time 3159103505 ps
CPU time 1.84 seconds
Started Aug 14 05:19:09 PM PDT 24
Finished Aug 14 05:19:11 PM PDT 24
Peak memory 201960 kb
Host smart-124e0687-e647-4d34-bb03-e57e00bd06e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725122032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2725122032
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3826855361
Short name T392
Test name
Test status
Simulation time 5965911727 ps
CPU time 15.03 seconds
Started Aug 14 05:19:00 PM PDT 24
Finished Aug 14 05:19:15 PM PDT 24
Peak memory 201984 kb
Host smart-5be91df8-b360-480a-87a9-9474a12a2572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826855361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3826855361
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2561063114
Short name T103
Test name
Test status
Simulation time 375258630689 ps
CPU time 112.97 seconds
Started Aug 14 05:19:10 PM PDT 24
Finished Aug 14 05:21:03 PM PDT 24
Peak memory 202160 kb
Host smart-4d19946d-8269-4a78-9e39-6cfd0bf61820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561063114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2561063114
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3018171484
Short name T247
Test name
Test status
Simulation time 7135419111 ps
CPU time 5.05 seconds
Started Aug 14 05:19:10 PM PDT 24
Finished Aug 14 05:19:15 PM PDT 24
Peak memory 202228 kb
Host smart-2e5abcff-1299-4dd8-b03b-e52a7b19a8cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018171484 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3018171484
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2999994170
Short name T746
Test name
Test status
Simulation time 420931175 ps
CPU time 1.62 seconds
Started Aug 14 05:19:09 PM PDT 24
Finished Aug 14 05:19:11 PM PDT 24
Peak memory 201988 kb
Host smart-96fe7145-7d80-4617-910f-1092a2764b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999994170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2999994170
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2981332565
Short name T645
Test name
Test status
Simulation time 563990378313 ps
CPU time 1340.35 seconds
Started Aug 14 05:19:10 PM PDT 24
Finished Aug 14 05:41:30 PM PDT 24
Peak memory 202016 kb
Host smart-2a6ab3f2-215f-47c1-92d3-3e2aeae85d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981332565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2981332565
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4108629214
Short name T286
Test name
Test status
Simulation time 488639392424 ps
CPU time 1212.46 seconds
Started Aug 14 05:19:09 PM PDT 24
Finished Aug 14 05:39:21 PM PDT 24
Peak memory 202088 kb
Host smart-f6d355b7-cf34-4597-9c67-437e23fec4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108629214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4108629214
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1914751722
Short name T569
Test name
Test status
Simulation time 163976793939 ps
CPU time 195.75 seconds
Started Aug 14 05:19:10 PM PDT 24
Finished Aug 14 05:22:26 PM PDT 24
Peak memory 202052 kb
Host smart-baa626b7-193f-48b4-83a2-32b5b928f832
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914751722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1914751722
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3103949434
Short name T572
Test name
Test status
Simulation time 162863337469 ps
CPU time 88.46 seconds
Started Aug 14 05:19:09 PM PDT 24
Finished Aug 14 05:20:38 PM PDT 24
Peak memory 202132 kb
Host smart-8b435737-54a8-49b6-bc52-0f065236475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103949434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3103949434
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1074393134
Short name T549
Test name
Test status
Simulation time 166451867409 ps
CPU time 106.47 seconds
Started Aug 14 05:19:09 PM PDT 24
Finished Aug 14 05:20:56 PM PDT 24
Peak memory 202160 kb
Host smart-0de9bec0-5a67-42bd-830f-54b72b2aa4f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074393134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1074393134
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2409833542
Short name T337
Test name
Test status
Simulation time 178972638832 ps
CPU time 107.18 seconds
Started Aug 14 05:19:10 PM PDT 24
Finished Aug 14 05:20:57 PM PDT 24
Peak memory 202196 kb
Host smart-fe2c7107-5a4d-4b7b-a155-b8a67a791630
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409833542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2409833542
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2460988437
Short name T530
Test name
Test status
Simulation time 388719051742 ps
CPU time 236.16 seconds
Started Aug 14 05:19:10 PM PDT 24
Finished Aug 14 05:23:06 PM PDT 24
Peak memory 202044 kb
Host smart-c48c0a5c-c11b-4aa8-a561-b54bc9cae9f6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460988437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2460988437
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2105958366
Short name T685
Test name
Test status
Simulation time 91331425861 ps
CPU time 309.04 seconds
Started Aug 14 05:19:09 PM PDT 24
Finished Aug 14 05:24:18 PM PDT 24
Peak memory 202388 kb
Host smart-bd3de3c7-de04-4fe0-ab86-70d9b8e72da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105958366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2105958366
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3127768704
Short name T541
Test name
Test status
Simulation time 45441853991 ps
CPU time 27.6 seconds
Started Aug 14 05:19:12 PM PDT 24
Finished Aug 14 05:19:39 PM PDT 24
Peak memory 201972 kb
Host smart-9f65271c-c446-41f1-8e02-4989db15d36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127768704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3127768704
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1058653338
Short name T513
Test name
Test status
Simulation time 3200371879 ps
CPU time 4.5 seconds
Started Aug 14 05:19:08 PM PDT 24
Finished Aug 14 05:19:12 PM PDT 24
Peak memory 201940 kb
Host smart-dc378caf-0646-445c-b40b-f39005a8cdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058653338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1058653338
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3846366585
Short name T745
Test name
Test status
Simulation time 5764974940 ps
CPU time 3.97 seconds
Started Aug 14 05:19:08 PM PDT 24
Finished Aug 14 05:19:12 PM PDT 24
Peak memory 202028 kb
Host smart-51c1856a-acaf-4c52-959e-3f2c65e46cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846366585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3846366585
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3707831400
Short name T260
Test name
Test status
Simulation time 370343902184 ps
CPU time 867.52 seconds
Started Aug 14 05:19:10 PM PDT 24
Finished Aug 14 05:33:37 PM PDT 24
Peak memory 202144 kb
Host smart-bdcf6967-3fd1-4a64-9b7b-17be680acd8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707831400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3707831400
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1412921273
Short name T111
Test name
Test status
Simulation time 5123136664 ps
CPU time 13.81 seconds
Started Aug 14 05:19:09 PM PDT 24
Finished Aug 14 05:19:23 PM PDT 24
Peak memory 210712 kb
Host smart-7c389f51-593c-4890-9044-3f9054d75bf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412921273 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1412921273
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.166295883
Short name T623
Test name
Test status
Simulation time 474227743 ps
CPU time 1.67 seconds
Started Aug 14 05:19:19 PM PDT 24
Finished Aug 14 05:19:21 PM PDT 24
Peak memory 201964 kb
Host smart-67f149f4-8f8d-4ef0-b560-9c230024645b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166295883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.166295883
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.4086445947
Short name T122
Test name
Test status
Simulation time 373406548436 ps
CPU time 113.94 seconds
Started Aug 14 05:19:20 PM PDT 24
Finished Aug 14 05:21:14 PM PDT 24
Peak memory 202160 kb
Host smart-87734d83-0d79-4e28-b26f-8d5f511fd38b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086445947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.4086445947
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2060445433
Short name T331
Test name
Test status
Simulation time 161429430878 ps
CPU time 93.99 seconds
Started Aug 14 05:19:18 PM PDT 24
Finished Aug 14 05:20:52 PM PDT 24
Peak memory 202196 kb
Host smart-e413e1a9-bfd3-4cd6-8732-9d65e609df9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060445433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2060445433
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3878643775
Short name T167
Test name
Test status
Simulation time 159776530450 ps
CPU time 101.1 seconds
Started Aug 14 05:19:18 PM PDT 24
Finished Aug 14 05:20:59 PM PDT 24
Peak memory 202160 kb
Host smart-762ed0b1-4451-45d2-9651-0770ae5c160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878643775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3878643775
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.4208524682
Short name T10
Test name
Test status
Simulation time 487883495979 ps
CPU time 1009.15 seconds
Started Aug 14 05:19:18 PM PDT 24
Finished Aug 14 05:36:08 PM PDT 24
Peak memory 202152 kb
Host smart-4e6d29cf-11b2-490a-a31a-45c4640d0630
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208524682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.4208524682
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2541706820
Short name T603
Test name
Test status
Simulation time 323317463105 ps
CPU time 348.18 seconds
Started Aug 14 05:19:17 PM PDT 24
Finished Aug 14 05:25:05 PM PDT 24
Peak memory 202120 kb
Host smart-6dda8034-7abf-431e-ad6c-0e24fe1f73eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541706820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2541706820
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2518953117
Short name T9
Test name
Test status
Simulation time 83729147092 ps
CPU time 464.28 seconds
Started Aug 14 05:19:18 PM PDT 24
Finished Aug 14 05:27:02 PM PDT 24
Peak memory 202388 kb
Host smart-326634e6-5994-4815-bdc3-f574280ce9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518953117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2518953117
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1987230638
Short name T102
Test name
Test status
Simulation time 29534583039 ps
CPU time 17.22 seconds
Started Aug 14 05:19:17 PM PDT 24
Finished Aug 14 05:19:34 PM PDT 24
Peak memory 201956 kb
Host smart-918649b9-157c-4f88-9b1e-a078a546be94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987230638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1987230638
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2451507934
Short name T398
Test name
Test status
Simulation time 3200648476 ps
CPU time 2.5 seconds
Started Aug 14 05:19:17 PM PDT 24
Finished Aug 14 05:19:20 PM PDT 24
Peak memory 201976 kb
Host smart-5688f2b1-f82a-4747-8b4e-208e90c716f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451507934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2451507934
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.671901159
Short name T556
Test name
Test status
Simulation time 5768075027 ps
CPU time 14.64 seconds
Started Aug 14 05:19:08 PM PDT 24
Finished Aug 14 05:19:23 PM PDT 24
Peak memory 201968 kb
Host smart-60da277b-72e8-491b-a4df-ec1660abbb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671901159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.671901159
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1899095345
Short name T492
Test name
Test status
Simulation time 2277050088 ps
CPU time 6.02 seconds
Started Aug 14 05:19:18 PM PDT 24
Finished Aug 14 05:19:24 PM PDT 24
Peak memory 202116 kb
Host smart-1e63b807-23f7-494d-9642-fc2cec1d7f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899095345 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1899095345
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1698426725
Short name T435
Test name
Test status
Simulation time 519681152 ps
CPU time 0.95 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:19:27 PM PDT 24
Peak memory 201972 kb
Host smart-000a4b96-5a8b-4969-a747-9afea6c29dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698426725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1698426725
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3552794425
Short name T183
Test name
Test status
Simulation time 510532177272 ps
CPU time 102.21 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:21:08 PM PDT 24
Peak memory 202044 kb
Host smart-80c77961-4352-42b8-b515-e056139db545
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552794425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3552794425
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.496166472
Short name T664
Test name
Test status
Simulation time 168584261722 ps
CPU time 80.41 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:20:46 PM PDT 24
Peak memory 202144 kb
Host smart-a21f1330-7627-485d-9449-dd6323d09f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496166472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.496166472
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3134134141
Short name T349
Test name
Test status
Simulation time 161766073529 ps
CPU time 179.73 seconds
Started Aug 14 05:19:18 PM PDT 24
Finished Aug 14 05:22:18 PM PDT 24
Peak memory 202132 kb
Host smart-50eb7994-97b8-4acf-a071-41952765a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134134141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3134134141
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3545701665
Short name T780
Test name
Test status
Simulation time 487798689721 ps
CPU time 322.53 seconds
Started Aug 14 05:19:17 PM PDT 24
Finished Aug 14 05:24:40 PM PDT 24
Peak memory 202120 kb
Host smart-909f94df-b1bb-431c-9322-f2256fe50959
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545701665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3545701665
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1336234134
Short name T185
Test name
Test status
Simulation time 485510840864 ps
CPU time 285.27 seconds
Started Aug 14 05:19:19 PM PDT 24
Finished Aug 14 05:24:04 PM PDT 24
Peak memory 202084 kb
Host smart-3c02ad3c-aa1e-4c46-a350-00974b1b283c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336234134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1336234134
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.494325371
Short name T598
Test name
Test status
Simulation time 160025031509 ps
CPU time 355.2 seconds
Started Aug 14 05:19:18 PM PDT 24
Finished Aug 14 05:25:13 PM PDT 24
Peak memory 202104 kb
Host smart-612c2ccb-d92c-4cf0-ba66-a9044ae188bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=494325371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.494325371
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2841689490
Short name T307
Test name
Test status
Simulation time 393519307321 ps
CPU time 922.37 seconds
Started Aug 14 05:19:15 PM PDT 24
Finished Aug 14 05:34:38 PM PDT 24
Peak memory 202172 kb
Host smart-a22234d3-56e1-443a-8a95-06589b59e860
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841689490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2841689490
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2350689475
Short name T32
Test name
Test status
Simulation time 197703350318 ps
CPU time 118.64 seconds
Started Aug 14 05:19:25 PM PDT 24
Finished Aug 14 05:21:24 PM PDT 24
Peak memory 202132 kb
Host smart-fe6040cd-9ee1-4d28-a4c8-7add66f412d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350689475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2350689475
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3008265325
Short name T704
Test name
Test status
Simulation time 84190540206 ps
CPU time 313.78 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:24:39 PM PDT 24
Peak memory 202440 kb
Host smart-74b034e1-6c84-4068-8dbf-808c8963cb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008265325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3008265325
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2574082948
Short name T529
Test name
Test status
Simulation time 24017343593 ps
CPU time 15.71 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:19:41 PM PDT 24
Peak memory 201936 kb
Host smart-bbe5c270-14df-43d2-a0ca-9edcb77dfa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574082948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2574082948
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4228014544
Short name T724
Test name
Test status
Simulation time 3660026169 ps
CPU time 3.14 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:19:29 PM PDT 24
Peak memory 201924 kb
Host smart-e2a4fd5b-6e53-4588-a1c0-bac1d146e274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228014544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4228014544
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3426319314
Short name T557
Test name
Test status
Simulation time 5776174991 ps
CPU time 7.6 seconds
Started Aug 14 05:19:16 PM PDT 24
Finished Aug 14 05:19:24 PM PDT 24
Peak memory 201856 kb
Host smart-5e4d177e-2ffe-494f-bfeb-df70978b4942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426319314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3426319314
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.564145373
Short name T45
Test name
Test status
Simulation time 82570077709 ps
CPU time 6.88 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:19:33 PM PDT 24
Peak memory 202260 kb
Host smart-7decc398-6ba4-451b-90d9-d185774c83d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564145373 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.564145373
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1984530195
Short name T423
Test name
Test status
Simulation time 495554148 ps
CPU time 0.98 seconds
Started Aug 14 05:19:35 PM PDT 24
Finished Aug 14 05:19:36 PM PDT 24
Peak memory 202012 kb
Host smart-76561230-0aa5-42be-b886-09dd4b4dc663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984530195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1984530195
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.71341431
Short name T532
Test name
Test status
Simulation time 159935755758 ps
CPU time 355.07 seconds
Started Aug 14 05:19:35 PM PDT 24
Finished Aug 14 05:25:30 PM PDT 24
Peak memory 202120 kb
Host smart-6d35a9ae-3308-45b0-89c3-f997121dc542
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=71341431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt
_fixed.71341431
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2136736992
Short name T559
Test name
Test status
Simulation time 493031425775 ps
CPU time 599.29 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:29:25 PM PDT 24
Peak memory 202140 kb
Host smart-4559cddd-a621-4088-936b-875a8ece8be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136736992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2136736992
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.678578784
Short name T698
Test name
Test status
Simulation time 159249183464 ps
CPU time 354.12 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:25:20 PM PDT 24
Peak memory 202116 kb
Host smart-4b905927-1d3e-48c6-91cb-51c2efb94097
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=678578784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.678578784
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.713315547
Short name T326
Test name
Test status
Simulation time 569200502165 ps
CPU time 1198.88 seconds
Started Aug 14 05:19:35 PM PDT 24
Finished Aug 14 05:39:34 PM PDT 24
Peak memory 202128 kb
Host smart-9bd6e9eb-68d5-48f0-b478-03f3d563d6bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713315547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.713315547
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.60585952
Short name T649
Test name
Test status
Simulation time 593849246638 ps
CPU time 1280.01 seconds
Started Aug 14 05:19:33 PM PDT 24
Finished Aug 14 05:40:53 PM PDT 24
Peak memory 202180 kb
Host smart-0a4d5e5a-9bb1-4da0-a910-ca91b0307b63
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60585952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.a
dc_ctrl_filters_wakeup_fixed.60585952
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.353218972
Short name T229
Test name
Test status
Simulation time 123980891321 ps
CPU time 688.06 seconds
Started Aug 14 05:19:34 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 202432 kb
Host smart-e0d942ef-8e01-4984-8af8-22f95f3be595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353218972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.353218972
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3590440453
Short name T459
Test name
Test status
Simulation time 40965708786 ps
CPU time 19.53 seconds
Started Aug 14 05:19:36 PM PDT 24
Finished Aug 14 05:19:56 PM PDT 24
Peak memory 201948 kb
Host smart-ef1c7caf-09f6-413c-b790-74d8838d8ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590440453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3590440453
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2922510126
Short name T779
Test name
Test status
Simulation time 3901433768 ps
CPU time 2.78 seconds
Started Aug 14 05:19:35 PM PDT 24
Finished Aug 14 05:19:38 PM PDT 24
Peak memory 201864 kb
Host smart-5b47b355-702e-4838-8a43-d2c6a5341cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922510126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2922510126
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.442708796
Short name T475
Test name
Test status
Simulation time 5755271572 ps
CPU time 7.47 seconds
Started Aug 14 05:19:26 PM PDT 24
Finished Aug 14 05:19:33 PM PDT 24
Peak memory 201968 kb
Host smart-7b584e1a-9c14-42fb-b6a5-73c5f91766e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442708796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.442708796
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4263158006
Short name T723
Test name
Test status
Simulation time 645328210087 ps
CPU time 1085.36 seconds
Started Aug 14 05:19:36 PM PDT 24
Finished Aug 14 05:37:42 PM PDT 24
Peak memory 202376 kb
Host smart-7440c59a-d4c8-4b11-a464-17f3c64e9fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263158006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4263158006
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3854295255
Short name T52
Test name
Test status
Simulation time 16156953232 ps
CPU time 9.82 seconds
Started Aug 14 05:19:33 PM PDT 24
Finished Aug 14 05:19:43 PM PDT 24
Peak memory 213580 kb
Host smart-0f20f30e-2591-47d9-bf84-ae73dc381043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854295255 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3854295255
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.427577542
Short name T424
Test name
Test status
Simulation time 440518254 ps
CPU time 1.13 seconds
Started Aug 14 05:19:43 PM PDT 24
Finished Aug 14 05:19:44 PM PDT 24
Peak memory 201984 kb
Host smart-399fd40e-c32b-48c0-afff-60679e2a62cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427577542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.427577542
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.222928845
Short name T317
Test name
Test status
Simulation time 495101316472 ps
CPU time 803.82 seconds
Started Aug 14 05:19:43 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 202124 kb
Host smart-684c0c4d-3ed4-4900-94a9-cbd850ab044d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222928845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.222928845
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1831776288
Short name T363
Test name
Test status
Simulation time 517654785322 ps
CPU time 298.38 seconds
Started Aug 14 05:19:44 PM PDT 24
Finished Aug 14 05:24:43 PM PDT 24
Peak memory 202148 kb
Host smart-dbd3cda2-a27b-4aa8-a890-ef9039728e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831776288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1831776288
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1654713952
Short name T250
Test name
Test status
Simulation time 492463385592 ps
CPU time 592.87 seconds
Started Aug 14 05:19:34 PM PDT 24
Finished Aug 14 05:29:27 PM PDT 24
Peak memory 202112 kb
Host smart-87c90ad7-ae1d-4807-b9f5-71b4fe3b8260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654713952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1654713952
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2917114007
Short name T3
Test name
Test status
Simulation time 490780219382 ps
CPU time 238.39 seconds
Started Aug 14 05:19:42 PM PDT 24
Finished Aug 14 05:23:40 PM PDT 24
Peak memory 202104 kb
Host smart-bc32125a-6284-418e-a90b-6516512ac38a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917114007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2917114007
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3213181561
Short name T594
Test name
Test status
Simulation time 480906528617 ps
CPU time 198.39 seconds
Started Aug 14 05:19:37 PM PDT 24
Finished Aug 14 05:22:55 PM PDT 24
Peak memory 202172 kb
Host smart-c7be2cd9-d47a-4b62-aa16-8c5b7cd31ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213181561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3213181561
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3405110533
Short name T560
Test name
Test status
Simulation time 497479030184 ps
CPU time 538.4 seconds
Started Aug 14 05:19:33 PM PDT 24
Finished Aug 14 05:28:32 PM PDT 24
Peak memory 202144 kb
Host smart-40992107-cdfc-4e77-81e0-adba154ef7b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405110533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3405110533
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2672761046
Short name T607
Test name
Test status
Simulation time 610994559175 ps
CPU time 250.06 seconds
Started Aug 14 05:19:43 PM PDT 24
Finished Aug 14 05:23:53 PM PDT 24
Peak memory 202276 kb
Host smart-b353b639-a55b-40cf-b74f-c81d90bd2290
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672761046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2672761046
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2803605082
Short name T793
Test name
Test status
Simulation time 66606542915 ps
CPU time 239.06 seconds
Started Aug 14 05:19:44 PM PDT 24
Finished Aug 14 05:23:43 PM PDT 24
Peak memory 202452 kb
Host smart-c1465e76-ff15-4183-b801-edb1957e3c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803605082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2803605082
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2058222883
Short name T574
Test name
Test status
Simulation time 26546731886 ps
CPU time 29.89 seconds
Started Aug 14 05:19:42 PM PDT 24
Finished Aug 14 05:20:12 PM PDT 24
Peak memory 201920 kb
Host smart-92e6d925-352a-4566-9226-9a10e14f21f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058222883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2058222883
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.447936841
Short name T397
Test name
Test status
Simulation time 3733320721 ps
CPU time 9.17 seconds
Started Aug 14 05:19:42 PM PDT 24
Finished Aug 14 05:19:51 PM PDT 24
Peak memory 201968 kb
Host smart-bc8038e3-5f56-4572-ae0f-f904fca9d2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447936841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.447936841
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1997160087
Short name T502
Test name
Test status
Simulation time 5716403406 ps
CPU time 13.45 seconds
Started Aug 14 05:19:36 PM PDT 24
Finished Aug 14 05:19:50 PM PDT 24
Peak memory 201972 kb
Host smart-6b1d518d-e50a-415c-a8df-c9788ead424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997160087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1997160087
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3444873975
Short name T563
Test name
Test status
Simulation time 455611854063 ps
CPU time 533.67 seconds
Started Aug 14 05:19:44 PM PDT 24
Finished Aug 14 05:28:38 PM PDT 24
Peak memory 210600 kb
Host smart-f045db2b-bd39-4836-a664-a919cf0e0030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444873975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3444873975
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1399552677
Short name T53
Test name
Test status
Simulation time 22305479377 ps
CPU time 12.83 seconds
Started Aug 14 05:19:43 PM PDT 24
Finished Aug 14 05:19:56 PM PDT 24
Peak memory 210516 kb
Host smart-c5338a7a-6c92-4243-b3b2-f2e07a73d518
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399552677 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1399552677
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1376098509
Short name T614
Test name
Test status
Simulation time 289090008 ps
CPU time 1.25 seconds
Started Aug 14 05:17:25 PM PDT 24
Finished Aug 14 05:17:27 PM PDT 24
Peak memory 202000 kb
Host smart-ced5d539-8669-4347-b968-d88c0da240af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376098509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1376098509
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1107256771
Short name T222
Test name
Test status
Simulation time 184597073798 ps
CPU time 77.47 seconds
Started Aug 14 05:17:24 PM PDT 24
Finished Aug 14 05:18:42 PM PDT 24
Peak memory 202160 kb
Host smart-82cbe822-4bdb-421f-9bab-6c2f3f477371
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107256771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1107256771
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.255725242
Short name T359
Test name
Test status
Simulation time 327254552977 ps
CPU time 343.09 seconds
Started Aug 14 05:17:10 PM PDT 24
Finished Aug 14 05:22:53 PM PDT 24
Peak memory 202112 kb
Host smart-2d808b0f-e34c-488f-8c88-7206b6bf0404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255725242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.255725242
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.207012811
Short name T499
Test name
Test status
Simulation time 168038609456 ps
CPU time 191.82 seconds
Started Aug 14 05:17:20 PM PDT 24
Finished Aug 14 05:20:32 PM PDT 24
Peak memory 202116 kb
Host smart-a8540e08-3850-4cdb-aae8-d8f77836a2d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=207012811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.207012811
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.535967172
Short name T579
Test name
Test status
Simulation time 490220327680 ps
CPU time 122.39 seconds
Started Aug 14 05:17:08 PM PDT 24
Finished Aug 14 05:19:11 PM PDT 24
Peak memory 202144 kb
Host smart-541638b2-a211-462a-9a60-89057d9541ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535967172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.535967172
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3031709793
Short name T580
Test name
Test status
Simulation time 164743274743 ps
CPU time 111.13 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:18:58 PM PDT 24
Peak memory 202280 kb
Host smart-9d227bf5-3dac-4c69-bfdb-715fc5c9d613
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031709793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3031709793
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2574764367
Short name T348
Test name
Test status
Simulation time 532477681298 ps
CPU time 1219.26 seconds
Started Aug 14 05:17:24 PM PDT 24
Finished Aug 14 05:37:43 PM PDT 24
Peak memory 202128 kb
Host smart-f3127b89-38eb-46c1-897d-7fa8d3d79a92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574764367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2574764367
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3425399522
Short name T547
Test name
Test status
Simulation time 405597669412 ps
CPU time 637.81 seconds
Started Aug 14 05:17:24 PM PDT 24
Finished Aug 14 05:28:02 PM PDT 24
Peak memory 202040 kb
Host smart-f6c3a827-03a1-4210-aed4-81dd07703893
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425399522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3425399522
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1850521546
Short name T232
Test name
Test status
Simulation time 91257715887 ps
CPU time 456.52 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:25:00 PM PDT 24
Peak memory 202424 kb
Host smart-c454aa5d-26e2-497a-b70a-7d58f20c08ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850521546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1850521546
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2618170083
Short name T468
Test name
Test status
Simulation time 24242965473 ps
CPU time 55.64 seconds
Started Aug 14 05:17:22 PM PDT 24
Finished Aug 14 05:18:18 PM PDT 24
Peak memory 201948 kb
Host smart-aa5c3c44-7801-4fc1-8391-c34e0f675ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618170083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2618170083
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1438197307
Short name T455
Test name
Test status
Simulation time 2922424514 ps
CPU time 6.91 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:17:30 PM PDT 24
Peak memory 201980 kb
Host smart-267c81d8-8339-4e4a-b2a3-ad4f1d77c519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438197307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1438197307
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1875904572
Short name T91
Test name
Test status
Simulation time 3974400792 ps
CPU time 9.51 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:17:33 PM PDT 24
Peak memory 217460 kb
Host smart-40ce6538-1baa-46f2-8541-ca038ca10c67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875904572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1875904572
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2331970545
Short name T456
Test name
Test status
Simulation time 6166407830 ps
CPU time 16.06 seconds
Started Aug 14 05:17:07 PM PDT 24
Finished Aug 14 05:17:23 PM PDT 24
Peak memory 201944 kb
Host smart-f8628115-cd97-4aff-a871-accae1dd710a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331970545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2331970545
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.815706287
Short name T790
Test name
Test status
Simulation time 115451157664 ps
CPU time 586.53 seconds
Started Aug 14 05:17:22 PM PDT 24
Finished Aug 14 05:27:09 PM PDT 24
Peak memory 202388 kb
Host smart-2493b3f5-6d44-4aa3-92a5-87d4ff34ecce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815706287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.815706287
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1978570092
Short name T446
Test name
Test status
Simulation time 400489443 ps
CPU time 0.83 seconds
Started Aug 14 05:19:52 PM PDT 24
Finished Aug 14 05:19:53 PM PDT 24
Peak memory 201996 kb
Host smart-8bec6edb-b776-4b9f-b39e-220fd650f514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978570092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1978570092
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3195287315
Short name T293
Test name
Test status
Simulation time 331404138753 ps
CPU time 49.12 seconds
Started Aug 14 05:19:53 PM PDT 24
Finished Aug 14 05:20:42 PM PDT 24
Peak memory 202220 kb
Host smart-a0ab5f33-2385-46a2-b286-8e11bb0b1a73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195287315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3195287315
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1275720769
Short name T742
Test name
Test status
Simulation time 182802526176 ps
CPU time 414.49 seconds
Started Aug 14 05:19:54 PM PDT 24
Finished Aug 14 05:26:49 PM PDT 24
Peak memory 202124 kb
Host smart-345c9748-9a01-4b2c-9b92-9764bd38cc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275720769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1275720769
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1843876582
Short name T500
Test name
Test status
Simulation time 158569355547 ps
CPU time 360.92 seconds
Started Aug 14 05:19:43 PM PDT 24
Finished Aug 14 05:25:44 PM PDT 24
Peak memory 202124 kb
Host smart-b4d340db-ec6a-4419-b47b-a4f804ea9979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843876582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1843876582
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.246622463
Short name T197
Test name
Test status
Simulation time 163660659546 ps
CPU time 58.13 seconds
Started Aug 14 05:19:43 PM PDT 24
Finished Aug 14 05:20:41 PM PDT 24
Peak memory 202140 kb
Host smart-10af467c-0d15-4aa3-96ca-0ca6efde8c9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=246622463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.246622463
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3101450516
Short name T24
Test name
Test status
Simulation time 330969691063 ps
CPU time 60.28 seconds
Started Aug 14 05:19:43 PM PDT 24
Finished Aug 14 05:20:43 PM PDT 24
Peak memory 202164 kb
Host smart-5f76b737-cc7e-4356-a6ae-0014b0c62082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101450516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3101450516
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.211229620
Short name T660
Test name
Test status
Simulation time 331620361212 ps
CPU time 397.03 seconds
Started Aug 14 05:19:44 PM PDT 24
Finished Aug 14 05:26:22 PM PDT 24
Peak memory 202132 kb
Host smart-c3e76743-d7eb-427e-ab9f-fe1a6aa9dd78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=211229620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.211229620
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1706541223
Short name T26
Test name
Test status
Simulation time 190580267441 ps
CPU time 218.2 seconds
Started Aug 14 05:19:43 PM PDT 24
Finished Aug 14 05:23:22 PM PDT 24
Peak memory 202124 kb
Host smart-8ebedf13-358d-4202-af18-65f48228fe5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706541223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1706541223
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2608009526
Short name T587
Test name
Test status
Simulation time 387274472912 ps
CPU time 151.13 seconds
Started Aug 14 05:19:44 PM PDT 24
Finished Aug 14 05:22:16 PM PDT 24
Peak memory 202124 kb
Host smart-cf57d729-005a-4fc4-841b-2b65abf8fd24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608009526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2608009526
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.194131157
Short name T62
Test name
Test status
Simulation time 82133667703 ps
CPU time 388.3 seconds
Started Aug 14 05:19:52 PM PDT 24
Finished Aug 14 05:26:21 PM PDT 24
Peak memory 202412 kb
Host smart-9a9283fa-5b85-4714-ba02-4cc80590964a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194131157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.194131157
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3339945081
Short name T505
Test name
Test status
Simulation time 46984927551 ps
CPU time 110.11 seconds
Started Aug 14 05:19:52 PM PDT 24
Finished Aug 14 05:21:42 PM PDT 24
Peak memory 201920 kb
Host smart-326de831-0655-481e-9542-c518a9e5dca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339945081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3339945081
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1341979235
Short name T771
Test name
Test status
Simulation time 2973254281 ps
CPU time 7.78 seconds
Started Aug 14 05:19:51 PM PDT 24
Finished Aug 14 05:19:59 PM PDT 24
Peak memory 201980 kb
Host smart-957c0787-501c-45f6-8756-4de44a49a066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341979235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1341979235
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1998722483
Short name T526
Test name
Test status
Simulation time 5799254133 ps
CPU time 13.21 seconds
Started Aug 14 05:19:44 PM PDT 24
Finished Aug 14 05:19:57 PM PDT 24
Peak memory 201980 kb
Host smart-e74bbe37-5abf-4b1c-acd0-a3d8a0c1c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998722483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1998722483
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1488452342
Short name T681
Test name
Test status
Simulation time 286083246636 ps
CPU time 539.47 seconds
Started Aug 14 05:19:53 PM PDT 24
Finished Aug 14 05:28:53 PM PDT 24
Peak memory 212984 kb
Host smart-02faf3d7-3687-49f4-a88b-42e43d27ef7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488452342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1488452342
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2045711407
Short name T773
Test name
Test status
Simulation time 3490156909 ps
CPU time 6.43 seconds
Started Aug 14 05:19:52 PM PDT 24
Finished Aug 14 05:19:58 PM PDT 24
Peak memory 202028 kb
Host smart-8480221d-1b4c-42f5-bbc9-8fd4ef0578ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045711407 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2045711407
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3205265373
Short name T620
Test name
Test status
Simulation time 421697884 ps
CPU time 1.63 seconds
Started Aug 14 05:20:00 PM PDT 24
Finished Aug 14 05:20:02 PM PDT 24
Peak memory 202008 kb
Host smart-6e75406b-7488-43e8-a19a-a918725413e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205265373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3205265373
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2869294415
Short name T555
Test name
Test status
Simulation time 519272938004 ps
CPU time 412.03 seconds
Started Aug 14 05:19:52 PM PDT 24
Finished Aug 14 05:26:45 PM PDT 24
Peak memory 202132 kb
Host smart-3fd108a3-1db2-443c-8956-1c3970dd856c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869294415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2869294415
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.4067673853
Short name T313
Test name
Test status
Simulation time 509152874560 ps
CPU time 1172.59 seconds
Started Aug 14 05:19:55 PM PDT 24
Finished Aug 14 05:39:28 PM PDT 24
Peak memory 202112 kb
Host smart-8605615e-adb4-49fd-8ca1-496f577a51b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067673853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.4067673853
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4130326886
Short name T564
Test name
Test status
Simulation time 336054878525 ps
CPU time 202.65 seconds
Started Aug 14 05:19:53 PM PDT 24
Finished Aug 14 05:23:16 PM PDT 24
Peak memory 202160 kb
Host smart-ec829556-5cac-4df8-b582-dd2fc2efe76f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130326886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4130326886
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.636594949
Short name T196
Test name
Test status
Simulation time 165376948659 ps
CPU time 188.28 seconds
Started Aug 14 05:19:53 PM PDT 24
Finished Aug 14 05:23:01 PM PDT 24
Peak memory 202160 kb
Host smart-04912413-c2bc-49af-8a7b-6cd4ba6b8b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636594949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.636594949
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.868635819
Short name T395
Test name
Test status
Simulation time 329120459892 ps
CPU time 687.9 seconds
Started Aug 14 05:19:53 PM PDT 24
Finished Aug 14 05:31:21 PM PDT 24
Peak memory 202112 kb
Host smart-cb395695-ec50-46bc-a070-22192d303d60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=868635819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.868635819
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4242810612
Short name T347
Test name
Test status
Simulation time 546415568852 ps
CPU time 288.41 seconds
Started Aug 14 05:19:53 PM PDT 24
Finished Aug 14 05:24:42 PM PDT 24
Peak memory 202128 kb
Host smart-921ffde2-2b56-443d-8086-b2e9ac6164a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242810612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4242810612
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2581365456
Short name T400
Test name
Test status
Simulation time 404651205352 ps
CPU time 919.34 seconds
Started Aug 14 05:19:52 PM PDT 24
Finished Aug 14 05:35:11 PM PDT 24
Peak memory 202120 kb
Host smart-012fb14d-15ec-4f99-a604-fef2f57b71e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581365456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2581365456
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.4073470630
Short name T730
Test name
Test status
Simulation time 74749081705 ps
CPU time 275.26 seconds
Started Aug 14 05:20:02 PM PDT 24
Finished Aug 14 05:24:37 PM PDT 24
Peak memory 202416 kb
Host smart-07565e36-677c-49be-9679-b9ae0983e41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073470630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.4073470630
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1038125290
Short name T93
Test name
Test status
Simulation time 31328449996 ps
CPU time 30.03 seconds
Started Aug 14 05:20:02 PM PDT 24
Finished Aug 14 05:20:32 PM PDT 24
Peak memory 201956 kb
Host smart-8719f70a-85a5-4e88-8678-b45f8e910541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038125290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1038125290
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1543704286
Short name T688
Test name
Test status
Simulation time 3210869844 ps
CPU time 8.45 seconds
Started Aug 14 05:20:00 PM PDT 24
Finished Aug 14 05:20:09 PM PDT 24
Peak memory 201964 kb
Host smart-37451998-3e29-442f-b9ec-b05b4511605d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543704286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1543704286
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1645681111
Short name T568
Test name
Test status
Simulation time 5730251386 ps
CPU time 3.7 seconds
Started Aug 14 05:19:52 PM PDT 24
Finished Aug 14 05:19:56 PM PDT 24
Peak memory 201972 kb
Host smart-f96a1ab9-37d3-46c0-a1a0-6ca2f114449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645681111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1645681111
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.4196769255
Short name T231
Test name
Test status
Simulation time 389498901023 ps
CPU time 1200.39 seconds
Started Aug 14 05:20:01 PM PDT 24
Finished Aug 14 05:40:01 PM PDT 24
Peak memory 202416 kb
Host smart-ca371b1a-deee-4950-afb0-d411d9642552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196769255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.4196769255
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1215407781
Short name T16
Test name
Test status
Simulation time 161551369207 ps
CPU time 47.1 seconds
Started Aug 14 05:20:00 PM PDT 24
Finished Aug 14 05:20:47 PM PDT 24
Peak memory 202264 kb
Host smart-376dcb0f-c1b2-4c6e-a55c-5ce7dacf4a7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215407781 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1215407781
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.70109201
Short name T83
Test name
Test status
Simulation time 331540765 ps
CPU time 0.8 seconds
Started Aug 14 05:20:00 PM PDT 24
Finished Aug 14 05:20:01 PM PDT 24
Peak memory 201980 kb
Host smart-74d0faad-57ef-4c94-9bcf-d36ab97d493e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70109201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.70109201
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2741438596
Short name T290
Test name
Test status
Simulation time 167968990837 ps
CPU time 52.67 seconds
Started Aug 14 05:20:04 PM PDT 24
Finished Aug 14 05:20:57 PM PDT 24
Peak memory 202160 kb
Host smart-2be31e2b-3f81-4c67-a50c-de993be109e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741438596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2741438596
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1541508771
Short name T458
Test name
Test status
Simulation time 164865955842 ps
CPU time 407.51 seconds
Started Aug 14 05:20:00 PM PDT 24
Finished Aug 14 05:26:48 PM PDT 24
Peak memory 202156 kb
Host smart-29e2014d-6a8f-441f-9b76-1cfeac571226
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541508771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1541508771
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3616844473
Short name T288
Test name
Test status
Simulation time 487299685764 ps
CPU time 287.73 seconds
Started Aug 14 05:20:01 PM PDT 24
Finished Aug 14 05:24:49 PM PDT 24
Peak memory 202232 kb
Host smart-ae28b6be-6a94-4f67-bef1-b7295e75584b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616844473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3616844473
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2394039362
Short name T729
Test name
Test status
Simulation time 329997794871 ps
CPU time 387.52 seconds
Started Aug 14 05:20:01 PM PDT 24
Finished Aug 14 05:26:28 PM PDT 24
Peak memory 202148 kb
Host smart-cb28a46d-bfd7-4973-ac6d-4be26da72e48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394039362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2394039362
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.109961941
Short name T613
Test name
Test status
Simulation time 549477802549 ps
CPU time 350.71 seconds
Started Aug 14 05:20:02 PM PDT 24
Finished Aug 14 05:25:53 PM PDT 24
Peak memory 202172 kb
Host smart-43f112be-9640-49b5-8a49-039456f99511
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109961941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.109961941
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4211903502
Short name T515
Test name
Test status
Simulation time 596731250347 ps
CPU time 1382.46 seconds
Started Aug 14 05:20:02 PM PDT 24
Finished Aug 14 05:43:05 PM PDT 24
Peak memory 202112 kb
Host smart-224aa173-4679-42bd-9210-8287c73fed3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211903502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4211903502
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2580754194
Short name T373
Test name
Test status
Simulation time 73869030901 ps
CPU time 229.49 seconds
Started Aug 14 05:20:01 PM PDT 24
Finished Aug 14 05:23:51 PM PDT 24
Peak memory 202404 kb
Host smart-63ee3681-ab0c-458f-9d01-d9606d540883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580754194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2580754194
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.733832710
Short name T192
Test name
Test status
Simulation time 33318155175 ps
CPU time 16.95 seconds
Started Aug 14 05:20:01 PM PDT 24
Finished Aug 14 05:20:18 PM PDT 24
Peak memory 201940 kb
Host smart-9ee951c2-e85f-446a-8f94-4832ae847923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733832710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.733832710
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3518892197
Short name T533
Test name
Test status
Simulation time 4687925668 ps
CPU time 12.38 seconds
Started Aug 14 05:19:59 PM PDT 24
Finished Aug 14 05:20:12 PM PDT 24
Peak memory 201860 kb
Host smart-d9713881-f63c-4562-a0a5-4ac491f43adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518892197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3518892197
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.858491970
Short name T601
Test name
Test status
Simulation time 5807933950 ps
CPU time 3.28 seconds
Started Aug 14 05:20:00 PM PDT 24
Finished Aug 14 05:20:04 PM PDT 24
Peak memory 201960 kb
Host smart-f9b3428e-639b-41de-ac04-ca3859e0d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858491970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.858491970
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.753163225
Short name T686
Test name
Test status
Simulation time 170217631505 ps
CPU time 108.54 seconds
Started Aug 14 05:20:03 PM PDT 24
Finished Aug 14 05:21:52 PM PDT 24
Peak memory 202144 kb
Host smart-0f98de5a-6d1b-464f-91e7-1c5ed842cc9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753163225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
753163225
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1864123659
Short name T291
Test name
Test status
Simulation time 20286855878 ps
CPU time 15.81 seconds
Started Aug 14 05:20:02 PM PDT 24
Finished Aug 14 05:20:18 PM PDT 24
Peak memory 210472 kb
Host smart-1e52585b-3a9e-4ee7-835c-627022fdb379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864123659 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1864123659
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1253885023
Short name T593
Test name
Test status
Simulation time 310282719 ps
CPU time 1.36 seconds
Started Aug 14 05:20:08 PM PDT 24
Finished Aug 14 05:20:09 PM PDT 24
Peak memory 201984 kb
Host smart-1971bd67-c280-4fe9-a1f3-3fc3060c0300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253885023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1253885023
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3016815514
Short name T273
Test name
Test status
Simulation time 163923136694 ps
CPU time 91.89 seconds
Started Aug 14 05:20:07 PM PDT 24
Finished Aug 14 05:21:39 PM PDT 24
Peak memory 202180 kb
Host smart-ecac1b51-25a9-4d56-92cd-6f0528791884
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016815514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3016815514
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1519815420
Short name T256
Test name
Test status
Simulation time 331451021974 ps
CPU time 183.61 seconds
Started Aug 14 05:20:12 PM PDT 24
Finished Aug 14 05:23:15 PM PDT 24
Peak memory 202092 kb
Host smart-311fbb7b-c6e5-48dd-8e9f-c44b0d59ce6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519815420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1519815420
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.548188115
Short name T481
Test name
Test status
Simulation time 163640005636 ps
CPU time 101.14 seconds
Started Aug 14 05:20:08 PM PDT 24
Finished Aug 14 05:21:49 PM PDT 24
Peak memory 202140 kb
Host smart-315d093f-fb33-4301-af1a-80248f24715e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=548188115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.548188115
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1021136634
Short name T328
Test name
Test status
Simulation time 496915074155 ps
CPU time 67.95 seconds
Started Aug 14 05:20:00 PM PDT 24
Finished Aug 14 05:21:08 PM PDT 24
Peak memory 202116 kb
Host smart-dd4cfcb9-d96d-4fdc-ab82-ef75edca4c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021136634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1021136634
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2703113235
Short name T784
Test name
Test status
Simulation time 486167663286 ps
CPU time 297.87 seconds
Started Aug 14 05:20:01 PM PDT 24
Finished Aug 14 05:24:59 PM PDT 24
Peak memory 202116 kb
Host smart-36814b2a-d3fb-41c6-8867-30f487d3ec1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703113235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2703113235
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3668249057
Short name T332
Test name
Test status
Simulation time 187677056113 ps
CPU time 456.44 seconds
Started Aug 14 05:20:09 PM PDT 24
Finished Aug 14 05:27:46 PM PDT 24
Peak memory 202176 kb
Host smart-ca6b8357-42d4-48b8-82d5-4f903bb8a312
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668249057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3668249057
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1134905151
Short name T528
Test name
Test status
Simulation time 415661494655 ps
CPU time 1009.36 seconds
Started Aug 14 05:20:11 PM PDT 24
Finished Aug 14 05:37:01 PM PDT 24
Peak memory 202140 kb
Host smart-bd4c4f0d-96cb-4fd2-9545-4e337e062617
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134905151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1134905151
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3620421986
Short name T691
Test name
Test status
Simulation time 106386896638 ps
CPU time 394.9 seconds
Started Aug 14 05:20:11 PM PDT 24
Finished Aug 14 05:26:46 PM PDT 24
Peak memory 202380 kb
Host smart-8bc379e4-fddc-4b6d-b619-a0278bbdc5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620421986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3620421986
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2160472181
Short name T656
Test name
Test status
Simulation time 31960025064 ps
CPU time 8.75 seconds
Started Aug 14 05:20:09 PM PDT 24
Finished Aug 14 05:20:18 PM PDT 24
Peak memory 201976 kb
Host smart-e5ebe79d-d557-412b-a9a6-408783cf0b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160472181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2160472181
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1417605284
Short name T719
Test name
Test status
Simulation time 4540238608 ps
CPU time 8.2 seconds
Started Aug 14 05:20:12 PM PDT 24
Finished Aug 14 05:20:20 PM PDT 24
Peak memory 201928 kb
Host smart-3762fa0b-5e87-46cd-b2bb-997968f02417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417605284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1417605284
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3245512258
Short name T128
Test name
Test status
Simulation time 5539838134 ps
CPU time 3.36 seconds
Started Aug 14 05:20:02 PM PDT 24
Finished Aug 14 05:20:06 PM PDT 24
Peak memory 201948 kb
Host smart-e6a30d2d-2fff-4a2d-9154-5e7475d9e9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245512258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3245512258
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1144630924
Short name T774
Test name
Test status
Simulation time 359862774571 ps
CPU time 424.89 seconds
Started Aug 14 05:20:10 PM PDT 24
Finished Aug 14 05:27:15 PM PDT 24
Peak memory 202104 kb
Host smart-ec7bed27-fc96-4ad8-a227-7358137b43bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144630924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1144630924
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.207799605
Short name T46
Test name
Test status
Simulation time 3661271813 ps
CPU time 11.78 seconds
Started Aug 14 05:20:10 PM PDT 24
Finished Aug 14 05:20:22 PM PDT 24
Peak memory 210764 kb
Host smart-2f993bfd-5472-44f7-bfd5-f07a4da6d461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207799605 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.207799605
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3027734359
Short name T531
Test name
Test status
Simulation time 473074469 ps
CPU time 1.72 seconds
Started Aug 14 05:20:17 PM PDT 24
Finished Aug 14 05:20:19 PM PDT 24
Peak memory 201968 kb
Host smart-4196e391-bb26-4378-a5b7-8f363cb8c93e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027734359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3027734359
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3328992914
Short name T221
Test name
Test status
Simulation time 505461325766 ps
CPU time 95.57 seconds
Started Aug 14 05:20:11 PM PDT 24
Finished Aug 14 05:21:47 PM PDT 24
Peak memory 202092 kb
Host smart-99d27aa6-6105-42dc-94a1-6f76b8623d82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328992914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3328992914
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1901554441
Short name T538
Test name
Test status
Simulation time 530560181161 ps
CPU time 325.73 seconds
Started Aug 14 05:20:16 PM PDT 24
Finished Aug 14 05:25:42 PM PDT 24
Peak memory 202160 kb
Host smart-9b6cbb94-73ba-44e9-8e24-19b1df7c9303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901554441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1901554441
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3755005936
Short name T717
Test name
Test status
Simulation time 323430527044 ps
CPU time 747.01 seconds
Started Aug 14 05:20:10 PM PDT 24
Finished Aug 14 05:32:37 PM PDT 24
Peak memory 202160 kb
Host smart-1c85040e-f31d-4f66-bba0-2780941e54e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755005936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3755005936
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1978449020
Short name T495
Test name
Test status
Simulation time 331175878604 ps
CPU time 65.07 seconds
Started Aug 14 05:20:08 PM PDT 24
Finished Aug 14 05:21:13 PM PDT 24
Peak memory 202144 kb
Host smart-59bd5219-3374-4121-b708-bff52fe1ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978449020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1978449020
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.290962793
Short name T791
Test name
Test status
Simulation time 339759221887 ps
CPU time 126.31 seconds
Started Aug 14 05:20:11 PM PDT 24
Finished Aug 14 05:22:17 PM PDT 24
Peak memory 202116 kb
Host smart-6d8caffd-a0c2-490c-b90a-1b08706f8074
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=290962793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.290962793
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3082412496
Short name T265
Test name
Test status
Simulation time 368825880267 ps
CPU time 835.81 seconds
Started Aug 14 05:20:08 PM PDT 24
Finished Aug 14 05:34:04 PM PDT 24
Peak memory 202108 kb
Host smart-faec6dc7-9099-42fc-bba9-61f9683537f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082412496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3082412496
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1965146803
Short name T765
Test name
Test status
Simulation time 594044622178 ps
CPU time 549.01 seconds
Started Aug 14 05:20:10 PM PDT 24
Finished Aug 14 05:29:19 PM PDT 24
Peak memory 202100 kb
Host smart-fd681855-e2c9-40a5-8ce3-3bb72d97d770
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965146803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1965146803
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3814520302
Short name T589
Test name
Test status
Simulation time 111949069933 ps
CPU time 377.64 seconds
Started Aug 14 05:20:21 PM PDT 24
Finished Aug 14 05:26:39 PM PDT 24
Peak memory 202452 kb
Host smart-d4a2310d-a602-4711-96eb-33546df63014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814520302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3814520302
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.472188360
Short name T119
Test name
Test status
Simulation time 28805982104 ps
CPU time 16.68 seconds
Started Aug 14 05:20:16 PM PDT 24
Finished Aug 14 05:20:33 PM PDT 24
Peak memory 201920 kb
Host smart-ce33ea7d-4698-4c75-832c-648161b4549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472188360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.472188360
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1259745376
Short name T680
Test name
Test status
Simulation time 2910348256 ps
CPU time 6.7 seconds
Started Aug 14 05:20:18 PM PDT 24
Finished Aug 14 05:20:25 PM PDT 24
Peak memory 201992 kb
Host smart-b52b2f3d-38cc-4c79-b3c8-e4ebc85b5de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259745376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1259745376
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3983437230
Short name T725
Test name
Test status
Simulation time 5874248378 ps
CPU time 4.55 seconds
Started Aug 14 05:20:09 PM PDT 24
Finished Aug 14 05:20:13 PM PDT 24
Peak memory 201988 kb
Host smart-6f9f4f63-ac1c-400c-8198-d61ef5de97ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983437230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3983437230
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.901953840
Short name T51
Test name
Test status
Simulation time 14768072371 ps
CPU time 28.91 seconds
Started Aug 14 05:20:34 PM PDT 24
Finished Aug 14 05:21:03 PM PDT 24
Peak memory 211120 kb
Host smart-90d6ab56-e36a-4108-b247-aade673087f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901953840 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.901953840
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.324547545
Short name T463
Test name
Test status
Simulation time 425493736 ps
CPU time 1.63 seconds
Started Aug 14 05:20:25 PM PDT 24
Finished Aug 14 05:20:27 PM PDT 24
Peak memory 201980 kb
Host smart-7d63e947-0088-41d3-b506-0b504f9987ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324547545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.324547545
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1779602436
Short name T575
Test name
Test status
Simulation time 351586996073 ps
CPU time 98.82 seconds
Started Aug 14 05:20:25 PM PDT 24
Finished Aug 14 05:22:03 PM PDT 24
Peak memory 202172 kb
Host smart-91382af8-f872-4ee7-b893-9586711cdb59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779602436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1779602436
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2394577987
Short name T304
Test name
Test status
Simulation time 492374635902 ps
CPU time 1132.66 seconds
Started Aug 14 05:20:26 PM PDT 24
Finished Aug 14 05:39:18 PM PDT 24
Peak memory 202144 kb
Host smart-6aec4c77-d673-4308-b7c8-68c7513166cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394577987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2394577987
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1991716906
Short name T573
Test name
Test status
Simulation time 492254387468 ps
CPU time 1181.54 seconds
Started Aug 14 05:20:20 PM PDT 24
Finished Aug 14 05:40:02 PM PDT 24
Peak memory 202136 kb
Host smart-bc09301e-0045-4597-9d5a-bb1b86e773e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991716906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1991716906
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2826957103
Short name T788
Test name
Test status
Simulation time 499650832149 ps
CPU time 1183.14 seconds
Started Aug 14 05:20:20 PM PDT 24
Finished Aug 14 05:40:04 PM PDT 24
Peak memory 202140 kb
Host smart-4f2df8e6-1da2-4602-aef3-de16214e8640
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826957103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2826957103
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.791133229
Short name T454
Test name
Test status
Simulation time 171394845315 ps
CPU time 53.68 seconds
Started Aug 14 05:20:17 PM PDT 24
Finished Aug 14 05:21:11 PM PDT 24
Peak memory 202124 kb
Host smart-cf9b0300-01f3-4a02-9fbc-76009c59ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791133229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.791133229
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.709865038
Short name T633
Test name
Test status
Simulation time 487297250720 ps
CPU time 281.27 seconds
Started Aug 14 05:20:18 PM PDT 24
Finished Aug 14 05:24:59 PM PDT 24
Peak memory 202016 kb
Host smart-a9af4760-d15c-4359-bb15-25c811a7dc61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=709865038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.709865038
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3708950405
Short name T190
Test name
Test status
Simulation time 207108514863 ps
CPU time 236.43 seconds
Started Aug 14 05:20:25 PM PDT 24
Finished Aug 14 05:24:22 PM PDT 24
Peak memory 202148 kb
Host smart-0ede0294-8e5b-4982-adb6-30f9a929540d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708950405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3708950405
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1484448917
Short name T605
Test name
Test status
Simulation time 91502767890 ps
CPU time 353 seconds
Started Aug 14 05:20:24 PM PDT 24
Finished Aug 14 05:26:17 PM PDT 24
Peak memory 202408 kb
Host smart-f85cc27f-ae24-4e42-8d07-65ccac0f1755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484448917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1484448917
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2342082826
Short name T747
Test name
Test status
Simulation time 40522574408 ps
CPU time 89.38 seconds
Started Aug 14 05:20:23 PM PDT 24
Finished Aug 14 05:21:53 PM PDT 24
Peak memory 201968 kb
Host smart-45c5da9b-cf38-4a5e-b7bb-19e6c724fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342082826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2342082826
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2062535025
Short name T591
Test name
Test status
Simulation time 3453613806 ps
CPU time 2.55 seconds
Started Aug 14 05:20:24 PM PDT 24
Finished Aug 14 05:20:26 PM PDT 24
Peak memory 201940 kb
Host smart-4f9fd0b0-ab73-44e4-aa8c-e559569946f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062535025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2062535025
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1624330604
Short name T425
Test name
Test status
Simulation time 5827277172 ps
CPU time 2.31 seconds
Started Aug 14 05:20:17 PM PDT 24
Finished Aug 14 05:20:19 PM PDT 24
Peak memory 201952 kb
Host smart-a41af9d4-2839-4cb4-9b1d-40731494e07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624330604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1624330604
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3389664187
Short name T179
Test name
Test status
Simulation time 207444626224 ps
CPU time 61.74 seconds
Started Aug 14 05:20:24 PM PDT 24
Finished Aug 14 05:21:26 PM PDT 24
Peak memory 202164 kb
Host smart-77476cc3-1e31-4ed4-a571-e33409bf6a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389664187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3389664187
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2436360556
Short name T694
Test name
Test status
Simulation time 2997406614 ps
CPU time 5.81 seconds
Started Aug 14 05:20:24 PM PDT 24
Finished Aug 14 05:20:30 PM PDT 24
Peak memory 202096 kb
Host smart-40e58ac0-6acc-4579-849f-1e74addc85ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436360556 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2436360556
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2035815503
Short name T786
Test name
Test status
Simulation time 421395904 ps
CPU time 1.58 seconds
Started Aug 14 05:20:48 PM PDT 24
Finished Aug 14 05:20:50 PM PDT 24
Peak memory 201784 kb
Host smart-20f134b0-7e93-48ee-98d9-3d569a7d411e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035815503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2035815503
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.714739077
Short name T763
Test name
Test status
Simulation time 330742541482 ps
CPU time 817.86 seconds
Started Aug 14 05:20:35 PM PDT 24
Finished Aug 14 05:34:13 PM PDT 24
Peak memory 202148 kb
Host smart-e5aa7cc1-2f23-47aa-a9a5-c10dfc6557bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714739077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.714739077
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1858202430
Short name T542
Test name
Test status
Simulation time 162474943029 ps
CPU time 344.58 seconds
Started Aug 14 05:20:28 PM PDT 24
Finished Aug 14 05:26:13 PM PDT 24
Peak memory 202188 kb
Host smart-ebdbdac3-98a1-4f26-8da4-a786b72fd2d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858202430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1858202430
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1040654033
Short name T40
Test name
Test status
Simulation time 175797142368 ps
CPU time 101.5 seconds
Started Aug 14 05:20:24 PM PDT 24
Finished Aug 14 05:22:06 PM PDT 24
Peak memory 202144 kb
Host smart-7b8691d1-e79a-449e-9622-f00b5690a967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040654033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1040654033
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3458464779
Short name T769
Test name
Test status
Simulation time 169329367123 ps
CPU time 60.74 seconds
Started Aug 14 05:20:24 PM PDT 24
Finished Aug 14 05:21:24 PM PDT 24
Peak memory 202172 kb
Host smart-f2371a85-c1b2-46a8-a6d7-c0da16c9f755
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458464779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3458464779
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.636617777
Short name T638
Test name
Test status
Simulation time 337220883651 ps
CPU time 760.89 seconds
Started Aug 14 05:20:25 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 202168 kb
Host smart-5f5d41d1-a903-417c-9fd1-2c235c4f0445
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636617777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.636617777
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4110433296
Short name T600
Test name
Test status
Simulation time 196983300520 ps
CPU time 114.25 seconds
Started Aug 14 05:20:31 PM PDT 24
Finished Aug 14 05:22:26 PM PDT 24
Peak memory 202152 kb
Host smart-b1d64bb1-273f-4bbc-ad78-70779fc8bc89
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110433296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4110433296
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3728179503
Short name T702
Test name
Test status
Simulation time 45866905800 ps
CPU time 102.64 seconds
Started Aug 14 05:20:33 PM PDT 24
Finished Aug 14 05:22:16 PM PDT 24
Peak memory 201948 kb
Host smart-2f63b328-d627-42eb-8ef9-a20458b2a44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728179503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3728179503
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.356194097
Short name T588
Test name
Test status
Simulation time 3025448247 ps
CPU time 1.74 seconds
Started Aug 14 05:20:31 PM PDT 24
Finished Aug 14 05:20:33 PM PDT 24
Peak memory 201980 kb
Host smart-539d4d8d-8ca7-4cec-862c-967361fda6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356194097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.356194097
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1726705430
Short name T151
Test name
Test status
Simulation time 5843323727 ps
CPU time 10.63 seconds
Started Aug 14 05:20:23 PM PDT 24
Finished Aug 14 05:20:34 PM PDT 24
Peak memory 201988 kb
Host smart-5b7b08d1-a902-40c1-9631-d4d66625733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726705430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1726705430
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1690508221
Short name T115
Test name
Test status
Simulation time 12276412034 ps
CPU time 27.31 seconds
Started Aug 14 05:20:32 PM PDT 24
Finished Aug 14 05:20:59 PM PDT 24
Peak memory 202200 kb
Host smart-caef0ded-ab0c-4b34-8880-aabd1d2446a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690508221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1690508221
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2009454048
Short name T33
Test name
Test status
Simulation time 46092987011 ps
CPU time 62.18 seconds
Started Aug 14 05:20:33 PM PDT 24
Finished Aug 14 05:21:36 PM PDT 24
Peak memory 210748 kb
Host smart-529e7971-7893-42e2-b43c-a80ff334029b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009454048 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2009454048
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1562691244
Short name T469
Test name
Test status
Simulation time 475848476 ps
CPU time 0.96 seconds
Started Aug 14 05:20:44 PM PDT 24
Finished Aug 14 05:20:45 PM PDT 24
Peak memory 201988 kb
Host smart-9670af02-7eca-4e10-940d-e8a91a4e4dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562691244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1562691244
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.113532988
Short name T174
Test name
Test status
Simulation time 330231187460 ps
CPU time 194.89 seconds
Started Aug 14 05:20:41 PM PDT 24
Finished Aug 14 05:23:56 PM PDT 24
Peak memory 202204 kb
Host smart-e496efd3-fb3b-4c71-8e3c-e5fa5af22ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113532988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.113532988
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2813811793
Short name T211
Test name
Test status
Simulation time 485290009416 ps
CPU time 314.94 seconds
Started Aug 14 05:20:42 PM PDT 24
Finished Aug 14 05:25:57 PM PDT 24
Peak memory 202040 kb
Host smart-2beb5414-9d96-4b6e-adcd-a3d988b77f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813811793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2813811793
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2153218224
Short name T191
Test name
Test status
Simulation time 489077571536 ps
CPU time 582.55 seconds
Started Aug 14 05:20:43 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 202132 kb
Host smart-2034f505-a2ea-40dd-8fcb-d54e3e83daf8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153218224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2153218224
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3191106858
Short name T178
Test name
Test status
Simulation time 332293839789 ps
CPU time 285.39 seconds
Started Aug 14 05:20:42 PM PDT 24
Finished Aug 14 05:25:28 PM PDT 24
Peak memory 202144 kb
Host smart-6a7742a3-9c06-43bf-9ced-d8c63e07d336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191106858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3191106858
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2131001724
Short name T520
Test name
Test status
Simulation time 323469258593 ps
CPU time 195.17 seconds
Started Aug 14 05:20:43 PM PDT 24
Finished Aug 14 05:23:58 PM PDT 24
Peak memory 202116 kb
Host smart-6816d700-ef9c-4f0d-bfd6-21f8db06eec1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131001724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2131001724
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2721378163
Short name T354
Test name
Test status
Simulation time 630582743863 ps
CPU time 324.37 seconds
Started Aug 14 05:20:39 PM PDT 24
Finished Aug 14 05:26:04 PM PDT 24
Peak memory 202176 kb
Host smart-7a144ace-633b-49ca-a194-4d0e22af3b4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721378163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2721378163
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3800623615
Short name T798
Test name
Test status
Simulation time 395583126606 ps
CPU time 921.65 seconds
Started Aug 14 05:20:48 PM PDT 24
Finished Aug 14 05:36:10 PM PDT 24
Peak memory 201968 kb
Host smart-144ccdac-c3ad-4ef5-9dfa-307fff6235c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800623615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3800623615
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3473224606
Short name T227
Test name
Test status
Simulation time 75884826761 ps
CPU time 320.05 seconds
Started Aug 14 05:20:44 PM PDT 24
Finished Aug 14 05:26:04 PM PDT 24
Peak memory 202408 kb
Host smart-7f5c69a3-5905-4959-a33d-c3520992e947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473224606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3473224606
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1473738317
Short name T583
Test name
Test status
Simulation time 23206978813 ps
CPU time 5.88 seconds
Started Aug 14 05:20:41 PM PDT 24
Finished Aug 14 05:20:47 PM PDT 24
Peak memory 201952 kb
Host smart-2f58301d-dcb4-417d-b479-58755f092203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473738317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1473738317
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.228273695
Short name T609
Test name
Test status
Simulation time 3442118483 ps
CPU time 3.99 seconds
Started Aug 14 05:20:41 PM PDT 24
Finished Aug 14 05:20:46 PM PDT 24
Peak memory 201856 kb
Host smart-a27f565d-d76b-4a11-8ddf-750e66ca656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228273695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.228273695
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3978372947
Short name T743
Test name
Test status
Simulation time 5779613160 ps
CPU time 4.48 seconds
Started Aug 14 05:20:43 PM PDT 24
Finished Aug 14 05:20:48 PM PDT 24
Peak memory 201980 kb
Host smart-0e5268aa-1bcb-4d3f-a8d6-0f2392e1d5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978372947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3978372947
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3099761184
Short name T333
Test name
Test status
Simulation time 10800096795 ps
CPU time 12.67 seconds
Started Aug 14 05:20:41 PM PDT 24
Finished Aug 14 05:20:54 PM PDT 24
Peak memory 210532 kb
Host smart-48b641ee-75ad-4275-81dc-9a719b3bc70f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099761184 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3099761184
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2495320877
Short name T671
Test name
Test status
Simulation time 482989316 ps
CPU time 0.92 seconds
Started Aug 14 05:20:50 PM PDT 24
Finished Aug 14 05:20:51 PM PDT 24
Peak memory 201972 kb
Host smart-25250342-edc5-4ca9-a8b7-b3c4d012d24a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495320877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2495320877
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2028609322
Short name T200
Test name
Test status
Simulation time 337748615726 ps
CPU time 58.46 seconds
Started Aug 14 05:20:54 PM PDT 24
Finished Aug 14 05:21:53 PM PDT 24
Peak memory 202216 kb
Host smart-75f246c2-7323-47ef-8b71-14858b4b6390
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028609322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2028609322
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.38697525
Short name T739
Test name
Test status
Simulation time 165169873906 ps
CPU time 97.75 seconds
Started Aug 14 05:20:50 PM PDT 24
Finished Aug 14 05:22:29 PM PDT 24
Peak memory 202132 kb
Host smart-743b6c58-0c9d-4fe4-aa28-e8a697688f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38697525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.38697525
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1773274362
Short name T453
Test name
Test status
Simulation time 163686074946 ps
CPU time 176.91 seconds
Started Aug 14 05:20:54 PM PDT 24
Finished Aug 14 05:23:51 PM PDT 24
Peak memory 202204 kb
Host smart-aa401502-fd40-4e63-ad34-a8bb28533148
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773274362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1773274362
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1543602121
Short name T206
Test name
Test status
Simulation time 497631040785 ps
CPU time 60.45 seconds
Started Aug 14 05:20:41 PM PDT 24
Finished Aug 14 05:21:42 PM PDT 24
Peak memory 202128 kb
Host smart-8fe4b45a-ba18-4f1c-9f43-cf91d373640d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543602121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1543602121
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2764859883
Short name T581
Test name
Test status
Simulation time 504339946260 ps
CPU time 229.24 seconds
Started Aug 14 05:20:44 PM PDT 24
Finished Aug 14 05:24:33 PM PDT 24
Peak memory 202144 kb
Host smart-76b1bb63-4361-4a60-b151-69ce69024299
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764859883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2764859883
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.400625061
Short name T284
Test name
Test status
Simulation time 171334377721 ps
CPU time 391.33 seconds
Started Aug 14 05:20:50 PM PDT 24
Finished Aug 14 05:27:22 PM PDT 24
Peak memory 202124 kb
Host smart-e3013ac9-8b4e-4ce0-902d-3c1ca951cf93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400625061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.400625061
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3823851629
Short name T640
Test name
Test status
Simulation time 581234442225 ps
CPU time 1403.04 seconds
Started Aug 14 05:20:49 PM PDT 24
Finished Aug 14 05:44:12 PM PDT 24
Peak memory 202136 kb
Host smart-d619b7e3-c787-4b60-83b8-8997e94a8e8a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823851629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3823851629
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.785536712
Short name T449
Test name
Test status
Simulation time 99738630097 ps
CPU time 403.84 seconds
Started Aug 14 05:20:48 PM PDT 24
Finished Aug 14 05:27:32 PM PDT 24
Peak memory 202404 kb
Host smart-050f4591-493f-462b-a604-7d1bdefcc2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785536712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.785536712
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2553429350
Short name T637
Test name
Test status
Simulation time 34309097039 ps
CPU time 38.23 seconds
Started Aug 14 05:20:48 PM PDT 24
Finished Aug 14 05:21:26 PM PDT 24
Peak memory 201956 kb
Host smart-77681ed9-c5f2-48f6-9708-c536270cb188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553429350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2553429350
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.329938088
Short name T109
Test name
Test status
Simulation time 3045733265 ps
CPU time 7.53 seconds
Started Aug 14 05:20:48 PM PDT 24
Finished Aug 14 05:20:56 PM PDT 24
Peak memory 201976 kb
Host smart-3c05762a-427f-40f8-bc61-060ef4b7ae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329938088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.329938088
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.571569439
Short name T767
Test name
Test status
Simulation time 5955403302 ps
CPU time 2.83 seconds
Started Aug 14 05:20:41 PM PDT 24
Finished Aug 14 05:20:44 PM PDT 24
Peak memory 201956 kb
Host smart-a10dad2c-99a0-4f28-a305-aa98c8c4dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571569439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.571569439
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3519726114
Short name T236
Test name
Test status
Simulation time 597539266845 ps
CPU time 1682.18 seconds
Started Aug 14 05:20:54 PM PDT 24
Finished Aug 14 05:48:56 PM PDT 24
Peak memory 202460 kb
Host smart-5b66c821-b160-455e-8884-7331cf49a655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519726114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3519726114
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3341303883
Short name T49
Test name
Test status
Simulation time 2681221342 ps
CPU time 2.34 seconds
Started Aug 14 05:20:50 PM PDT 24
Finished Aug 14 05:20:52 PM PDT 24
Peak memory 202020 kb
Host smart-8a46b77b-15e2-47dc-af72-e0f599005be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341303883 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3341303883
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3246953945
Short name T393
Test name
Test status
Simulation time 336172808 ps
CPU time 0.92 seconds
Started Aug 14 05:20:57 PM PDT 24
Finished Aug 14 05:20:58 PM PDT 24
Peak memory 201984 kb
Host smart-122a7344-f834-4885-8cb3-78962a652ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246953945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3246953945
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1649861570
Short name T585
Test name
Test status
Simulation time 338092095183 ps
CPU time 545.02 seconds
Started Aug 14 05:20:58 PM PDT 24
Finished Aug 14 05:30:03 PM PDT 24
Peak memory 202148 kb
Host smart-c8a14c7b-4ab8-4f4f-bf93-a504dab4d7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649861570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1649861570
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4162723838
Short name T252
Test name
Test status
Simulation time 162160933621 ps
CPU time 387.1 seconds
Started Aug 14 05:20:58 PM PDT 24
Finished Aug 14 05:27:25 PM PDT 24
Peak memory 202072 kb
Host smart-21593e76-0e63-4a74-bd94-ea478d737350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162723838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4162723838
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2057940492
Short name T682
Test name
Test status
Simulation time 330778651308 ps
CPU time 739.23 seconds
Started Aug 14 05:20:58 PM PDT 24
Finished Aug 14 05:33:18 PM PDT 24
Peak memory 202148 kb
Host smart-73cf0a2b-124d-4ac2-b1fa-ff9df0a52c9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057940492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2057940492
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1705742362
Short name T95
Test name
Test status
Simulation time 334131785568 ps
CPU time 740.38 seconds
Started Aug 14 05:20:51 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 202132 kb
Host smart-f31915e0-252f-471c-812b-f20d8b962432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705742362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1705742362
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1261821687
Short name T482
Test name
Test status
Simulation time 328605054833 ps
CPU time 202.11 seconds
Started Aug 14 05:20:59 PM PDT 24
Finished Aug 14 05:24:22 PM PDT 24
Peak memory 202164 kb
Host smart-8498061c-8fe6-4276-bce4-b76ffc61911b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261821687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1261821687
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1570198025
Short name T246
Test name
Test status
Simulation time 580249840432 ps
CPU time 362.22 seconds
Started Aug 14 05:20:58 PM PDT 24
Finished Aug 14 05:27:00 PM PDT 24
Peak memory 202132 kb
Host smart-eb15e388-5622-4632-91a6-fe93f6d4bb8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570198025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1570198025
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1142286894
Short name T116
Test name
Test status
Simulation time 199478953464 ps
CPU time 492.2 seconds
Started Aug 14 05:20:58 PM PDT 24
Finished Aug 14 05:29:11 PM PDT 24
Peak memory 202140 kb
Host smart-3ce9d3a5-714d-4833-a18e-a158a9a08a22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142286894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1142286894
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.300504969
Short name T390
Test name
Test status
Simulation time 37011852552 ps
CPU time 41.41 seconds
Started Aug 14 05:20:57 PM PDT 24
Finished Aug 14 05:21:39 PM PDT 24
Peak memory 201960 kb
Host smart-f0877be3-b734-4989-99d9-d8108da44471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300504969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.300504969
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.529585790
Short name T7
Test name
Test status
Simulation time 3374413638 ps
CPU time 1.23 seconds
Started Aug 14 05:21:00 PM PDT 24
Finished Aug 14 05:21:02 PM PDT 24
Peak memory 201944 kb
Host smart-2dd87096-4a05-4510-a6d5-10ccb4cfe0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529585790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.529585790
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.4044308759
Short name T785
Test name
Test status
Simulation time 6084310575 ps
CPU time 3.25 seconds
Started Aug 14 05:20:49 PM PDT 24
Finished Aug 14 05:20:52 PM PDT 24
Peak memory 201964 kb
Host smart-1733245b-c24b-4514-a0ea-0a29b120bc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044308759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4044308759
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1281038262
Short name T783
Test name
Test status
Simulation time 281802428746 ps
CPU time 923.37 seconds
Started Aug 14 05:20:57 PM PDT 24
Finished Aug 14 05:36:20 PM PDT 24
Peak memory 210628 kb
Host smart-6f987d30-da1f-4d06-845d-73f659f13c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281038262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1281038262
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2393126529
Short name T700
Test name
Test status
Simulation time 37141197593 ps
CPU time 17.75 seconds
Started Aug 14 05:21:03 PM PDT 24
Finished Aug 14 05:21:21 PM PDT 24
Peak memory 210696 kb
Host smart-4dbd64af-b131-43e4-a72d-3fe90e23097c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393126529 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2393126529
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2912786766
Short name T612
Test name
Test status
Simulation time 382793411 ps
CPU time 1.42 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:17:29 PM PDT 24
Peak memory 201972 kb
Host smart-35323b45-c110-4bd1-8903-d8423637f72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912786766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2912786766
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2752044626
Short name T325
Test name
Test status
Simulation time 488748367175 ps
CPU time 728.77 seconds
Started Aug 14 05:17:21 PM PDT 24
Finished Aug 14 05:29:30 PM PDT 24
Peak memory 202056 kb
Host smart-7f45be4a-e4a9-4e52-a9da-f5b17cc574e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752044626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2752044626
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4119350864
Short name T216
Test name
Test status
Simulation time 499244098203 ps
CPU time 319.7 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:22:43 PM PDT 24
Peak memory 202128 kb
Host smart-4195362c-b3be-4284-87a3-b6ecb4aef946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119350864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4119350864
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1240526287
Short name T389
Test name
Test status
Simulation time 332840235045 ps
CPU time 808.46 seconds
Started Aug 14 05:17:25 PM PDT 24
Finished Aug 14 05:30:54 PM PDT 24
Peak memory 202136 kb
Host smart-67911b1c-673c-4351-93ce-a413454849d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240526287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1240526287
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.131070528
Short name T225
Test name
Test status
Simulation time 329193353426 ps
CPU time 55.49 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:18:18 PM PDT 24
Peak memory 202152 kb
Host smart-bfd81a7c-1ddd-45a6-8484-9ffc34e404c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131070528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.131070528
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1773365941
Short name T797
Test name
Test status
Simulation time 489580340967 ps
CPU time 742.35 seconds
Started Aug 14 05:17:22 PM PDT 24
Finished Aug 14 05:29:45 PM PDT 24
Peak memory 202124 kb
Host smart-93ea36fa-1479-45e5-b26e-ff28c0be0d30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773365941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1773365941
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1147637780
Short name T627
Test name
Test status
Simulation time 263493057148 ps
CPU time 546.3 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:26:30 PM PDT 24
Peak memory 202152 kb
Host smart-69340ecf-fc79-4bc2-b2b5-1bf8579684ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147637780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1147637780
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1037167629
Short name T562
Test name
Test status
Simulation time 587237840719 ps
CPU time 1381.46 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:40:25 PM PDT 24
Peak memory 202140 kb
Host smart-b952b353-57ef-44c0-adac-1facdc85fb7a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037167629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1037167629
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4191178339
Short name T715
Test name
Test status
Simulation time 41796566436 ps
CPU time 46.7 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:18:10 PM PDT 24
Peak memory 201972 kb
Host smart-24b7a878-8821-462d-9bb8-7fe2fe19b304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191178339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4191178339
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2150830375
Short name T634
Test name
Test status
Simulation time 4465164677 ps
CPU time 6.83 seconds
Started Aug 14 05:17:23 PM PDT 24
Finished Aug 14 05:17:30 PM PDT 24
Peak memory 201952 kb
Host smart-17bee466-d0e3-47bd-9d31-c28266f0d7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150830375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2150830375
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3788748978
Short name T92
Test name
Test status
Simulation time 7464103974 ps
CPU time 5.54 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:17:33 PM PDT 24
Peak memory 218636 kb
Host smart-e5019d0e-3a27-4607-823b-416c12c1f503
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788748978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3788748978
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2160375797
Short name T107
Test name
Test status
Simulation time 5913825819 ps
CPU time 4.41 seconds
Started Aug 14 05:17:24 PM PDT 24
Finished Aug 14 05:17:29 PM PDT 24
Peak memory 202028 kb
Host smart-553f960b-752a-4f98-9dfd-eb6b7ae617e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160375797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2160375797
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.653373933
Short name T339
Test name
Test status
Simulation time 334839304476 ps
CPU time 749.98 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:29:57 PM PDT 24
Peak memory 202136 kb
Host smart-e52b4b1e-d8f1-4c36-b2a3-f5ce408e38d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653373933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.653373933
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3393144815
Short name T508
Test name
Test status
Simulation time 17266290170 ps
CPU time 8.38 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:17:35 PM PDT 24
Peak memory 210480 kb
Host smart-7ad299cb-61fe-478c-b824-92f6b42de6e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393144815 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3393144815
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.803241708
Short name T732
Test name
Test status
Simulation time 477620781 ps
CPU time 1.18 seconds
Started Aug 14 05:21:15 PM PDT 24
Finished Aug 14 05:21:17 PM PDT 24
Peak memory 201988 kb
Host smart-3e608170-6dbe-44ee-ac9e-cbfe52a80a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803241708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.803241708
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3139585352
Short name T794
Test name
Test status
Simulation time 181032170976 ps
CPU time 112.61 seconds
Started Aug 14 05:21:07 PM PDT 24
Finished Aug 14 05:23:00 PM PDT 24
Peak memory 202112 kb
Host smart-709395fd-cef3-478c-a794-dfea0ad64153
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139585352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3139585352
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2915130535
Short name T104
Test name
Test status
Simulation time 262699576681 ps
CPU time 577.2 seconds
Started Aug 14 05:21:08 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 202148 kb
Host smart-b706ecf1-e1ff-4fd1-b208-e6f4f066db87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915130535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2915130535
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.200765166
Short name T728
Test name
Test status
Simulation time 166852851282 ps
CPU time 359.91 seconds
Started Aug 14 05:21:07 PM PDT 24
Finished Aug 14 05:27:07 PM PDT 24
Peak memory 202108 kb
Host smart-cfbf34e2-f1fa-4b03-bf61-ba28907364db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200765166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.200765166
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1021338079
Short name T624
Test name
Test status
Simulation time 500153850761 ps
CPU time 1162.87 seconds
Started Aug 14 05:21:05 PM PDT 24
Finished Aug 14 05:40:28 PM PDT 24
Peak memory 202188 kb
Host smart-4da30a2d-b41e-497e-a3ac-16450ab1790b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021338079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1021338079
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.524074814
Short name T186
Test name
Test status
Simulation time 505224876721 ps
CPU time 1156.59 seconds
Started Aug 14 05:21:07 PM PDT 24
Finished Aug 14 05:40:24 PM PDT 24
Peak memory 202128 kb
Host smart-a7c567e2-9f74-4998-9287-6e85c8138ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524074814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.524074814
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3750577450
Short name T488
Test name
Test status
Simulation time 493388662135 ps
CPU time 1166.03 seconds
Started Aug 14 05:21:07 PM PDT 24
Finished Aug 14 05:40:33 PM PDT 24
Peak memory 202132 kb
Host smart-b89593aa-cc1e-457a-b74a-7124fcd1f68c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750577450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3750577450
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2299523819
Short name T552
Test name
Test status
Simulation time 407118788645 ps
CPU time 238.56 seconds
Started Aug 14 05:21:07 PM PDT 24
Finished Aug 14 05:25:05 PM PDT 24
Peak memory 202164 kb
Host smart-b54902e9-6772-4a29-b56f-4ede0bcddb9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299523819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2299523819
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1158158531
Short name T708
Test name
Test status
Simulation time 101254479810 ps
CPU time 354.16 seconds
Started Aug 14 05:21:15 PM PDT 24
Finished Aug 14 05:27:10 PM PDT 24
Peak memory 202368 kb
Host smart-3720a3f1-d848-48f2-913d-aebc9b475b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158158531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1158158531
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.117328281
Short name T386
Test name
Test status
Simulation time 40527656811 ps
CPU time 97.04 seconds
Started Aug 14 05:21:06 PM PDT 24
Finished Aug 14 05:22:43 PM PDT 24
Peak memory 201984 kb
Host smart-5e4eedd8-ebdf-4e24-9a96-14dbb87b89b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117328281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.117328281
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3379370278
Short name T430
Test name
Test status
Simulation time 3230286417 ps
CPU time 7.8 seconds
Started Aug 14 05:21:06 PM PDT 24
Finished Aug 14 05:21:14 PM PDT 24
Peak memory 201940 kb
Host smart-bedaab0e-e06d-44ef-a18f-a74dcb562c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379370278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3379370278
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3507005131
Short name T720
Test name
Test status
Simulation time 5830456670 ps
CPU time 14.3 seconds
Started Aug 14 05:21:06 PM PDT 24
Finished Aug 14 05:21:20 PM PDT 24
Peak memory 201984 kb
Host smart-e0edd0d5-ceef-45ad-b24c-b64e1c903e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507005131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3507005131
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.473079371
Short name T82
Test name
Test status
Simulation time 27803948849 ps
CPU time 65.34 seconds
Started Aug 14 05:21:14 PM PDT 24
Finished Aug 14 05:22:20 PM PDT 24
Peak memory 201964 kb
Host smart-75bc308f-f887-4976-ba39-711463e1282a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473079371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
473079371
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3455106301
Short name T539
Test name
Test status
Simulation time 77354812252 ps
CPU time 19.38 seconds
Started Aug 14 05:21:15 PM PDT 24
Finished Aug 14 05:21:34 PM PDT 24
Peak memory 211472 kb
Host smart-0c44174b-cb1c-456f-8363-cf28d48a8388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455106301 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3455106301
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3567356558
Short name T758
Test name
Test status
Simulation time 436584262 ps
CPU time 1.49 seconds
Started Aug 14 05:21:25 PM PDT 24
Finished Aug 14 05:21:26 PM PDT 24
Peak memory 201988 kb
Host smart-758907f8-4d51-42bd-97c9-ced31b99b61d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567356558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3567356558
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.917257663
Short name T768
Test name
Test status
Simulation time 165975905327 ps
CPU time 27.48 seconds
Started Aug 14 05:21:16 PM PDT 24
Finished Aug 14 05:21:43 PM PDT 24
Peak memory 202132 kb
Host smart-f277d85c-2548-4f8a-a3ae-b1bf46708ad9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917257663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.917257663
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3646044823
Short name T268
Test name
Test status
Simulation time 510970039931 ps
CPU time 626.1 seconds
Started Aug 14 05:21:15 PM PDT 24
Finished Aug 14 05:31:41 PM PDT 24
Peak memory 202108 kb
Host smart-577939f3-749e-4c4e-a405-809e9f043301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646044823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3646044823
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.550380777
Short name T187
Test name
Test status
Simulation time 492337144559 ps
CPU time 73.65 seconds
Started Aug 14 05:21:14 PM PDT 24
Finished Aug 14 05:22:28 PM PDT 24
Peak memory 202176 kb
Host smart-d3b1090b-d583-4519-86c7-e496ac7334cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550380777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.550380777
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3697273373
Short name T659
Test name
Test status
Simulation time 498012909544 ps
CPU time 587.25 seconds
Started Aug 14 05:21:14 PM PDT 24
Finished Aug 14 05:31:02 PM PDT 24
Peak memory 202084 kb
Host smart-77ad1954-d549-4d60-83d6-8b923a76933a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697273373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3697273373
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1742800037
Short name T561
Test name
Test status
Simulation time 161103530465 ps
CPU time 185.16 seconds
Started Aug 14 05:21:16 PM PDT 24
Finished Aug 14 05:24:21 PM PDT 24
Peak memory 202160 kb
Host smart-767c472a-7b2a-41ec-a138-d28835514089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742800037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1742800037
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3973782565
Short name T667
Test name
Test status
Simulation time 170149310343 ps
CPU time 188.32 seconds
Started Aug 14 05:21:16 PM PDT 24
Finished Aug 14 05:24:25 PM PDT 24
Peak memory 202180 kb
Host smart-8179705a-a9e3-4b3d-b0be-38a64bb799ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973782565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3973782565
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.4211469508
Short name T693
Test name
Test status
Simulation time 215380398573 ps
CPU time 497.79 seconds
Started Aug 14 05:21:16 PM PDT 24
Finished Aug 14 05:29:34 PM PDT 24
Peak memory 202124 kb
Host smart-c4acbb16-5035-4424-a9e8-9f321ba09f7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211469508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.4211469508
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.496777120
Short name T426
Test name
Test status
Simulation time 199900941434 ps
CPU time 472.18 seconds
Started Aug 14 05:21:14 PM PDT 24
Finished Aug 14 05:29:06 PM PDT 24
Peak memory 202156 kb
Host smart-3873a90c-fbf0-41c1-a25c-8f6f6327c1a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496777120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.496777120
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2852362203
Short name T470
Test name
Test status
Simulation time 101164234592 ps
CPU time 253.65 seconds
Started Aug 14 05:21:14 PM PDT 24
Finished Aug 14 05:25:28 PM PDT 24
Peak memory 202384 kb
Host smart-c20bc7d0-ecfe-480f-a59c-5e7cc814d93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852362203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2852362203
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3507858456
Short name T494
Test name
Test status
Simulation time 29022921493 ps
CPU time 16.6 seconds
Started Aug 14 05:21:16 PM PDT 24
Finished Aug 14 05:21:33 PM PDT 24
Peak memory 201996 kb
Host smart-c34578fc-8bc8-43b3-b02a-03d0913abe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507858456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3507858456
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1133829335
Short name T418
Test name
Test status
Simulation time 3805366827 ps
CPU time 1.27 seconds
Started Aug 14 05:21:16 PM PDT 24
Finished Aug 14 05:21:17 PM PDT 24
Peak memory 201972 kb
Host smart-d0bb077b-57c9-4e44-ba74-f592463c708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133829335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1133829335
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1353210455
Short name T772
Test name
Test status
Simulation time 5691211140 ps
CPU time 3.85 seconds
Started Aug 14 05:21:13 PM PDT 24
Finished Aug 14 05:21:17 PM PDT 24
Peak memory 201976 kb
Host smart-54f15711-a9c5-43bc-8660-ac7eb5ecadc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353210455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1353210455
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.499690889
Short name T749
Test name
Test status
Simulation time 397404891888 ps
CPU time 420.02 seconds
Started Aug 14 05:21:24 PM PDT 24
Finished Aug 14 05:28:25 PM PDT 24
Peak memory 210572 kb
Host smart-43232168-1646-439b-a5de-ccb3c145ad79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499690889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
499690889
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2284421760
Short name T663
Test name
Test status
Simulation time 21402324084 ps
CPU time 8.34 seconds
Started Aug 14 05:21:16 PM PDT 24
Finished Aug 14 05:21:25 PM PDT 24
Peak memory 211524 kb
Host smart-f29dfab9-6738-4fd0-aabe-824b5890c29d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284421760 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2284421760
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3690979945
Short name T545
Test name
Test status
Simulation time 437978581 ps
CPU time 1.57 seconds
Started Aug 14 05:21:33 PM PDT 24
Finished Aug 14 05:21:35 PM PDT 24
Peak memory 202000 kb
Host smart-7c75276e-1f09-4c4a-8793-641449ba63d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690979945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3690979945
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3868928629
Short name T277
Test name
Test status
Simulation time 191247513304 ps
CPU time 215.12 seconds
Started Aug 14 05:21:35 PM PDT 24
Finished Aug 14 05:25:10 PM PDT 24
Peak memory 202156 kb
Host smart-a284b4bb-6227-48fc-9a67-1cec0216cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868928629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3868928629
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.764262699
Short name T340
Test name
Test status
Simulation time 167563173776 ps
CPU time 101.58 seconds
Started Aug 14 05:21:33 PM PDT 24
Finished Aug 14 05:23:15 PM PDT 24
Peak memory 202188 kb
Host smart-e3c63212-1dd5-4483-8acb-120bd214b48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764262699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.764262699
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.335534639
Short name T471
Test name
Test status
Simulation time 159359100349 ps
CPU time 363.2 seconds
Started Aug 14 05:21:24 PM PDT 24
Finished Aug 14 05:27:28 PM PDT 24
Peak memory 202148 kb
Host smart-889ab4bd-51dc-4cdd-97d9-7ea9d565c285
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=335534639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.335534639
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1281506149
Short name T158
Test name
Test status
Simulation time 498116310466 ps
CPU time 1180.95 seconds
Started Aug 14 05:21:24 PM PDT 24
Finished Aug 14 05:41:05 PM PDT 24
Peak memory 202164 kb
Host smart-9a618977-263b-42cf-acb0-3033775e2470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281506149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1281506149
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4000631281
Short name T1
Test name
Test status
Simulation time 169511712281 ps
CPU time 409.71 seconds
Started Aug 14 05:21:24 PM PDT 24
Finished Aug 14 05:28:13 PM PDT 24
Peak memory 202164 kb
Host smart-7f9ebf1c-29dc-4763-b2a0-41761f9928f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000631281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4000631281
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.938536541
Short name T217
Test name
Test status
Simulation time 590823668816 ps
CPU time 98.86 seconds
Started Aug 14 05:21:23 PM PDT 24
Finished Aug 14 05:23:02 PM PDT 24
Peak memory 202140 kb
Host smart-19a4abfd-514d-4977-8792-b5741629981d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938536541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.938536541
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3914952431
Short name T42
Test name
Test status
Simulation time 84881964237 ps
CPU time 281.68 seconds
Started Aug 14 05:21:32 PM PDT 24
Finished Aug 14 05:26:14 PM PDT 24
Peak memory 202436 kb
Host smart-7ee6017f-da37-41e5-9f11-f5d2b9306e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914952431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3914952431
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3920682138
Short name T519
Test name
Test status
Simulation time 30352334618 ps
CPU time 74.46 seconds
Started Aug 14 05:21:31 PM PDT 24
Finished Aug 14 05:22:46 PM PDT 24
Peak memory 201956 kb
Host smart-88426f39-5179-444d-8e08-185abd09837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920682138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3920682138
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3031901350
Short name T436
Test name
Test status
Simulation time 3814958503 ps
CPU time 9.9 seconds
Started Aug 14 05:21:32 PM PDT 24
Finished Aug 14 05:21:42 PM PDT 24
Peak memory 201976 kb
Host smart-f9f9db6c-7979-49a5-8249-68d30f58436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031901350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3031901350
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.977546070
Short name T653
Test name
Test status
Simulation time 6103305567 ps
CPU time 6.65 seconds
Started Aug 14 05:21:33 PM PDT 24
Finished Aug 14 05:21:40 PM PDT 24
Peak memory 202024 kb
Host smart-733b4610-0e19-46e9-a878-1aaaeda05d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977546070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.977546070
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1483009325
Short name T646
Test name
Test status
Simulation time 418097876666 ps
CPU time 435.38 seconds
Started Aug 14 05:21:34 PM PDT 24
Finished Aug 14 05:28:49 PM PDT 24
Peak memory 210660 kb
Host smart-20f91f3b-5898-4c6b-8f8f-65ddfabce3b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483009325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1483009325
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.574887022
Short name T19
Test name
Test status
Simulation time 22164453163 ps
CPU time 26.32 seconds
Started Aug 14 05:21:33 PM PDT 24
Finished Aug 14 05:22:00 PM PDT 24
Peak memory 210704 kb
Host smart-807eff29-2364-4cd2-bcec-1764e80b5747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574887022 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.574887022
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2544169393
Short name T441
Test name
Test status
Simulation time 349280554 ps
CPU time 0.77 seconds
Started Aug 14 05:21:41 PM PDT 24
Finished Aug 14 05:21:42 PM PDT 24
Peak memory 201956 kb
Host smart-f082a9d7-11af-4d2d-af10-f0212aab9bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544169393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2544169393
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2710793328
Short name T322
Test name
Test status
Simulation time 373424146823 ps
CPU time 206.09 seconds
Started Aug 14 05:21:32 PM PDT 24
Finished Aug 14 05:24:58 PM PDT 24
Peak memory 202236 kb
Host smart-47e9b6cf-078d-4c2f-b71a-a6f96d1d18f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710793328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2710793328
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1838903269
Short name T628
Test name
Test status
Simulation time 514809193056 ps
CPU time 485.38 seconds
Started Aug 14 05:21:33 PM PDT 24
Finished Aug 14 05:29:39 PM PDT 24
Peak memory 202152 kb
Host smart-4db5cc1b-7f44-46b2-8e25-355f0b6f3a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838903269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1838903269
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.4082614979
Short name T642
Test name
Test status
Simulation time 330485185433 ps
CPU time 213.35 seconds
Started Aug 14 05:21:35 PM PDT 24
Finished Aug 14 05:25:08 PM PDT 24
Peak memory 202160 kb
Host smart-61ed52a4-7892-470e-8e45-5a73f75902fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082614979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.4082614979
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2035259837
Short name T778
Test name
Test status
Simulation time 481958890609 ps
CPU time 1121.42 seconds
Started Aug 14 05:21:35 PM PDT 24
Finished Aug 14 05:40:17 PM PDT 24
Peak memory 202128 kb
Host smart-1ca1118a-346a-4903-b47a-3d090116f3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035259837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2035259837
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2133055876
Short name T512
Test name
Test status
Simulation time 326673138723 ps
CPU time 760.1 seconds
Started Aug 14 05:21:33 PM PDT 24
Finished Aug 14 05:34:13 PM PDT 24
Peak memory 201992 kb
Host smart-8e04410b-9f14-4a53-87b5-510a301d93fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133055876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2133055876
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3576545030
Short name T170
Test name
Test status
Simulation time 345807321824 ps
CPU time 191.85 seconds
Started Aug 14 05:21:34 PM PDT 24
Finished Aug 14 05:24:46 PM PDT 24
Peak memory 202136 kb
Host smart-56b3f4b7-28ee-4753-b1cb-602fa05ff774
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576545030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3576545030
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.4229914964
Short name T718
Test name
Test status
Simulation time 390802868067 ps
CPU time 874.4 seconds
Started Aug 14 05:21:34 PM PDT 24
Finished Aug 14 05:36:09 PM PDT 24
Peak memory 202184 kb
Host smart-4b942ddc-c263-4104-ab9b-ceaebbcf40f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229914964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.4229914964
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.4009388838
Short name T230
Test name
Test status
Simulation time 100696480901 ps
CPU time 516.35 seconds
Started Aug 14 05:21:41 PM PDT 24
Finished Aug 14 05:30:17 PM PDT 24
Peak memory 202400 kb
Host smart-7d0a4401-9cdc-457c-9f54-2302d514fadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009388838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.4009388838
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2469231378
Short name T188
Test name
Test status
Simulation time 31829351175 ps
CPU time 79.08 seconds
Started Aug 14 05:21:50 PM PDT 24
Finished Aug 14 05:23:09 PM PDT 24
Peak memory 202012 kb
Host smart-d2ec6996-38c5-40f1-b348-f2bb011529ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469231378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2469231378
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3300421794
Short name T123
Test name
Test status
Simulation time 4194145868 ps
CPU time 3.06 seconds
Started Aug 14 05:21:34 PM PDT 24
Finished Aug 14 05:21:37 PM PDT 24
Peak memory 201988 kb
Host smart-7b978795-d033-4105-a4d3-5e22bd06ba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300421794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3300421794
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2249748414
Short name T754
Test name
Test status
Simulation time 5588195170 ps
CPU time 7.06 seconds
Started Aug 14 05:21:32 PM PDT 24
Finished Aug 14 05:21:39 PM PDT 24
Peak memory 201856 kb
Host smart-e20565c8-ab27-4502-ac58-d064914667d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249748414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2249748414
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3661293331
Short name T558
Test name
Test status
Simulation time 206778813126 ps
CPU time 98.64 seconds
Started Aug 14 05:21:41 PM PDT 24
Finished Aug 14 05:23:19 PM PDT 24
Peak memory 202128 kb
Host smart-175a494c-c919-4ae9-8018-05c22b97a3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661293331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3661293331
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.583056341
Short name T54
Test name
Test status
Simulation time 3855691026 ps
CPU time 3.32 seconds
Started Aug 14 05:21:42 PM PDT 24
Finished Aug 14 05:21:45 PM PDT 24
Peak memory 202088 kb
Host smart-f1229c3b-09fa-413c-95cb-34b826e32788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583056341 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.583056341
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1472194899
Short name T748
Test name
Test status
Simulation time 464944715 ps
CPU time 1.62 seconds
Started Aug 14 05:21:56 PM PDT 24
Finished Aug 14 05:21:58 PM PDT 24
Peak memory 201992 kb
Host smart-ec6c13ef-4aa3-4a53-919d-03b6119be5d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472194899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1472194899
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2807585577
Short name T68
Test name
Test status
Simulation time 548757311262 ps
CPU time 147.03 seconds
Started Aug 14 05:21:55 PM PDT 24
Finished Aug 14 05:24:22 PM PDT 24
Peak memory 202256 kb
Host smart-08b10b38-7382-4188-a28e-c03a4a21c5f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807585577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2807585577
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2044755710
Short name T168
Test name
Test status
Simulation time 367094332937 ps
CPU time 601.27 seconds
Started Aug 14 05:21:50 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 202124 kb
Host smart-a7e6a258-263b-4490-bf63-8c662637f2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044755710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2044755710
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.525437576
Short name T644
Test name
Test status
Simulation time 163461924639 ps
CPU time 40.98 seconds
Started Aug 14 05:21:40 PM PDT 24
Finished Aug 14 05:22:21 PM PDT 24
Peak memory 202140 kb
Host smart-9ae11964-25a6-40d5-8fb3-47fed4642596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525437576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.525437576
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2805037407
Short name T764
Test name
Test status
Simulation time 488995332421 ps
CPU time 1070.78 seconds
Started Aug 14 05:21:50 PM PDT 24
Finished Aug 14 05:39:41 PM PDT 24
Peak memory 202164 kb
Host smart-f40ecb4a-6685-4bd2-becb-fe07f07d0540
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805037407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2805037407
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.745110126
Short name T321
Test name
Test status
Simulation time 494047014453 ps
CPU time 1058.09 seconds
Started Aug 14 05:21:41 PM PDT 24
Finished Aug 14 05:39:20 PM PDT 24
Peak memory 202116 kb
Host smart-5e461ad7-78d2-4c53-b78c-10ad4f05b9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745110126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.745110126
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2985876577
Short name T198
Test name
Test status
Simulation time 163540675385 ps
CPU time 268.64 seconds
Started Aug 14 05:21:41 PM PDT 24
Finished Aug 14 05:26:10 PM PDT 24
Peak memory 202108 kb
Host smart-181dccca-d134-47af-b54b-449adc944e9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985876577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2985876577
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1824803102
Short name T697
Test name
Test status
Simulation time 170855710411 ps
CPU time 360.51 seconds
Started Aug 14 05:21:41 PM PDT 24
Finished Aug 14 05:27:42 PM PDT 24
Peak memory 202124 kb
Host smart-ed05b4ef-d3ba-4415-b482-e4212ff93e40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824803102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1824803102
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1348980844
Short name T118
Test name
Test status
Simulation time 396824890028 ps
CPU time 211.35 seconds
Started Aug 14 05:21:54 PM PDT 24
Finished Aug 14 05:25:26 PM PDT 24
Peak memory 202164 kb
Host smart-e12d2356-3aa9-4344-b665-4b5b6eba1d3b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348980844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1348980844
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3464073687
Short name T567
Test name
Test status
Simulation time 101875191803 ps
CPU time 345.91 seconds
Started Aug 14 05:21:49 PM PDT 24
Finished Aug 14 05:27:35 PM PDT 24
Peak memory 202384 kb
Host smart-32a2ab0c-b88e-4117-ad1f-f27424d6340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464073687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3464073687
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4275871260
Short name T658
Test name
Test status
Simulation time 27357338302 ps
CPU time 17.19 seconds
Started Aug 14 05:21:49 PM PDT 24
Finished Aug 14 05:22:07 PM PDT 24
Peak memory 201980 kb
Host smart-423fb9aa-b3d0-4b0a-b4d7-748e470feb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275871260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4275871260
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2261758333
Short name T525
Test name
Test status
Simulation time 4786595181 ps
CPU time 12.2 seconds
Started Aug 14 05:21:49 PM PDT 24
Finished Aug 14 05:22:01 PM PDT 24
Peak memory 201960 kb
Host smart-8befa6e8-0a58-4ea7-99a0-c52e676458b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261758333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2261758333
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2280651790
Short name T108
Test name
Test status
Simulation time 5946103537 ps
CPU time 4.3 seconds
Started Aug 14 05:21:43 PM PDT 24
Finished Aug 14 05:21:47 PM PDT 24
Peak memory 201916 kb
Host smart-8f1a7299-7f9f-461e-84ef-c9a9eee7c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280651790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2280651790
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1014642001
Short name T22
Test name
Test status
Simulation time 3152994626 ps
CPU time 8.06 seconds
Started Aug 14 05:21:48 PM PDT 24
Finished Aug 14 05:21:56 PM PDT 24
Peak memory 202032 kb
Host smart-d5035c8a-9c9f-43ee-8a09-bf83b8c444a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014642001 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1014642001
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1295688636
Short name T388
Test name
Test status
Simulation time 518314043 ps
CPU time 0.79 seconds
Started Aug 14 05:22:06 PM PDT 24
Finished Aug 14 05:22:07 PM PDT 24
Peak memory 202000 kb
Host smart-780d06b6-8cf6-4625-adf9-339233bcf4b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295688636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1295688636
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3893902856
Short name T629
Test name
Test status
Simulation time 176539901743 ps
CPU time 419.84 seconds
Started Aug 14 05:21:58 PM PDT 24
Finished Aug 14 05:28:58 PM PDT 24
Peak memory 202156 kb
Host smart-29453e18-0931-49a6-a5dc-aa20361e3d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893902856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3893902856
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1669853008
Short name T473
Test name
Test status
Simulation time 164423266506 ps
CPU time 350.77 seconds
Started Aug 14 05:21:59 PM PDT 24
Finished Aug 14 05:27:50 PM PDT 24
Peak memory 202120 kb
Host smart-5691f382-81db-4a88-8355-0c523cb05ff2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669853008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1669853008
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2228656588
Short name T342
Test name
Test status
Simulation time 496131149137 ps
CPU time 1023.68 seconds
Started Aug 14 05:21:58 PM PDT 24
Finished Aug 14 05:39:02 PM PDT 24
Peak memory 202132 kb
Host smart-9305920d-d8fb-43a2-9540-8e93b3c7f615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228656588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2228656588
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.4133876900
Short name T412
Test name
Test status
Simulation time 329475669178 ps
CPU time 375.28 seconds
Started Aug 14 05:21:58 PM PDT 24
Finished Aug 14 05:28:14 PM PDT 24
Peak memory 202124 kb
Host smart-9af9e0b6-e927-47ee-b0cf-2adcffc94240
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133876900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.4133876900
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1352280315
Short name T738
Test name
Test status
Simulation time 169896842803 ps
CPU time 92.35 seconds
Started Aug 14 05:22:06 PM PDT 24
Finished Aug 14 05:23:38 PM PDT 24
Peak memory 202104 kb
Host smart-53d9c082-bfec-4aa2-b0be-4dabb36966e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352280315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1352280315
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2568970220
Short name T452
Test name
Test status
Simulation time 609104168644 ps
CPU time 356.43 seconds
Started Aug 14 05:21:57 PM PDT 24
Finished Aug 14 05:27:54 PM PDT 24
Peak memory 202124 kb
Host smart-9c08b085-09dc-46eb-9ddf-b6b43ff506f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568970220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2568970220
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1699540538
Short name T374
Test name
Test status
Simulation time 140436670820 ps
CPU time 488.27 seconds
Started Aug 14 05:22:07 PM PDT 24
Finished Aug 14 05:30:15 PM PDT 24
Peak memory 202404 kb
Host smart-b97ee37a-89d6-40d2-934e-d8b719e271d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699540538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1699540538
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1281304812
Short name T553
Test name
Test status
Simulation time 34663700883 ps
CPU time 21.29 seconds
Started Aug 14 05:21:59 PM PDT 24
Finished Aug 14 05:22:20 PM PDT 24
Peak memory 201936 kb
Host smart-35a72ddc-fd8c-4566-a889-0bb5cd4ec06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281304812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1281304812
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2495649634
Short name T523
Test name
Test status
Simulation time 3850435270 ps
CPU time 2.8 seconds
Started Aug 14 05:21:58 PM PDT 24
Finished Aug 14 05:22:01 PM PDT 24
Peak memory 201984 kb
Host smart-fa2e87c1-3662-447e-9d3e-f1fbd4e74a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495649634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2495649634
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1959883885
Short name T127
Test name
Test status
Simulation time 5572163832 ps
CPU time 13.46 seconds
Started Aug 14 05:21:58 PM PDT 24
Finished Aug 14 05:22:12 PM PDT 24
Peak memory 201976 kb
Host smart-312a0529-d9fb-4f2b-8248-76ad4b317e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959883885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1959883885
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.854895849
Short name T152
Test name
Test status
Simulation time 333864547368 ps
CPU time 404.92 seconds
Started Aug 14 05:22:05 PM PDT 24
Finished Aug 14 05:28:50 PM PDT 24
Peak memory 202084 kb
Host smart-8c87344e-68f0-4593-b3af-254e30d2dc8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854895849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
854895849
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2359493992
Short name T527
Test name
Test status
Simulation time 2157765453 ps
CPU time 11.08 seconds
Started Aug 14 05:22:08 PM PDT 24
Finished Aug 14 05:22:20 PM PDT 24
Peak memory 210584 kb
Host smart-5cb9bb21-908b-400b-b8a6-218b86741e22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359493992 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2359493992
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1762574824
Short name T673
Test name
Test status
Simulation time 380365458 ps
CPU time 0.75 seconds
Started Aug 14 05:22:15 PM PDT 24
Finished Aug 14 05:22:16 PM PDT 24
Peak memory 202000 kb
Host smart-7d82de52-3a47-473f-b526-2cc946134c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762574824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1762574824
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3870432580
Short name T308
Test name
Test status
Simulation time 174551515517 ps
CPU time 34.16 seconds
Started Aug 14 05:22:15 PM PDT 24
Finished Aug 14 05:22:50 PM PDT 24
Peak memory 202132 kb
Host smart-7af6ba97-54bc-430f-bc0a-b8e0d9e5d165
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870432580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3870432580
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1659035865
Short name T12
Test name
Test status
Simulation time 322888230530 ps
CPU time 778.49 seconds
Started Aug 14 05:22:07 PM PDT 24
Finished Aug 14 05:35:06 PM PDT 24
Peak memory 202160 kb
Host smart-a6543d80-18e7-4ef9-a4bc-7ec91cc81533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659035865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1659035865
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1196926202
Short name T582
Test name
Test status
Simulation time 327035585285 ps
CPU time 759.31 seconds
Started Aug 14 05:22:07 PM PDT 24
Finished Aug 14 05:34:46 PM PDT 24
Peak memory 202168 kb
Host smart-c2957aef-c86c-4078-9490-b0155bd00c1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196926202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1196926202
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1082238287
Short name T336
Test name
Test status
Simulation time 167190569187 ps
CPU time 71.58 seconds
Started Aug 14 05:22:07 PM PDT 24
Finished Aug 14 05:23:19 PM PDT 24
Peak memory 202152 kb
Host smart-5215c8b3-988a-44d3-8687-95a4b693d189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082238287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1082238287
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1707774108
Short name T110
Test name
Test status
Simulation time 329529773274 ps
CPU time 773.1 seconds
Started Aug 14 05:22:06 PM PDT 24
Finished Aug 14 05:35:00 PM PDT 24
Peak memory 202128 kb
Host smart-492c0641-971b-4338-8410-c3804c29f0d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707774108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1707774108
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1473130474
Short name T358
Test name
Test status
Simulation time 457754624031 ps
CPU time 1013 seconds
Started Aug 14 05:22:09 PM PDT 24
Finished Aug 14 05:39:02 PM PDT 24
Peak memory 202028 kb
Host smart-907e070b-1fa0-43cb-9523-66a6e015d71c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473130474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1473130474
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1482735057
Short name T379
Test name
Test status
Simulation time 408452694897 ps
CPU time 227.09 seconds
Started Aug 14 05:22:08 PM PDT 24
Finished Aug 14 05:25:55 PM PDT 24
Peak memory 202024 kb
Host smart-a8913e6d-18be-4ecb-aa35-f7c0ab3d3344
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482735057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1482735057
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2647435125
Short name T208
Test name
Test status
Simulation time 45968373731 ps
CPU time 98.89 seconds
Started Aug 14 05:22:13 PM PDT 24
Finished Aug 14 05:23:52 PM PDT 24
Peak memory 201960 kb
Host smart-d1f52e3a-4c72-4b3c-bc48-a7c2d1ac9997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647435125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2647435125
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2980262371
Short name T431
Test name
Test status
Simulation time 2808393101 ps
CPU time 4.01 seconds
Started Aug 14 05:22:15 PM PDT 24
Finished Aug 14 05:22:19 PM PDT 24
Peak memory 201968 kb
Host smart-0a83e3d6-fb1d-4e06-aa82-6374954d0892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980262371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2980262371
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.4175592676
Short name T716
Test name
Test status
Simulation time 5874103089 ps
CPU time 2.71 seconds
Started Aug 14 05:22:06 PM PDT 24
Finished Aug 14 05:22:09 PM PDT 24
Peak memory 201968 kb
Host smart-d42216af-165b-483d-bb85-26b33727efce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175592676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4175592676
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.807023760
Short name T278
Test name
Test status
Simulation time 497502035566 ps
CPU time 420.84 seconds
Started Aug 14 05:22:25 PM PDT 24
Finished Aug 14 05:29:26 PM PDT 24
Peak memory 212900 kb
Host smart-fbb2860c-94a7-4f50-8fc5-0d43d4e8232b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807023760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
807023760
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3443710309
Short name T14
Test name
Test status
Simulation time 9385148253 ps
CPU time 11.2 seconds
Started Aug 14 05:22:15 PM PDT 24
Finished Aug 14 05:22:26 PM PDT 24
Peak memory 210564 kb
Host smart-e7bf833e-6eea-4f0e-bcf6-9c2ba1e625bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443710309 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3443710309
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2299387801
Short name T672
Test name
Test status
Simulation time 381929213 ps
CPU time 1.49 seconds
Started Aug 14 05:22:30 PM PDT 24
Finished Aug 14 05:22:31 PM PDT 24
Peak memory 201992 kb
Host smart-2c79c77a-3eeb-4661-839e-62e91b4cdbed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299387801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2299387801
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1477567677
Short name T126
Test name
Test status
Simulation time 162338082411 ps
CPU time 102.69 seconds
Started Aug 14 05:22:26 PM PDT 24
Finished Aug 14 05:24:09 PM PDT 24
Peak memory 202204 kb
Host smart-b4c677c1-65d2-4c2d-9612-62f209db7988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477567677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1477567677
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.378667783
Short name T597
Test name
Test status
Simulation time 160194889238 ps
CPU time 400.29 seconds
Started Aug 14 05:22:25 PM PDT 24
Finished Aug 14 05:29:06 PM PDT 24
Peak memory 202104 kb
Host smart-5192d94c-6dab-4347-9448-341dbfdf1571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378667783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.378667783
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1668001448
Short name T626
Test name
Test status
Simulation time 322409705744 ps
CPU time 249.85 seconds
Started Aug 14 05:22:25 PM PDT 24
Finished Aug 14 05:26:35 PM PDT 24
Peak memory 202188 kb
Host smart-3e823def-4abf-444c-820b-13be247dcf0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668001448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1668001448
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1962403545
Short name T100
Test name
Test status
Simulation time 328475564156 ps
CPU time 191.87 seconds
Started Aug 14 05:22:26 PM PDT 24
Finished Aug 14 05:25:38 PM PDT 24
Peak memory 202168 kb
Host smart-374a5f4e-713b-4b07-bba0-551faebdb055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962403545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1962403545
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1374974302
Short name T711
Test name
Test status
Simulation time 491135347730 ps
CPU time 1117.34 seconds
Started Aug 14 05:22:25 PM PDT 24
Finished Aug 14 05:41:03 PM PDT 24
Peak memory 202180 kb
Host smart-437037c0-1649-421c-acd2-0f4c9a5184f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374974302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1374974302
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3887775325
Short name T157
Test name
Test status
Simulation time 535272742289 ps
CPU time 325.54 seconds
Started Aug 14 05:22:26 PM PDT 24
Finished Aug 14 05:27:52 PM PDT 24
Peak memory 202120 kb
Host smart-2f225ba4-b71d-4e63-acc5-3a91252ee596
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887775325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3887775325
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2794513849
Short name T540
Test name
Test status
Simulation time 405583082088 ps
CPU time 254.85 seconds
Started Aug 14 05:22:27 PM PDT 24
Finished Aug 14 05:26:42 PM PDT 24
Peak memory 202196 kb
Host smart-2866d48a-b378-4bf7-82b9-f52f21586cd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794513849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2794513849
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3472817043
Short name T534
Test name
Test status
Simulation time 101457499116 ps
CPU time 416.35 seconds
Started Aug 14 05:22:25 PM PDT 24
Finished Aug 14 05:29:21 PM PDT 24
Peak memory 202452 kb
Host smart-fbda89f0-08c0-4510-af75-017a91d95b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472817043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3472817043
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2913354992
Short name T450
Test name
Test status
Simulation time 42751575333 ps
CPU time 100.41 seconds
Started Aug 14 05:22:25 PM PDT 24
Finished Aug 14 05:24:06 PM PDT 24
Peak memory 201960 kb
Host smart-18e52561-b34b-4671-bd9c-77ced72d8d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913354992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2913354992
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.924568442
Short name T487
Test name
Test status
Simulation time 5141921414 ps
CPU time 11.43 seconds
Started Aug 14 05:22:25 PM PDT 24
Finished Aug 14 05:22:37 PM PDT 24
Peak memory 202000 kb
Host smart-c6e3856e-e074-4041-b60e-3ab4ae99c96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924568442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.924568442
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3544381910
Short name T394
Test name
Test status
Simulation time 5654120817 ps
CPU time 3.9 seconds
Started Aug 14 05:22:32 PM PDT 24
Finished Aug 14 05:22:36 PM PDT 24
Peak memory 201972 kb
Host smart-33aa3216-fbf5-469d-b0d3-b8f84aa400b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544381910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3544381910
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1820290128
Short name T61
Test name
Test status
Simulation time 321436150733 ps
CPU time 1108.44 seconds
Started Aug 14 05:22:26 PM PDT 24
Finished Aug 14 05:40:55 PM PDT 24
Peak memory 218724 kb
Host smart-65dfc28b-65b1-416f-a231-ed3a85ca396f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820290128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1820290128
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.568188765
Short name T20
Test name
Test status
Simulation time 14348283323 ps
CPU time 6.03 seconds
Started Aug 14 05:22:26 PM PDT 24
Finished Aug 14 05:22:32 PM PDT 24
Peak memory 210468 kb
Host smart-f4513542-327f-4faf-a7d2-6deca7dc6d47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568188765 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.568188765
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.145134807
Short name T421
Test name
Test status
Simulation time 463064296 ps
CPU time 1.63 seconds
Started Aug 14 05:22:38 PM PDT 24
Finished Aug 14 05:22:39 PM PDT 24
Peak memory 201984 kb
Host smart-6b8ba034-c7a7-4175-a934-0c166272077f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145134807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.145134807
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.4146211958
Short name T721
Test name
Test status
Simulation time 347594760756 ps
CPU time 383.63 seconds
Started Aug 14 05:22:29 PM PDT 24
Finished Aug 14 05:28:53 PM PDT 24
Peak memory 202116 kb
Host smart-7f9add0a-3961-4225-9493-cdc204d34ce0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146211958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.4146211958
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1957939618
Short name T106
Test name
Test status
Simulation time 413454986137 ps
CPU time 475.34 seconds
Started Aug 14 05:22:30 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 202136 kb
Host smart-cae56bd7-8a16-4555-ad9f-a1eea7f2e3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957939618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1957939618
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3122528408
Short name T578
Test name
Test status
Simulation time 326223942643 ps
CPU time 784.58 seconds
Started Aug 14 05:22:30 PM PDT 24
Finished Aug 14 05:35:34 PM PDT 24
Peak memory 202108 kb
Host smart-f263e0fd-5156-4e1c-bee6-8cd6638e70ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122528408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3122528408
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4075970488
Short name T387
Test name
Test status
Simulation time 161739718530 ps
CPU time 133.31 seconds
Started Aug 14 05:22:35 PM PDT 24
Finished Aug 14 05:24:49 PM PDT 24
Peak memory 202168 kb
Host smart-087d162e-4111-4729-b492-176263639ddf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075970488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4075970488
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.4134230513
Short name T479
Test name
Test status
Simulation time 164812432882 ps
CPU time 384.89 seconds
Started Aug 14 05:22:34 PM PDT 24
Finished Aug 14 05:28:59 PM PDT 24
Peak memory 202120 kb
Host smart-650c2b92-1d17-4adf-9f70-1625aef27ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134230513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4134230513
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.321587422
Short name T792
Test name
Test status
Simulation time 328065792741 ps
CPU time 733.42 seconds
Started Aug 14 05:22:29 PM PDT 24
Finished Aug 14 05:34:42 PM PDT 24
Peak memory 202092 kb
Host smart-58d46204-066b-4342-a35e-4772b4ea0319
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=321587422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.321587422
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3154928677
Short name T114
Test name
Test status
Simulation time 612363725069 ps
CPU time 680.18 seconds
Started Aug 14 05:22:34 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 202124 kb
Host smart-78bfe4aa-0258-4bdb-97a5-3a78d2a45ea3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154928677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3154928677
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2793217611
Short name T233
Test name
Test status
Simulation time 116217016651 ps
CPU time 598.06 seconds
Started Aug 14 05:22:31 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 202388 kb
Host smart-9f481ac6-deb9-4ff3-9679-7b54ca6d1e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793217611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2793217611
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3222221946
Short name T734
Test name
Test status
Simulation time 36887024496 ps
CPU time 39.4 seconds
Started Aug 14 05:22:29 PM PDT 24
Finished Aug 14 05:23:09 PM PDT 24
Peak memory 201880 kb
Host smart-86a3e9af-2691-45ad-821e-fc5a58592e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222221946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3222221946
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2999520883
Short name T565
Test name
Test status
Simulation time 5370429199 ps
CPU time 11.02 seconds
Started Aug 14 05:22:34 PM PDT 24
Finished Aug 14 05:22:45 PM PDT 24
Peak memory 201960 kb
Host smart-94570a50-372a-4baa-be16-d9863b6613a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999520883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2999520883
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.366068038
Short name T443
Test name
Test status
Simulation time 5796636641 ps
CPU time 14.83 seconds
Started Aug 14 05:22:28 PM PDT 24
Finished Aug 14 05:22:43 PM PDT 24
Peak memory 201960 kb
Host smart-17cc0e46-80d1-4597-a587-7d85deda884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366068038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.366068038
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3826747433
Short name T777
Test name
Test status
Simulation time 331135009398 ps
CPU time 700.8 seconds
Started Aug 14 05:22:29 PM PDT 24
Finished Aug 14 05:34:10 PM PDT 24
Peak memory 202024 kb
Host smart-048ff240-9a6a-4aed-a183-890e9800a6ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826747433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3826747433
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1280148572
Short name T759
Test name
Test status
Simulation time 20343509694 ps
CPU time 9.44 seconds
Started Aug 14 05:22:29 PM PDT 24
Finished Aug 14 05:22:38 PM PDT 24
Peak memory 202080 kb
Host smart-b25c95cd-7240-4039-a535-0ec9f5906218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280148572 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1280148572
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3132883463
Short name T411
Test name
Test status
Simulation time 348920045 ps
CPU time 1.33 seconds
Started Aug 14 05:22:46 PM PDT 24
Finished Aug 14 05:22:48 PM PDT 24
Peak memory 201984 kb
Host smart-6b278ae5-9bf0-4960-8c42-d6172b2d81a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132883463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3132883463
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3754327548
Short name T154
Test name
Test status
Simulation time 349426288626 ps
CPU time 167 seconds
Started Aug 14 05:22:37 PM PDT 24
Finished Aug 14 05:25:24 PM PDT 24
Peak memory 202216 kb
Host smart-92b9f169-21fb-4272-9006-179747a43a4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754327548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3754327548
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2991584696
Short name T274
Test name
Test status
Simulation time 329791212131 ps
CPU time 755.9 seconds
Started Aug 14 05:22:38 PM PDT 24
Finished Aug 14 05:35:14 PM PDT 24
Peak memory 202176 kb
Host smart-88d6a5f6-70c2-4fcf-86aa-798522c198a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991584696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2991584696
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3396261363
Short name T5
Test name
Test status
Simulation time 340626540177 ps
CPU time 98.97 seconds
Started Aug 14 05:22:38 PM PDT 24
Finished Aug 14 05:24:17 PM PDT 24
Peak memory 202168 kb
Host smart-1f415317-2e08-47ab-97ed-d35ea7c5fe5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396261363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3396261363
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.186926925
Short name T466
Test name
Test status
Simulation time 335858694181 ps
CPU time 362.03 seconds
Started Aug 14 05:22:37 PM PDT 24
Finished Aug 14 05:28:39 PM PDT 24
Peak memory 202148 kb
Host smart-3abd0591-21fe-4ada-93a0-9133fc187f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186926925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.186926925
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.752787760
Short name T420
Test name
Test status
Simulation time 329888290800 ps
CPU time 700.23 seconds
Started Aug 14 05:22:37 PM PDT 24
Finished Aug 14 05:34:18 PM PDT 24
Peak memory 202108 kb
Host smart-b8ff2f64-37ab-44da-88b5-ed46afc2a675
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=752787760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.752787760
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1668836291
Short name T405
Test name
Test status
Simulation time 167560316289 ps
CPU time 91.52 seconds
Started Aug 14 05:22:36 PM PDT 24
Finished Aug 14 05:24:08 PM PDT 24
Peak memory 202172 kb
Host smart-8f9e511c-e7b2-40a7-9b0b-58bbc496044e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668836291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1668836291
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.880892065
Short name T384
Test name
Test status
Simulation time 399448189158 ps
CPU time 591.9 seconds
Started Aug 14 05:22:37 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 202132 kb
Host smart-c9136e4d-dbf4-4684-934f-de2da2f05e5f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880892065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.880892065
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1745543883
Short name T59
Test name
Test status
Simulation time 120791873134 ps
CPU time 463.38 seconds
Started Aug 14 05:22:44 PM PDT 24
Finished Aug 14 05:30:28 PM PDT 24
Peak memory 202552 kb
Host smart-a55af9f4-816c-4821-90f7-87ac85d0a088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745543883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1745543883
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.768354310
Short name T381
Test name
Test status
Simulation time 42981003542 ps
CPU time 42.72 seconds
Started Aug 14 05:22:45 PM PDT 24
Finished Aug 14 05:23:28 PM PDT 24
Peak memory 201972 kb
Host smart-57642716-2534-4f1f-b3c7-81852ac71b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768354310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.768354310
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.4196222332
Short name T477
Test name
Test status
Simulation time 4497462144 ps
CPU time 11.32 seconds
Started Aug 14 05:22:43 PM PDT 24
Finished Aug 14 05:22:55 PM PDT 24
Peak memory 201976 kb
Host smart-311c3675-4f86-4ed1-9232-a098a291f498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196222332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.4196222332
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.381895438
Short name T416
Test name
Test status
Simulation time 5659688896 ps
CPU time 13.65 seconds
Started Aug 14 05:22:37 PM PDT 24
Finished Aug 14 05:22:51 PM PDT 24
Peak memory 201936 kb
Host smart-2ebd8601-0da9-414b-954c-dc665973023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381895438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.381895438
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4116324090
Short name T662
Test name
Test status
Simulation time 437368481 ps
CPU time 0.86 seconds
Started Aug 14 05:17:31 PM PDT 24
Finished Aug 14 05:17:32 PM PDT 24
Peak memory 201952 kb
Host smart-0a2db27b-56eb-464b-9500-371bb0fcd3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116324090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4116324090
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.441001900
Short name T244
Test name
Test status
Simulation time 572483774361 ps
CPU time 1225.78 seconds
Started Aug 14 05:17:26 PM PDT 24
Finished Aug 14 05:37:52 PM PDT 24
Peak memory 202144 kb
Host smart-317277de-d9ba-47a7-84eb-f8d5a38d43b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441001900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.441001900
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3983351354
Short name T129
Test name
Test status
Simulation time 163846650299 ps
CPU time 68.54 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:18:36 PM PDT 24
Peak memory 202024 kb
Host smart-ce5464e3-ef31-4b20-88a0-69a4c3e00892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983351354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3983351354
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1789801286
Short name T125
Test name
Test status
Simulation time 506572967320 ps
CPU time 1128.48 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:36:16 PM PDT 24
Peak memory 202152 kb
Host smart-07f8453f-79aa-4638-bb79-fdc456f23a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789801286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1789801286
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.357208265
Short name T705
Test name
Test status
Simulation time 507488224771 ps
CPU time 301.95 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:22:29 PM PDT 24
Peak memory 202184 kb
Host smart-8913d965-cc53-40ea-b8c1-32b95786a99d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=357208265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.357208265
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2051693946
Short name T518
Test name
Test status
Simulation time 164281524222 ps
CPU time 45.79 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:18:13 PM PDT 24
Peak memory 202056 kb
Host smart-8e27f698-5a6e-40d4-8762-13001b30d252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051693946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2051693946
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3569923668
Short name T409
Test name
Test status
Simulation time 485258596128 ps
CPU time 580.67 seconds
Started Aug 14 05:17:29 PM PDT 24
Finished Aug 14 05:27:10 PM PDT 24
Peak memory 202084 kb
Host smart-0c6046a5-8b0b-4914-a555-d01f97bdb1c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569923668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3569923668
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3922551034
Short name T590
Test name
Test status
Simulation time 597452144127 ps
CPU time 601.06 seconds
Started Aug 14 05:17:28 PM PDT 24
Finished Aug 14 05:27:30 PM PDT 24
Peak memory 202140 kb
Host smart-13e605cb-e936-4fa9-8692-ed01d2cf8f91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922551034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3922551034
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2353598665
Short name T176
Test name
Test status
Simulation time 127079365067 ps
CPU time 445.44 seconds
Started Aug 14 05:17:28 PM PDT 24
Finished Aug 14 05:24:54 PM PDT 24
Peak memory 202436 kb
Host smart-6c982824-74b0-44d4-9d18-07d4318e8a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353598665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2353598665
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.754472002
Short name T417
Test name
Test status
Simulation time 29961384446 ps
CPU time 20.32 seconds
Started Aug 14 05:17:28 PM PDT 24
Finished Aug 14 05:17:48 PM PDT 24
Peak memory 201828 kb
Host smart-f88231fc-da2a-4163-8a26-879c727cc0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754472002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.754472002
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2849146963
Short name T2
Test name
Test status
Simulation time 5155843059 ps
CPU time 3.99 seconds
Started Aug 14 05:17:27 PM PDT 24
Finished Aug 14 05:17:31 PM PDT 24
Peak memory 201968 kb
Host smart-3d4845da-35ca-46ee-acad-484fc4f61fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849146963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2849146963
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2765913743
Short name T401
Test name
Test status
Simulation time 5701424137 ps
CPU time 6.86 seconds
Started Aug 14 05:17:28 PM PDT 24
Finished Aug 14 05:17:35 PM PDT 24
Peak memory 202136 kb
Host smart-b6c0b0e7-7dcd-4bd4-8a2c-d29844ee41c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765913743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2765913743
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2169366021
Short name T226
Test name
Test status
Simulation time 45297839376 ps
CPU time 25.39 seconds
Started Aug 14 05:17:30 PM PDT 24
Finished Aug 14 05:17:55 PM PDT 24
Peak memory 201988 kb
Host smart-088a02dc-0162-4749-a89d-f12b4bedd4ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169366021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2169366021
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.327614894
Short name T722
Test name
Test status
Simulation time 3216422018 ps
CPU time 4.42 seconds
Started Aug 14 05:17:28 PM PDT 24
Finished Aug 14 05:17:32 PM PDT 24
Peak memory 202056 kb
Host smart-2caa52ff-6576-468c-9153-6057865b02a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327614894 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.327614894
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.494318863
Short name T13
Test name
Test status
Simulation time 406538470 ps
CPU time 0.9 seconds
Started Aug 14 05:17:37 PM PDT 24
Finished Aug 14 05:17:38 PM PDT 24
Peak memory 201988 kb
Host smart-afc0dd1e-026f-4119-a14a-7ae07b0e1168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494318863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.494318863
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.695833087
Short name T687
Test name
Test status
Simulation time 166091673133 ps
CPU time 361.12 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:23:34 PM PDT 24
Peak memory 202088 kb
Host smart-e19e7de8-f7a1-47cb-a1e2-79cfe8ccd770
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695833087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.695833087
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1742370006
Short name T712
Test name
Test status
Simulation time 168027972348 ps
CPU time 93.11 seconds
Started Aug 14 05:17:28 PM PDT 24
Finished Aug 14 05:19:01 PM PDT 24
Peak memory 202112 kb
Host smart-0cc38419-30c0-4e13-8ab2-3dd60b8a2666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742370006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1742370006
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.4027367379
Short name T781
Test name
Test status
Simulation time 495745447260 ps
CPU time 1104.14 seconds
Started Aug 14 05:17:29 PM PDT 24
Finished Aug 14 05:35:53 PM PDT 24
Peak memory 202164 kb
Host smart-95370f7b-20e1-46cb-82d0-19f6f212036d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027367379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.4027367379
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.140237806
Short name T153
Test name
Test status
Simulation time 170465666685 ps
CPU time 405.97 seconds
Started Aug 14 05:17:29 PM PDT 24
Finished Aug 14 05:24:15 PM PDT 24
Peak memory 202180 kb
Host smart-63bcaa0a-3c9c-4fd1-b916-33705744b474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140237806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.140237806
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.839495996
Short name T752
Test name
Test status
Simulation time 499032680847 ps
CPU time 545.12 seconds
Started Aug 14 05:17:29 PM PDT 24
Finished Aug 14 05:26:34 PM PDT 24
Peak memory 202256 kb
Host smart-36b0c0c3-4be8-416d-a9bb-cd3992d4a6a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=839495996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.839495996
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3353995115
Short name T775
Test name
Test status
Simulation time 191410113376 ps
CPU time 108.65 seconds
Started Aug 14 05:17:28 PM PDT 24
Finished Aug 14 05:19:17 PM PDT 24
Peak memory 202128 kb
Host smart-e0c41e90-2cf7-455a-8d02-b6785c73a413
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353995115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3353995115
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3736659303
Short name T55
Test name
Test status
Simulation time 409390587533 ps
CPU time 471.98 seconds
Started Aug 14 05:17:29 PM PDT 24
Finished Aug 14 05:25:22 PM PDT 24
Peak memory 202120 kb
Host smart-ec6c564c-1160-434b-81c9-7554d1f35441
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736659303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3736659303
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3964905585
Short name T654
Test name
Test status
Simulation time 122990156565 ps
CPU time 658.68 seconds
Started Aug 14 05:17:33 PM PDT 24
Finished Aug 14 05:28:32 PM PDT 24
Peak memory 202460 kb
Host smart-64be8b2b-7a41-4f75-8574-57bbe4734dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964905585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3964905585
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3542898485
Short name T592
Test name
Test status
Simulation time 27774837775 ps
CPU time 63.78 seconds
Started Aug 14 05:17:35 PM PDT 24
Finished Aug 14 05:18:39 PM PDT 24
Peak memory 201964 kb
Host smart-df2eb0da-aee7-434e-92e7-2b57ab7d5f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542898485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3542898485
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3240593997
Short name T635
Test name
Test status
Simulation time 3806198517 ps
CPU time 10.15 seconds
Started Aug 14 05:17:30 PM PDT 24
Finished Aug 14 05:17:41 PM PDT 24
Peak memory 201964 kb
Host smart-69a077f1-10d8-4d87-aa20-1165d14333df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240593997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3240593997
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3782248693
Short name T491
Test name
Test status
Simulation time 5620524022 ps
CPU time 7.7 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:17:40 PM PDT 24
Peak memory 201916 kb
Host smart-662f4799-4f0a-4ff0-934c-9f3e797764ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782248693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3782248693
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3591703740
Short name T301
Test name
Test status
Simulation time 169611788520 ps
CPU time 397.13 seconds
Started Aug 14 05:17:31 PM PDT 24
Finished Aug 14 05:24:09 PM PDT 24
Peak memory 202140 kb
Host smart-3caa7f34-1d34-438e-a24f-84db9c0f69a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591703740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3591703740
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.883158149
Short name T305
Test name
Test status
Simulation time 5111990496 ps
CPU time 5.49 seconds
Started Aug 14 05:17:37 PM PDT 24
Finished Aug 14 05:17:43 PM PDT 24
Peak memory 202084 kb
Host smart-912539b3-475f-4314-aa80-77cd883b05ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883158149 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.883158149
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1678963642
Short name T661
Test name
Test status
Simulation time 538902973 ps
CPU time 0.91 seconds
Started Aug 14 05:17:34 PM PDT 24
Finished Aug 14 05:17:35 PM PDT 24
Peak memory 201952 kb
Host smart-bcb9f3a0-6c61-44a9-93c8-14939b59699c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678963642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1678963642
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1092864510
Short name T292
Test name
Test status
Simulation time 520824148458 ps
CPU time 577.93 seconds
Started Aug 14 05:17:34 PM PDT 24
Finished Aug 14 05:27:13 PM PDT 24
Peak memory 202116 kb
Host smart-420409a1-b6e9-4979-a846-215a21ab8716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092864510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1092864510
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.4220549419
Short name T440
Test name
Test status
Simulation time 336001473867 ps
CPU time 364.22 seconds
Started Aug 14 05:17:30 PM PDT 24
Finished Aug 14 05:23:35 PM PDT 24
Peak memory 202132 kb
Host smart-0f5a4306-834d-4b95-a994-843bd8ff4580
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220549419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.4220549419
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2859765243
Short name T690
Test name
Test status
Simulation time 168510307771 ps
CPU time 338.47 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:23:11 PM PDT 24
Peak memory 202148 kb
Host smart-ddf867e9-2f3c-44f5-9789-c486e7202f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859765243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2859765243
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1135579980
Short name T195
Test name
Test status
Simulation time 336374832723 ps
CPU time 166.81 seconds
Started Aug 14 05:17:30 PM PDT 24
Finished Aug 14 05:20:17 PM PDT 24
Peak memory 202116 kb
Host smart-a1e3b9f8-14d3-4e54-8907-c281f4b14fcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135579980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1135579980
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3511344751
Short name T338
Test name
Test status
Simulation time 188745529697 ps
CPU time 224.02 seconds
Started Aug 14 05:17:30 PM PDT 24
Finished Aug 14 05:21:14 PM PDT 24
Peak memory 202100 kb
Host smart-513ac9e0-0ace-4949-ba2e-25d356f0f054
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511344751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3511344751
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1703170192
Short name T497
Test name
Test status
Simulation time 199684302576 ps
CPU time 333.08 seconds
Started Aug 14 05:17:30 PM PDT 24
Finished Aug 14 05:23:04 PM PDT 24
Peak memory 202040 kb
Host smart-66239f17-2490-4c8b-bd0e-4829320be95b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703170192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1703170192
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2378687366
Short name T375
Test name
Test status
Simulation time 101279511342 ps
CPU time 358.66 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:23:31 PM PDT 24
Peak memory 202388 kb
Host smart-7e79029b-458c-4c0e-a860-53c1f0675b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378687366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2378687366
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2850812833
Short name T608
Test name
Test status
Simulation time 37838192142 ps
CPU time 24.56 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:17:56 PM PDT 24
Peak memory 201960 kb
Host smart-54076fa9-5616-4ad1-980d-2e77bcab6668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850812833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2850812833
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3841116095
Short name T112
Test name
Test status
Simulation time 5204433706 ps
CPU time 7.14 seconds
Started Aug 14 05:17:34 PM PDT 24
Finished Aug 14 05:17:41 PM PDT 24
Peak memory 201976 kb
Host smart-1966e43c-24e8-43fe-9e7d-6fabf51c50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841116095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3841116095
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.494930785
Short name T617
Test name
Test status
Simulation time 6140217352 ps
CPU time 4.37 seconds
Started Aug 14 05:17:30 PM PDT 24
Finished Aug 14 05:17:35 PM PDT 24
Peak memory 201992 kb
Host smart-77609fd4-bd1e-485a-abd5-173485066f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494930785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.494930785
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.495237432
Short name T641
Test name
Test status
Simulation time 344618393 ps
CPU time 0.84 seconds
Started Aug 14 05:17:43 PM PDT 24
Finished Aug 14 05:17:45 PM PDT 24
Peak memory 201984 kb
Host smart-1e23cd6e-d778-45b8-b0c4-5b159ae17759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495237432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.495237432
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2183853520
Short name T56
Test name
Test status
Simulation time 169101532646 ps
CPU time 39.29 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:18:11 PM PDT 24
Peak memory 202168 kb
Host smart-1f185d0c-589a-4de7-b883-f4956f40b9e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183853520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2183853520
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1448502591
Short name T696
Test name
Test status
Simulation time 167687353880 ps
CPU time 399.99 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:24:12 PM PDT 24
Peak memory 202168 kb
Host smart-2125278a-c1fc-416a-8d27-d560bdc25153
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448502591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1448502591
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2401279063
Short name T113
Test name
Test status
Simulation time 491671757691 ps
CPU time 178.6 seconds
Started Aug 14 05:17:33 PM PDT 24
Finished Aug 14 05:20:31 PM PDT 24
Peak memory 202076 kb
Host smart-4eed2468-a793-4d46-ab2f-173cbea3e9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401279063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2401279063
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2043452907
Short name T639
Test name
Test status
Simulation time 162478973326 ps
CPU time 373.58 seconds
Started Aug 14 05:17:31 PM PDT 24
Finished Aug 14 05:23:44 PM PDT 24
Peak memory 202064 kb
Host smart-4da2c63e-7c65-42f4-9b4a-1fdd499602e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043452907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2043452907
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4074571995
Short name T566
Test name
Test status
Simulation time 364115156843 ps
CPU time 794.45 seconds
Started Aug 14 05:17:32 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 202152 kb
Host smart-de2ad8b6-deda-417f-b820-4bc618e2f88d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074571995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4074571995
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3139407371
Short name T451
Test name
Test status
Simulation time 197850371744 ps
CPU time 253.9 seconds
Started Aug 14 05:17:31 PM PDT 24
Finished Aug 14 05:21:45 PM PDT 24
Peak memory 202128 kb
Host smart-53a55cf6-346f-48c9-abda-2bc4b6de0a74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139407371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3139407371
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1722865949
Short name T235
Test name
Test status
Simulation time 115066355226 ps
CPU time 613.7 seconds
Started Aug 14 05:17:43 PM PDT 24
Finished Aug 14 05:27:58 PM PDT 24
Peak memory 202408 kb
Host smart-1fad9dbd-5296-45e7-b847-39783f72b0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722865949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1722865949
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3671022653
Short name T414
Test name
Test status
Simulation time 41122153951 ps
CPU time 92.53 seconds
Started Aug 14 05:17:44 PM PDT 24
Finished Aug 14 05:19:17 PM PDT 24
Peak memory 201960 kb
Host smart-479d6a8d-ed26-410a-bb17-5b2800841e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671022653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3671022653
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2620172361
Short name T399
Test name
Test status
Simulation time 3467940177 ps
CPU time 2.64 seconds
Started Aug 14 05:17:43 PM PDT 24
Finished Aug 14 05:17:46 PM PDT 24
Peak memory 201956 kb
Host smart-784b0a7b-9cc9-4799-bca9-fb13c292f262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620172361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2620172361
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3146199904
Short name T510
Test name
Test status
Simulation time 6036147745 ps
CPU time 8.19 seconds
Started Aug 14 05:17:30 PM PDT 24
Finished Aug 14 05:17:39 PM PDT 24
Peak memory 201912 kb
Host smart-63508486-b7de-4630-b2e9-42e43b1084ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146199904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3146199904
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.4293517910
Short name T402
Test name
Test status
Simulation time 1216167932 ps
CPU time 2.01 seconds
Started Aug 14 05:17:43 PM PDT 24
Finished Aug 14 05:17:45 PM PDT 24
Peak memory 201968 kb
Host smart-7186f5c3-ef65-4416-9c8e-93680a0291b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293517910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
4293517910
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.515535138
Short name T503
Test name
Test status
Simulation time 4388644471 ps
CPU time 6.04 seconds
Started Aug 14 05:17:42 PM PDT 24
Finished Aug 14 05:17:48 PM PDT 24
Peak memory 210544 kb
Host smart-cddf343c-f4ee-4904-9c4c-1f176bea7ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515535138 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.515535138
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1074723453
Short name T689
Test name
Test status
Simulation time 502638628 ps
CPU time 1.7 seconds
Started Aug 14 05:17:51 PM PDT 24
Finished Aug 14 05:17:52 PM PDT 24
Peak memory 201964 kb
Host smart-cc607685-6036-4fe2-817e-786051618c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074723453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1074723453
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3635358776
Short name T346
Test name
Test status
Simulation time 164024739431 ps
CPU time 92.77 seconds
Started Aug 14 05:17:44 PM PDT 24
Finished Aug 14 05:19:17 PM PDT 24
Peak memory 202128 kb
Host smart-39897dd4-72a9-43eb-be1f-7f6aa6fe45b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635358776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3635358776
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1421499582
Short name T224
Test name
Test status
Simulation time 334034597646 ps
CPU time 134.44 seconds
Started Aug 14 05:17:43 PM PDT 24
Finished Aug 14 05:19:58 PM PDT 24
Peak memory 202192 kb
Host smart-cb0f469d-c680-4e03-8ba4-a4da12e81511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421499582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1421499582
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3986006892
Short name T789
Test name
Test status
Simulation time 489301053004 ps
CPU time 304.23 seconds
Started Aug 14 05:17:45 PM PDT 24
Finished Aug 14 05:22:49 PM PDT 24
Peak memory 202120 kb
Host smart-e583df67-716b-4f1e-bfdf-1a47ac609d29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986006892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3986006892
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3768796748
Short name T329
Test name
Test status
Simulation time 493939656907 ps
CPU time 1111.71 seconds
Started Aug 14 05:17:43 PM PDT 24
Finished Aug 14 05:36:16 PM PDT 24
Peak memory 202312 kb
Host smart-d690455a-83f5-422d-a34c-837894523c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768796748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3768796748
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2417607274
Short name T741
Test name
Test status
Simulation time 324891054172 ps
CPU time 770.56 seconds
Started Aug 14 05:17:41 PM PDT 24
Finished Aug 14 05:30:32 PM PDT 24
Peak memory 202120 kb
Host smart-a6b7da27-6bed-432a-955b-3354d29b0607
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417607274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2417607274
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3986186820
Short name T361
Test name
Test status
Simulation time 543454919398 ps
CPU time 1214.43 seconds
Started Aug 14 05:17:42 PM PDT 24
Finished Aug 14 05:37:57 PM PDT 24
Peak memory 202120 kb
Host smart-5e3324e7-56db-4803-97a3-5a9519ea42fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986186820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3986186820
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.796927891
Short name T796
Test name
Test status
Simulation time 602737370849 ps
CPU time 370.74 seconds
Started Aug 14 05:17:43 PM PDT 24
Finished Aug 14 05:23:54 PM PDT 24
Peak memory 202136 kb
Host smart-a1a919b8-0a0b-4243-b9f8-28478a0eeacd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796927891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.796927891
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4051044008
Short name T692
Test name
Test status
Simulation time 38119637932 ps
CPU time 23.19 seconds
Started Aug 14 05:17:43 PM PDT 24
Finished Aug 14 05:18:07 PM PDT 24
Peak memory 201960 kb
Host smart-fa746640-7f89-4c64-a40d-86db14ccb472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051044008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4051044008
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1412905590
Short name T735
Test name
Test status
Simulation time 3080823768 ps
CPU time 2.65 seconds
Started Aug 14 05:17:42 PM PDT 24
Finished Aug 14 05:17:45 PM PDT 24
Peak memory 201964 kb
Host smart-0208dcdb-c07c-4c10-86e0-1d4edbcbefa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412905590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1412905590
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.109334958
Short name T434
Test name
Test status
Simulation time 6015028068 ps
CPU time 4.88 seconds
Started Aug 14 05:17:42 PM PDT 24
Finished Aug 14 05:17:47 PM PDT 24
Peak memory 201992 kb
Host smart-da3c49a6-5933-410d-90e5-34e5e854e589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109334958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.109334958
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2979024661
Short name T240
Test name
Test status
Simulation time 384948477331 ps
CPU time 357.61 seconds
Started Aug 14 05:17:49 PM PDT 24
Finished Aug 14 05:23:47 PM PDT 24
Peak memory 202180 kb
Host smart-3a79698b-fb70-4ea6-a5d1-23ec802b5de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979024661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2979024661
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1631901842
Short name T259
Test name
Test status
Simulation time 5517130628 ps
CPU time 7.73 seconds
Started Aug 14 05:17:49 PM PDT 24
Finished Aug 14 05:17:57 PM PDT 24
Peak memory 211548 kb
Host smart-1156128c-e710-4051-bdd2-31a866612f6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631901842 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1631901842
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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