Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5591	1			T1	4		T6	37		T8	6
testmodes[AdcCtrlTestmodeNormal]	4783	1			T1	7		T3	3		T4	2
testmodes[AdcCtrlTestmodeLowpower]	4819	1			T2	3		T5	1		T6	44
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2887	1			T1	1		T6	10		T8	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1472	1			T1	3		T6	14		T8	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1114	1			T6	13		T11	1		T37	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1486	1			T1	3		T6	11		T8	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1765	1			T1	3		T3	2		T4	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1194	1			T5	1		T6	17		T37	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1099	1			T6	15		T23	1		T37	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1209	1			T6	14		T11	1		T37	14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2267	1			T2	2		T6	14		T22	2