Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19782

1

T1

15

T2

13

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3114

1

T2

14

T4

12

T5

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16994

1

T1

11

T2

9

T4

12

auto[1]

5902

1

T1

4

T2

18

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	262	1			T35	1		T135	1		T136	1
values[1]	446	1			T5	2		T12	3		T134	1
values[2]	803	1			T1	4		T2	27		T5	32
values[3]	656	1			T5	13		T8	1		T154	35
values[4]	651	1			T22	7		T29	20		T36	25
values[5]	3004	1			T3	37		T4	15		T12	1
values[6]	624	1			T4	12		T8	1		T29	2
values[7]	748	1			T7	1		T22	18		T124	5
values[8]	618	1			T36	18		T127	9		T152	22
values[9]	757	1			T10	4		T11	4		T12	9
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	631	1			T2	4		T12	3		T134	1
values[1]	627	1			T1	4		T2	23		T5	32
values[2]	727	1			T5	13		T8	1		T136	1
values[3]	2878	1			T3	37		T22	7		T24	24
values[4]	693	1			T4	15		T12	1		T170	17
values[5]	700	1			T4	12		T8	1		T29	2
values[6]	727	1			T7	1		T22	18		T124	5
values[7]	553	1			T10	4		T35	5		T36	18
values[8]	725	1			T11	4		T12	9		T22	15
values[9]	170	1			T127	3		T150	31		T213	1
minimum	14465	1			T1	11		T5	2		T6	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	4		T12	1		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T125	18		T128	1		T133	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	3		T2	9		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	14		T5	16		T30	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	7		T146	8		T187	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	1		T136	1		T154	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T3	3		T22	7		T24	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	10		T124	18		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	1		T214	1		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	1		T170	17		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T29	1		T170	12		T144	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	1		T8	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T215	1		T144	9		T216	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	1		T22	18		T124	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	1		T35	5		T36	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T125	13		T127	1		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	1		T23	22		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	3		T22	15		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T150	15		T217	16		T218	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T127	1		T213	1		T219	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14286	1			T1	9		T6	125		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T5	1		T131	8		T220	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	2		T154	4		T221	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T125	21		T190	12		T222	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	1		T125	11		T165	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	16		T30	5		T129	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	6		T146	7		T151	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T154	18		T221	9		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T3	34		T28	9		T36	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	10		T124	17		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	14		T18	1		T138	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T152	12		T143	5		T150	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T29	1		T144	6		T129	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	11		T223	11		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T216	1		T160	2		T225	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T130	18		T167	5		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	3		T36	7		T226	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T125	7		T127	8		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	8		T127	2		T221	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	1		T31	1		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T150	16		T218	10		T227	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T127	2		T219	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T8	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T5	1		T220	8		T228	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T135	1		T137	1		T150	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T35	1		T136	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T134	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T5	1		T125	8		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	3		T2	13		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	14		T5	16		T30	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	7		T187	11		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	1		T154	17		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T22	7		T36	14		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T29	10		T124	18		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T3	3		T4	1		T24	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	1		T30	1		T170	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T29	1		T170	12		T144	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	1		T8	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T215	1		T144	9		T231	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	1		T22	18		T124	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T36	11		T226	1		T187	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T127	1		T152	12		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	1		T12	1		T23	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	3		T22	15		T232	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T150	16		T218	10		T178	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T233	11		T234	1		T219	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	2		T154	13		T165	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T5	1		T125	9		T225	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T125	11		T154	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	16		T30	5		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	6		T151	18		T235	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T154	18		T221	9		T129	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T36	11		T146	7		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T29	10		T124	17		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T3	34		T4	14		T28	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T152	12		T143	5		T150	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T29	1		T144	6		T129	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	11		T223	11		T237	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T231	6		T216	1		T236	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T130	18		T167	5		T97	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	7		T226	10		T225	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T127	8		T152	10		T132	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T10	3		T12	8		T127	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	1		T125	7		T127	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T12	3		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T125	23		T128	1		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	3		T2	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	1		T5	17		T30	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	7		T146	8		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	1		T136	1		T154	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T3	37		T22	1		T24	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	11		T124	19		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	15		T214	1		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T170	1		T152	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T29	2		T170	1		T144	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	12		T8	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T215	1		T144	1		T216	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	1		T22	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	4		T35	1		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T125	8		T127	9		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	9		T23	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	3		T22	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T150	17		T217	1		T218	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T127	3		T213	1		T219	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14395	1			T1	11		T6	125		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T5	2		T131	1		T220	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	3		T154	14		T238	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T125	16		T133	23		T190	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T2	8		T125	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	13		T5	15		T30	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	6		T146	7		T187	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T154	16		T145	11		T239	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T22	6		T24	22		T36	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	9		T124	16		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T18	1		T240	13		T217	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T170	16		T152	7		T143	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T170	11		T144	3		T89	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T133	4		T233	9		T235	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T144	8		T216	1		T241	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	17		T124	4		T196	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	4		T36	10		T187	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T125	12		T152	10		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T23	21		T13	1		T239	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	1		T22	14		T232	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T150	14		T217	15		T218	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T219	15		T242	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T154	6		T147	2		T96	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T131	7		T228	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T135	1		T137	1		T150	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T35	1		T136	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	3		T134	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T5	2		T125	10		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	3		T2	2		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T5	17		T30	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	7		T187	1		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T154	19		T221	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T22	1		T36	12		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	11		T124	19		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T3	37		T4	15		T24	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T30	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T29	2		T170	1		T144	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	12		T8	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T215	1		T144	1		T231	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T7	1		T22	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	8		T226	11		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T127	9		T152	12		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	4		T12	9		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	3		T22	1		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T150	14		T218	8		T243	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T233	12		T219	15		T244	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T154	6		T146	7		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T125	7		T131	7		T245	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T2	11		T125	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	13		T5	15		T30	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	6		T187	10		T151	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T154	16		T239	17		T241	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T22	6		T36	13		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	9		T124	16		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T24	22		T246	36		T195	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T170	16		T152	7		T143	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T170	11		T144	3		T89	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T133	4		T235	2		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T144	8		T231	6		T216	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	17		T124	4		T196	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T36	10		T187	13		T247	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T152	10		T16	1		T248	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T23	21		T35	4		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	1		T22	14		T232	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19804

1

T1

15

T2

9

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3092

1

T2

18

T4

12

T5

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17005

1

T1

11

T2

9

T4

12

auto[1]

5891

1

T1

4

T2

18

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	32	1			T219	32		-	-		-	-
values[0]	36	1			T169	1		T249	15		T250	20
values[1]	446	1			T1	4		T5	2		T12	3
values[2]	753	1			T2	27		T5	32		T136	1
values[3]	691	1			T5	13		T8	1		T125	26
values[4]	614	1			T22	7		T29	20		T36	25
values[5]	2996	1			T3	37		T4	15		T12	1
values[6]	727	1			T4	12		T8	1		T29	2
values[7]	653	1			T7	1		T22	18		T215	1
values[8]	619	1			T22	15		T36	18		T127	9
values[9]	1002	1			T10	4		T11	4		T12	9
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	724	1			T2	4		T5	2		T12	3
values[1]	654	1			T1	4		T2	23		T5	32
values[2]	721	1			T5	13		T136	1		T30	19
values[3]	2957	1			T3	37		T22	7		T24	24
values[4]	615	1			T4	15		T12	1		T170	17
values[5]	655	1			T4	12		T8	1		T29	2
values[6]	840	1			T7	1		T22	18		T124	5
values[7]	496	1			T10	4		T35	5		T36	18
values[8]	683	1			T11	4		T12	9		T22	15
values[9]	224	1			T137	1		T127	3		T150	31
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	1		T134	1		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	4		T5	1		T125	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	3		T2	9		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	14		T5	16		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	7		T146	8		T187	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T136	1		T30	14		T154	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T3	3		T24	24		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T22	7		T29	10		T124	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	1		T89	4		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	1		T170	17		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	1		T29	1		T170	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	1		T133	5		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T226	1		T215	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	1		T22	18		T124	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T10	1		T35	5		T36	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T125	13		T127	1		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	1		T23	22		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	3		T22	15		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T137	1		T251	4		T217	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T127	1		T150	15		T158	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	2		T154	17		T165	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T125	21		T221	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	1		T125	11		T165	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	16		T129	12		T167	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	6		T146	7		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T30	5		T154	18		T221	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T3	34		T28	9		T36	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T29	10		T124	17		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	14		T89	1		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T152	12		T143	5		T150	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T29	1		T144	6		T129	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	11		T223	11		T224	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T226	10		T216	1		T160	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T130	18		T167	5		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	3		T36	7		T240	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T125	7		T127	8		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	8		T127	2		T143	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	1		T31	1		T150	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T251	1		T252	4		T218	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T127	2		T150	16		T158	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T219	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T169	1		T249	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T250	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	3		T12	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T5	1		T125	8		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	9		T136	1		T154	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	18		T5	16		T30	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	7		T125	15		T187	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T221	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	14		T153	1		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	7		T29	10		T124	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T3	3		T4	1		T24	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T170	17		T152	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	1		T29	1		T170	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	1		T124	5		T133	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T215	1		T144	9		T216	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	1		T22	18		T130	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T36	11		T226	1		T187	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T22	15		T127	1		T152	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T10	1		T12	1		T23	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	3		T35	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T219	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T249	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T250	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	1		T12	2		T154	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	1		T125	9		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T154	4		T253	8		T190	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	16		T30	5		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	6		T125	11		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T221	9		T129	12		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	11		T146	7		T159	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T29	10		T124	17		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T3	34		T4	14		T28	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T152	12		T143	15		T150	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T29	1		T144	6		T129	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	11		T223	11		T237	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T216	1		T236	7		T254	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T130	18		T167	5		T97	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T36	7		T226	10		T240	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T127	8		T152	10		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T10	3		T12	8		T127	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	1		T125	7		T127	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1