Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17102

1

T1

11

T2

13

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

5794

1

T1

4

T2

14

T3

37

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16908

1

T1

15

T2

4

T5

15

auto[1]

5988

1

T2

23

T3

37

T4

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T206	13		T276	1		-	-
values[0]	90	1			T190	25		T219	20		T210	13
values[1]	751	1			T1	4		T8	1		T10	4
values[2]	468	1			T36	25		T136	1		T152	9
values[3]	822	1			T2	4		T5	13		T23	22
values[4]	707	1			T4	12		T22	18		T29	2
values[5]	554	1			T11	4		T12	3		T35	5
values[6]	589	1			T2	14		T12	9		T125	43
values[7]	602	1			T5	34		T7	1		T12	1
values[8]	510	1			T2	9		T8	1		T226	11
values[9]	3462	1			T3	37		T4	15		T22	22
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	948	1			T1	4		T8	1		T10	4
values[1]	2982	1			T3	37		T5	13		T24	24
values[2]	723	1			T2	4		T23	22		T29	20
values[3]	708	1			T4	12		T11	4		T22	18
values[4]	516	1			T12	3		T35	5		T136	1
values[5]	523	1			T2	14		T12	10		T134	1
values[6]	628	1			T2	9		T5	34		T7	1
values[7]	619	1			T4	15		T8	1		T22	15
values[8]	688	1			T22	7		T232	8		T136	1
values[9]	217	1			T287	6		T151	28		T224	8
minimum	14344	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T36	11		T136	1		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T1	3		T8	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	7		T31	2		T154	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1576	1			T3	3		T24	24		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	4		T23	22		T32	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T29	10		T124	5		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	3		T22	18		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	1		T89	4		T97	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T35	5		T30	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T136	1		T127	1		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T152	8		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	14		T12	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	9		T5	1		T124	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	16		T7	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T35	1		T226	1		T238	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	1		T8	1		T22	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T22	7		T170	8		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T232	8		T136	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T224	1		T258	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T287	5		T151	16		T139	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14241	1			T1	9		T6	125		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T18	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T36	7		T34	1		T212	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T1	1		T10	3		T152	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	6		T31	1		T154	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1118	1			T3	34		T28	9		T36	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T221	4		T129	3		T130	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T29	10		T127	2		T151	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	1		T29	1		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	11		T89	1		T97	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	2		T30	5		T125	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T127	8		T152	3		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	8		T152	12		T264	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T125	9		T267	1		T251	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T124	16		T125	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	16		T124	1		T143	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T226	10		T129	12		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	14		T150	16		T231	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T221	9		T146	7		T224	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T150	7		T151	1		T222	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T224	7		T261	16		T304	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T287	1		T151	12		T278	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T1	2		T8	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T18	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T206	1		T276	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T190	13		T324	1		T321	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T219	9		T210	12		T325	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T36	11		T34	1		T212	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T1	3		T8	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T136	1		T154	17		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T36	14		T152	2		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	4		T5	7		T23	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T29	10		T124	5		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T22	18		T29	1		T125	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	1		T127	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	3		T12	1		T35	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	1		T144	9		T145	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T125	15		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	14		T125	8		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	1		T35	1		T124	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	16		T7	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	9		T226	1		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	1		T128	1		T150	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T22	7		T170	8		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1742	1			T3	3		T4	1		T22	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T206	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T190	12		T321	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T219	11		T210	1		T325	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T36	7		T34	1		T212	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T10	3		T143	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T154	18		T130	10		T288	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T36	11		T152	7		T326	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	6		T127	2		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	10		T127	2		T154	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T29	1		T125	12		T154	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	11		T127	8		T89	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T11	1		T12	2		T30	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	11		T165	14		T97	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	8		T125	11		T132	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T125	9		T152	3		T267	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	1		T124	16		T125	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	16		T124	1		T143	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T226	10		T129	12		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T150	16		T236	12		T240	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T221	9		T146	7		T224	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1198	1			T3	34		T4	14		T28	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T36	8		T136	1		T34	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T1	3		T8	1		T10	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	7		T31	2		T154	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1448	1			T3	37		T24	2		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	1		T23	1		T32	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T29	11		T124	1		T127	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	3		T22	1		T29	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	12		T89	4		T97	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	3		T35	1		T30	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T136	1		T127	9		T152	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	9		T152	13		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	1		T12	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	1		T5	2		T124	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	17		T7	1		T124	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T35	1		T226	11		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	15		T8	1		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T22	1		T170	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T232	1		T136	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T224	8		T258	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T287	4		T151	13		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14335	1			T1	11		T6	125		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T18	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T36	10		T212	8		T247	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T1	1		T152	1		T143	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	6		T31	1		T154	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1246	1			T24	22		T36	13		T246	36
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	3		T23	21		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T29	9		T124	4		T151	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	1		T22	17		T125	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T89	1		T97	9		T216	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T35	4		T30	13		T125	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T152	9		T144	8		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T152	7		T16	1		T269	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T2	13		T125	7		T267	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	8		T124	16		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	15		T143	10		T133	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T238	3		T147	2		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T22	14		T131	6		T150	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T22	6		T170	7		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T232	7		T196	25		T150	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T261	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T287	2		T151	15		T139	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T290	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T18	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T206	13		T276	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T190	13		T324	1		T321	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T219	12		T210	2		T325	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T36	8		T34	2		T212	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T1	3		T8	1		T10	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T136	1		T154	19		T130	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T36	12		T152	8		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T2	1		T5	7		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T29	11		T124	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T22	1		T29	2		T125	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	12		T127	9		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	3		T12	3		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T136	1		T144	1		T145	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	9		T125	12		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T125	10		T152	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	2		T35	1		T124	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	17		T7	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	1		T226	11		T129	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	1		T128	1		T150	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T22	1		T170	1		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1553	1			T3	37		T4	15		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T190	12		T321	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T219	8		T210	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T36	10		T212	8		T247	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T143	12		T146	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T154	16		T217	8		T272	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T36	13		T152	1		T274	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	3		T5	6		T23	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T29	9		T124	4		T170	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	17		T125	9		T154	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T89	1		T239	9		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	1		T35	4		T30	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T144	8		T145	11		T187	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T125	14		T150	10		T284	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	13		T125	7		T152	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T124	16		T125	12		T152	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	15		T143	10		T133	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T2	8		T147	2		T187	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T150	14		T236	14		T240	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T22	6		T170	7		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1387	1			T22	14		T24	22		T232	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21