Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19514

1

T1

11

T3

37

T5

32

auto[ADC_CTRL_FILTER_COND_OUT]

3382

1

T1

4

T2

27

T4

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17096

1

T1

11

T2

4

T6

125

auto[1]

5800

1

T1

4

T2

23

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	293	1			T10	4		T12	3		T22	7
values[0]	9	1			T152	9		-	-		-	-
values[1]	643	1			T29	2		T35	6		T36	25
values[2]	580	1			T1	4		T5	2		T12	1
values[3]	529	1			T136	1		T127	3		T153	1
values[4]	3015	1			T2	4		T3	37		T7	1
values[5]	596	1			T4	12		T22	18		T31	3
values[6]	794	1			T2	14		T4	15		T5	45
values[7]	470	1			T152	20		T226	11		T154	20
values[8]	683	1			T2	9		T11	4		T23	22
values[9]	957	1			T12	9		T124	33		T125	48
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	582	1			T29	2		T35	1		T36	25
values[1]	572	1			T1	4		T5	2		T12	1
values[2]	512	1			T7	1		T136	2		T154	19
values[3]	3033	1			T2	4		T3	37		T24	24
values[4]	625	1			T4	12		T8	1		T22	18
values[5]	731	1			T2	14		T4	15		T5	45
values[6]	494	1			T2	9		T36	18		T152	20
values[7]	751	1			T11	4		T12	9		T23	22
values[8]	875	1			T10	4		T12	3		T124	40
values[9]	147	1			T22	7		T153	1		T128	1
minimum	14574	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T29	1		T35	1		T36	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T135	1		T125	8		T32	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T136	1		T30	14		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	3		T5	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T7	1		T136	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T136	1		T154	15		T196	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T3	3		T24	24		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	4		T127	1		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	1		T143	11		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	1		T22	18		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	16		T8	1		T144	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	14		T4	1		T5	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T152	8		T226	1		T154	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	9		T36	11		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T23	22		T127	1		T238	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	3		T12	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	1		T124	22		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	1		T124	1		T232	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T22	7		T216	4		T247	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T153	1		T128	1		T282	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14302	1			T1	9		T6	125		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T170	17		T144	9		T327	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	1		T36	11		T125	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T125	9		T231	9		T253	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T30	5		T150	1		T73	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T5	1		T130	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T167	5		T89	1		T294	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T154	4		T231	6		T299	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T3	34		T28	9		T180	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	2		T31	1		T221	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T143	10		T146	7		T224	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	11		T29	10		T190	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	16		T144	6		T129	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	14		T5	6		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T152	12		T226	10		T154	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T36	7		T240	12		T288	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T127	8		T130	10		T165	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	1		T12	8		T127	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	2		T124	16		T125	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	3		T124	1		T125	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T216	1		T318	13		T301	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T282	13		T302	1		T328	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	2		T8	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T290	7		T329	13		T305	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	1		T22	7		T124	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T10	1		T124	1		T232	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T152	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T29	1		T35	6		T36	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T125	8		T170	17		T144	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T136	1		T30	14		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	3		T5	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T153	1		T128	1		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T136	1		T127	1		T154	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T3	3		T7	1		T24	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	4		T31	1		T151	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T143	11		T128	1		T187	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	1		T22	18		T31	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	16		T8	2		T144	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	14		T4	1		T5	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T152	8		T226	1		T154	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T133	13		T223	1		T330	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T23	22		T127	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	9		T11	3		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T124	17		T125	15		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T12	1		T125	10		T170	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T12	2		T216	1		T326	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T10	3		T124	1		T132	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T152	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T29	1		T36	11		T125	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T125	9		T231	9		T233	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T30	5		T150	1		T206	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T5	1		T167	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T167	5		T89	1		T192	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T127	2		T154	4		T130	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T3	34		T28	9		T180	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T151	6		T224	14		T231	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T143	10		T34	1		T224	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	11		T31	1		T221	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	16		T144	6		T129	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	14		T5	6		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T152	12		T226	10		T154	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T223	9		T156	8		T278	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T127	8		T154	18		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	1		T36	7		T127	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T124	16		T125	11		T167	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	8		T125	12		T152	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	2		T35	1		T36	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T135	1		T125	10		T32	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T136	1		T30	6		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	3		T5	2		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T7	1		T136	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T136	1		T154	5		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T3	37		T24	2		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T127	3		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	1		T143	11		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	12		T22	1		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	17		T8	1		T144	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	1		T4	15		T5	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T152	13		T226	11		T154	33
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	1		T36	8		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T23	1		T127	9		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	3		T12	9		T127	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T12	3		T124	18		T125	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	4		T124	2		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T22	1		T216	4		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T153	1		T128	1		T282	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14389	1			T1	11		T6	125		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T170	1		T144	1		T327	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T36	13		T125	12		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T125	7		T131	7		T231	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T30	13		T150	10		T73	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	1		T97	9		T197	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T89	1		T294	4		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T154	14		T196	25		T133	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T24	22		T246	36		T170	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	3		T31	1		T151	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T143	10		T146	7		T187	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T22	17		T29	9		T190	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	15		T144	3		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	13		T5	6		T22	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T152	7		T154	22		T219	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	8		T36	10		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T23	21		T238	3		T146	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	1		T287	2		T212	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T124	20		T125	14		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T232	7		T125	9		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T22	6		T216	1		T247	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T302	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T35	4		T174	10		T236	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T170	16		T144	8		T327	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	3		T22	1		T124	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T10	4		T124	2		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T152	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	2		T35	2		T36	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T125	10		T170	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T136	1		T30	6		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	3		T5	2		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T153	1		T128	1		T167	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T136	1		T127	3		T154	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T3	37		T7	1		T24	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T31	1		T151	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T143	11		T128	1		T187	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	12		T22	1		T31	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	17		T8	2		T144	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T4	15		T5	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T152	13		T226	11		T154	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	1		T223	10		T330	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T23	1		T127	9		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T11	3		T36	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T124	17		T125	12		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T12	9		T125	13		T170	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T22	6		T124	4		T216	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T232	7		T217	8		T160	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T152	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T35	4		T36	13		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T125	7		T170	16		T144	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T30	13		T155	11		T150	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	1		T197	1		T217	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T89	1		T141	2		T331	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T154	14		T196	25		T133	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T24	22		T246	36		T170	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	3		T151	8		T239	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T143	10		T187	13		T236	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T22	17		T31	1		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	15		T144	3		T146	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	13		T5	6		T22	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T152	7		T154	6		T219	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T133	12		T278	2		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T23	21		T154	16		T146	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	8		T11	1		T36	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T124	16		T125	14		T238	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T125	9		T170	11		T152	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21