Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19794

1

T1

15

T2

9

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3102

1

T2

18

T8

1

T10

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17255

1

T1

11

T2

9

T4

12

auto[1]

5641

1

T1

4

T2

18

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	310	1			T153	1		T226	11		T154	55
values[0]	47	1			T4	12		T128	1		T333	12
values[1]	687	1			T2	4		T124	40		T30	20
values[2]	658	1			T11	4		T125	39		T137	1
values[3]	528	1			T5	32		T35	5		T134	1
values[4]	568	1			T29	20		T232	8		T127	3
values[5]	540	1			T2	9		T4	15		T5	2
values[6]	734	1			T5	13		T8	1		T10	4
values[7]	644	1			T12	3		T22	33		T23	22
values[8]	708	1			T2	14		T8	1		T12	1
values[9]	3145	1			T1	4		T3	37		T7	1
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	735	1			T2	4		T124	7		T30	1
values[1]	573	1			T134	1		T137	1		T215	1
values[2]	650	1			T5	32		T11	4		T29	20
values[3]	470	1			T29	2		T232	8		T127	3
values[4]	527	1			T2	9		T4	15		T5	15
values[5]	744	1			T8	1		T10	4		T12	3
values[6]	3252	1			T3	37		T12	1		T22	15
values[7]	497	1			T2	14		T8	1		T22	7
values[8]	824	1			T1	4		T125	20		T170	12
values[9]	121	1			T7	1		T12	9		T125	26
minimum	14503	1			T1	11		T4	12		T6	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T124	1		T153	1		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	4		T124	5		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T134	1		T154	15		T196	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T137	1		T215	1		T144	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	16		T11	3		T29	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T132	1		T230	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T29	1		T232	8		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T164	1		T130	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	9		T4	1		T5	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T129	2		T131	8		T146	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	1		T12	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	1		T22	18		T133	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T3	3		T12	1		T24	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T22	15		T23	22		T36	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T127	1		T170	17		T13	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	14		T8	1		T22	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	3		T125	13		T170	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T153	1		T143	8		T154	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T7	1		T12	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T125	15		T258	1		T264	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14250	1			T1	9		T4	1		T6	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T124	17		T30	14		T128	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T124	1		T150	16		T151	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T125	21		T222	9		T310	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T154	4		T97	1		T151	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T240	1		T156	8		T158	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	16		T11	1		T29	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T259	2		T260	2		T275	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	1		T127	2		T152	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T130	8		T167	10		T165	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	14		T5	7		T167	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T129	15		T146	7		T151	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	2		T165	14		T236	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	3		T224	21		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1140	1			T3	34		T28	9		T36	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T36	7		T152	3		T143	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T127	2		T97	17		T287	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T152	12		T145	11		T231	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T125	7		T143	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T143	5		T154	18		T144	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T12	8		T313	7		T334	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T125	11		T264	1		T192	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	2		T4	11		T8	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T124	16		T30	5		T150	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T226	1		T154	7		T99	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T153	1		T154	17		T144	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T4	1		T333	1		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T128	1		T265	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T124	1		T153	1		T32	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	4		T124	22		T30	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	3		T154	15		T16	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T125	18		T137	1		T133	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	16		T35	5		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T215	1		T144	9		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T29	10		T232	8		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T167	1		T132	1		T187	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	9		T4	1		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T164	1		T129	2		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	7		T8	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	1		T131	8		T224	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	1		T35	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T22	33		T23	22		T36	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T36	14		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	14		T8	1		T22	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T1	3		T3	3		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T125	15		T143	8		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T226	10		T154	13		T236	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T154	18		T144	6		T231	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T4	11		T333	11		T266	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T124	1		T150	16		T151	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T124	16		T30	5		T150	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	1		T154	4		T97	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T125	21		T240	1		T158	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	16		T221	4		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T156	8		T260	2		T275	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T29	10		T127	2		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T167	10		T132	5		T219	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	14		T5	1		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T129	15		T130	8		T165	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	6		T167	5		T236	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	3		T224	21		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	2		T127	8		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	7		T152	3		T240	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T36	11		T127	2		T287	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T152	12		T143	10		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T1	1		T3	34		T12	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T125	11		T143	5		T231	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T124	2		T153	1		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	1		T124	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T134	1		T154	5		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T137	1		T215	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	17		T11	3		T29	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T132	1		T230	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T29	2		T232	1		T127	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T164	1		T130	9		T167	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	1		T4	15		T5	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T129	17		T131	1		T146	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	1		T12	3		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	4		T22	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1477	1			T3	37		T12	1		T24	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T22	1		T23	1		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T127	3		T170	1		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T8	1		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	3		T125	8		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T153	1		T143	6		T154	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T7	1		T12	9		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T125	12		T258	1		T264	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14376	1			T1	11		T4	12		T6	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T124	17		T30	6		T128	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T16	1		T150	14		T151	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	3		T124	4		T125	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T154	14		T196	25		T151	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T144	8		T158	10		T235	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	15		T11	1		T29	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T217	13		T259	2		T245	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T232	7		T152	1		T131	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T187	10		T241	7		T219	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	8		T5	6		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T131	7		T146	7		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T187	13		T96	11		T239	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T22	17		T133	23		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T24	22		T36	13		T246	36
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T22	14		T23	21		T36	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T170	16		T13	1		T97	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T2	13		T22	6		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	1		T125	12		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T143	7		T154	16		T144	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T313	11		T334	9		T242	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T125	14		T290	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T252	7		T335	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T124	16		T30	13		T150	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T226	11		T154	14		T99	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T153	1		T154	19		T144	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T4	12		T333	12		T266	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T128	1		T265	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T124	2		T153	1		T32	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	1		T124	18		T30	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	3		T154	5		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T125	23		T137	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	17		T35	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T215	1		T144	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T29	11		T232	1		T127	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T167	11		T132	6		T187	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	1		T4	15		T5	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T164	1		T129	17		T130	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	7		T8	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	4		T131	1		T224	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	3		T35	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	2		T23	1		T36	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	1		T36	12		T127	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T8	1		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T1	3		T3	37		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T125	12		T143	6		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T154	6		T239	17		T236	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T154	16		T144	3		T231	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T265	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T150	14		T151	8		T240	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	3		T124	20		T30	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	1		T154	14		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T125	16		T133	4		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	15		T35	4		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T144	8		T217	8		T336	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	9		T232	7		T170	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T187	10		T217	5		T219	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	8		T267	1		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T146	7		T151	2		T241	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	6		T187	13		T96	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T131	7		T247	17		T190	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T31	1		T239	9		T216	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T22	31		T23	21		T36	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	13		T170	16		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	13		T22	6		T152	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T1	1		T24	22		T246	36
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T125	14		T143	7		T231	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21