Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19629

1

T1

11

T2

14

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3267

1

T1

4

T2

13

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17507

1

T1

11

T2

13

T4

12

auto[1]

5389

1

T1

4

T2

14

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	269	1			T22	18		T152	9		T145	23
values[0]	17	1			T128	1		T291	11		T292	5
values[1]	439	1			T8	1		T11	4		T125	22
values[2]	834	1			T10	4		T22	7		T36	25
values[3]	641	1			T2	4		T7	1		T134	1
values[4]	436	1			T5	13		T8	1		T12	4
values[5]	2802	1			T1	4		T3	37		T5	32
values[6]	806	1			T124	35		T125	17		T137	1
values[7]	738	1			T4	12		T22	15		T29	20
values[8]	495	1			T4	15		T5	2		T136	1
values[9]	1092	1			T2	23		T12	9		T23	22
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	580	1			T8	1		T11	4		T125	22
values[1]	697	1			T2	4		T10	4		T22	7
values[2]	647	1			T7	1		T134	1		T136	1
values[3]	2734	1			T1	4		T3	37		T5	13
values[4]	505	1			T5	32		T35	1		T36	18
values[5]	814	1			T124	35		T30	19		T125	17
values[6]	719	1			T4	12		T5	2		T22	15
values[7]	560	1			T4	15		T136	1		T137	1
values[8]	996	1			T12	9		T23	22		T29	2
values[9]	190	1			T2	23		T22	18		T96	12
minimum	14454	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	1		T125	10		T150	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	3		T170	12		T31	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T36	14		T132	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	4		T10	1		T22	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	1		T136	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T134	1		T125	15		T170	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T3	3		T5	7		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	3		T8	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	16		T35	1		T154	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T36	11		T170	8		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T30	14		T125	8		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T124	18		T32	3		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	1		T5	1		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T22	15		T135	1		T232	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	1		T238	4		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T136	1		T137	1		T143	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T29	1		T152	2		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T12	1		T23	22		T152	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T2	14		T151	3		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T2	9		T22	18		T96	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14256	1			T1	9		T6	125		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T127	1		T167	1		T330	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T125	12		T150	1		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	1		T31	1		T240	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T36	11		T132	5		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T10	3		T150	16		T231	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T129	12		T130	8		T146	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T125	11		T260	2		T256	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T3	34		T5	6		T28	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T1	1		T12	2		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T5	16		T154	4		T89	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T36	7		T152	12		T151	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T30	5		T125	9		T165	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T124	17		T143	10		T221	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	11		T5	1		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T125	7		T167	5		T212	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	14		T223	11		T288	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T143	5		T233	11		T299	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T29	1		T152	7		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	8		T152	3		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T151	1		T337	12		T338	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T97	17		T197	1		T210	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	2		T8	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T127	8		T167	10		T234	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T152	2		T224	1		T237	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T22	18		T145	12		T197	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T292	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T128	1		T291	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T8	1		T125	10		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T11	3		T127	1		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T36	14		T132	1		T231	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	1		T22	7		T124	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T136	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	4		T134	1		T125	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	7		T12	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T8	1		T12	1		T153	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1501	1			T3	3		T5	16		T24	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	3		T36	11		T170	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T125	8		T137	1		T13	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T124	18		T32	3		T143	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	1		T29	10		T35	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T22	15		T135	1		T232	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T4	1		T5	1		T238	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T136	1		T137	1		T143	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	14		T29	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T2	9		T12	1		T23	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T152	7		T224	14		T237	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T145	11		T197	1		T252	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T292	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T125	12		T127	2		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	1		T127	8		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T36	11		T132	5		T231	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T10	3		T150	16		T231	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	8		T146	6		T287	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T125	11		T260	2		T256	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T5	6		T127	2		T154	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T12	2		T165	12		T251	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T3	34		T5	16		T28	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	1		T36	7		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T125	9		T147	10		T223	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T124	17		T143	10		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	11		T29	10		T30	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T125	7		T167	5		T267	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	14		T5	1		T223	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T143	5		T212	8		T233	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T29	1		T151	1		T138	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T12	8		T152	3		T143	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	1		T125	13		T150	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	3		T170	1		T31	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T36	12		T132	6		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	1		T10	4		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	1		T136	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T134	1		T125	12		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T3	37		T5	7		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	3		T8	1		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	17		T35	1		T154	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	8		T170	1		T152	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T30	6		T125	10		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T124	19		T32	3		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	12		T5	2		T29	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T22	1		T135	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	15		T238	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	1		T137	1		T143	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T29	2		T152	8		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T12	9		T23	1		T152	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T2	1		T151	2		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T2	1		T22	1		T96	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14369	1			T1	11		T6	125		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T127	9		T167	11		T330	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T125	9		T150	10		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T170	11		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T36	13		T231	2		T217	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T2	3		T22	6		T124	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	7		T287	2		T236	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T125	14		T170	16		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T5	6		T24	22		T246	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T1	1		T174	10		T251	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	15		T154	14		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T36	10		T170	7		T152	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T30	13		T125	7		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T124	16		T143	10		T196	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T29	9		T35	4		T154	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T22	14		T232	7		T125	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T238	3		T131	7		T239	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T143	5		T233	9		T235	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	1		T239	9		T247	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T23	21		T152	9		T143	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T2	13		T151	2		T241	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T2	8		T22	17		T96	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T311	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T290	9		T339	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T152	8		T224	15		T237	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T22	1		T145	12		T197	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T292	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T128	1		T291	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	1		T125	13		T127	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	3		T127	9		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T36	12		T132	6		T231	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	4		T22	1		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	1		T136	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	1		T134	1		T125	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	7		T12	1		T127	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T8	1		T12	3		T153	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T3	37		T5	17		T24	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	3		T36	8		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T125	10		T137	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T124	19		T32	3		T143	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T4	12		T29	11		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T22	1		T135	1		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	15		T5	2		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	1		T137	1		T143	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	1		T29	2		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T2	1		T12	9		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T152	1		T219	8		T285	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T22	17		T145	11		T197	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T291	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T125	9		T150	10		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T11	1		T31	1		T133	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T36	13		T231	2		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	6		T124	4		T170	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T146	7		T287	2		T236	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	3		T125	14		T170	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	6		T154	6		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T251	1		T255	1		T245	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T5	15		T24	22		T246	36
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T36	10		T170	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T125	7		T13	1		T147	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T124	16		T143	10		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T29	9		T35	4		T30	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T22	14		T232	7		T125	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T238	3		T239	9		T241	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T143	5		T212	8		T233	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	13		T131	7		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T2	8		T23	21		T152	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21