Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19811

1

T1

15

T2

27

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3085

1

T5

32

T8

1

T11

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17208

1

T1

15

T2

14

T5

13

auto[1]

5688

1

T2

13

T3

37

T4

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	533	1			T5	13		T6	1		T22	18
values[0]	65	1			T155	12		T166	1		T247	12
values[1]	537	1			T2	9		T4	12		T124	2
values[2]	2923	1			T2	4		T3	37		T8	1
values[3]	662	1			T5	2		T29	20		T135	1
values[4]	569	1			T5	32		T8	1		T22	15
values[5]	595	1			T35	1		T124	5		T134	1
values[6]	686	1			T1	4		T12	3		T136	2
values[7]	745	1			T4	15		T23	22		T29	2
values[8]	525	1			T7	1		T11	4		T232	8
values[9]	1028	1			T2	14		T12	1		T22	7
minimum	14028	1			T1	11		T6	124		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	602	1			T2	9		T8	1		T10	4
values[1]	2866	1			T2	4		T3	37		T5	2
values[2]	638	1			T5	32		T29	20		T127	3
values[3]	530	1			T8	1		T22	15		T35	1
values[4]	574	1			T1	4		T12	3		T124	5
values[5]	706	1			T29	2		T136	2		T125	26
values[6]	807	1			T4	15		T7	1		T11	4
values[7]	570	1			T2	14		T12	1		T22	7
values[8]	892	1			T5	13		T36	18		T125	20
values[9]	156	1			T22	18		T35	5		T125	22
minimum	14555	1			T1	11		T4	12		T6	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	9		T10	1		T12	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T8	1		T124	1		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1485	1			T2	4		T3	3		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T135	1		T215	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T29	10		T127	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	16		T170	17		T32	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	1		T22	15		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T125	8		T153	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T1	3		T12	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T124	5		T144	4		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T125	15		T152	10		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	1		T136	2		T170	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T4	1		T7	1		T23	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	3		T232	8		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	14		T12	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T22	7		T124	17		T30	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T5	7		T36	11		T125	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T127	2		T167	1		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T35	5		T125	10		T154	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T22	18		T221	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14318	1			T1	9		T4	1		T6	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T137	1		T155	12		T166	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	3		T12	8		T129	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T124	1		T221	9		T167	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T3	34		T5	1		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T130	10		T240	12		T293	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T29	10		T127	2		T231	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	16		T143	5		T167	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T36	11		T31	1		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T125	9		T130	8		T150	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T1	1		T12	2		T152	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T144	6		T34	1		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T125	11		T152	3		T154	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	1		T226	10		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	14		T151	12		T190	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	1		T145	11		T174	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T294	6		T233	11		T210	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T124	16		T30	5		T223	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	6		T36	7		T125	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T127	10		T167	10		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T125	12		T154	4		T216	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T221	4		T224	7		T253	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	2		T4	11		T8	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T72	9		T274	2		T275	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T5	7		T6	1		T37	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T22	18		T127	1		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T191	8		T316	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T155	12		T166	1		T247	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	9		T4	1		T238	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T124	1		T137	1		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T2	4		T3	3		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T8	1		T215	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	1		T29	10		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T135	1		T170	17		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	1		T22	15		T36	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	16		T153	1		T143	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T35	1		T134	1		T170	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T124	5		T125	8		T144	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	3		T12	1		T125	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T136	2		T170	8		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T4	1		T23	22		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	1		T30	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	1		T129	1		T133	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	3		T232	8		T30	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T2	14		T12	1		T35	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T22	7		T124	17		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13936	1			T1	9		T6	124		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T5	6		T165	14		T216	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T127	8		T221	4		T253	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T191	7		T316	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T72	9		T317	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	11		T129	3		T132	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T124	1		T167	5		T97	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T3	34		T10	3		T12	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T221	9		T240	12		T293	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	1		T29	10		T127	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T130	10		T147	10		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T36	11		T31	1		T154	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	16		T143	5		T130	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T152	19		T97	17		T287	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T125	9		T144	6		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T12	2		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T226	10		T129	12		T165	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	14		T152	3		T146	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	1		T145	11		T223	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T294	6		T310	2		T210	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T11	1		T30	5		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	7		T125	19		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T124	16		T127	2		T167	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T2	1		T10	4		T12	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T8	1		T124	2		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T2	1		T3	37		T5	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T135	1		T215	1		T130	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	11		T127	3		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	17		T170	1		T32	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	1		T22	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T125	10		T153	1		T130	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T1	3		T12	3		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T124	1		T144	7		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T125	12		T152	4		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T29	2		T136	2		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T4	15		T7	1		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	3		T232	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T12	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T22	1		T124	17		T30	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	7		T36	8		T125	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T127	12		T167	11		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T35	1		T125	13		T154	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T22	1		T221	5		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14412	1			T1	11		T4	12		T6	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T137	1		T155	1		T166	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	8		T238	3		T196	25
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T96	11		T241	7		T278	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1163	1			T2	3		T24	22		T246	36
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T187	13		T240	10		T318	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T29	9		T131	7		T231	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	15		T170	16		T143	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T22	14		T36	13		T170	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T125	7		T150	10		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T1	1		T152	8		T89	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T124	4		T144	3		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T125	14		T152	9		T154	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T170	7		T241	23		T300	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T23	21		T133	27		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	1		T232	7		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	13		T16	1		T294	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T22	6		T124	16		T30	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	6		T36	10		T125	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T278	12		T310	7		T158	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T35	4		T125	9		T154	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T22	17		T218	3		T319	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T13	1		T235	2		T160	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T155	11		T247	11		T344	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	392	1			T5	7		T6	1		T37	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T22	1		T127	9		T221	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T191	8		T316	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T155	1		T166	1		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	1		T4	12		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T124	2		T137	1		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T2	1		T3	37		T10	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	1		T215	1		T221	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	2		T29	11		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T135	1		T170	1		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	1		T22	1		T36	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	17		T153	1		T143	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T35	1		T134	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T124	1		T125	10		T144	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	3		T12	3		T125	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T136	2		T170	1		T226	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	15		T23	1		T152	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	2		T30	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	1		T129	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	3		T232	1		T30	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	1		T12	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T22	1		T124	17		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14028	1			T1	11		T6	124		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T5	6		T216	1		T236	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T22	17		T158	10		T176	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T191	7		T316	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T155	11		T247	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	8		T238	3		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T96	11		T241	7		T278	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T2	3		T24	22		T246	36
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T187	13		T240	10		T245	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T29	9		T131	7		T231	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T170	16		T147	2		T222	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T22	14		T36	13		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	15		T143	7		T150	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T170	11		T152	8		T97	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T124	4		T125	7		T144	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T125	14		T154	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T170	7		T241	23		T300	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T23	21		T152	9		T146	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T145	11		T174	10		T345	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T133	23		T16	1		T294	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	1		T232	7		T30	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T2	13		T35	4		T36	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T22	6		T124	16		T150	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21