Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	3		T134	1		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	1		T5	2		T125	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	3		T2	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T5	17		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	7		T146	8		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T136	1		T30	6		T154	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T3	37		T24	2		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T22	1		T29	11		T124	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	15		T89	4		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T170	1		T152	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	1		T29	2		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	12		T133	1		T223	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T226	11		T215	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T7	1		T22	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	4		T35	1		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T125	8		T127	9		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	9		T23	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	3		T22	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T137	1		T251	4		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T127	3		T150	17		T158	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T154	20		T238	3		T146	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	3		T125	16		T131	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	1		T2	8		T125	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	13		T5	15		T133	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	6		T146	7		T187	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	13		T154	16		T151	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T24	22		T36	13		T246	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T22	6		T29	9		T124	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T89	1		T18	1		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T170	16		T152	7		T143	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T170	11		T144	11		T236	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T133	4		T231	6		T235	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T216	1		T241	14		T255	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T22	17		T124	4		T196	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T35	4		T36	10		T187	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T125	12		T152	10		T212	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T23	21		T232	7		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	1		T22	14		T170	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T251	1		T217	15		T252	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T150	14		T158	10		T219	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T219	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T169	1		T249	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T250	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	3		T12	3		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	2		T125	10		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	1		T136	1		T154	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	2		T5	17		T30	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	7		T125	12		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	1		T221	10		T129	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T36	12		T153	1		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T22	1		T29	11		T124	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T3	37		T4	15		T24	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T170	1		T152	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	1		T29	2		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	12		T124	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T215	1		T144	1		T216	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	1		T22	1		T130	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T36	8		T226	11		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T22	1		T127	9		T152	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	4		T12	9		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	3		T35	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T219	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T249	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T250	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T1	1		T154	6		T146	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T125	7		T131	7		T147	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	8		T154	14		T238	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	16		T5	15		T30	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	6		T125	14		T187	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T151	8		T239	17		T73	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T36	13		T146	7		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T22	6		T29	9		T124	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T24	22		T246	36		T195	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T170	16		T152	7		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T170	11		T144	3		T89	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T124	4		T133	4		T235	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T144	8		T216	1		T236	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	17		T196	25		T97	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	10		T187	13		T241	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T22	14		T152	10		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T23	21		T35	4		T232	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	1		T125	12		T170	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21