Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19757

1

T1

15

T2

9

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3139

1

T2

18

T8

1

T10

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17112

1

T1

11

T2

9

T4

12

auto[1]

5784

1

T1

4

T2

18

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T154	20		-	-		-	-
values[0]	54	1			T124	2		T256	28		T257	1
values[1]	691	1			T2	4		T4	12		T124	33
values[2]	614	1			T11	4		T124	5		T30	1
values[3]	516	1			T5	32		T35	5		T134	1
values[4]	625	1			T29	20		T127	3		T170	8
values[5]	517	1			T2	9		T4	15		T5	2
values[6]	767	1			T5	13		T8	1		T10	4
values[7]	588	1			T12	3		T22	33		T23	22
values[8]	760	1			T2	14		T8	1		T12	1
values[9]	3417	1			T1	4		T3	37		T7	1
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	885	1			T2	4		T4	12		T124	40
values[1]	585	1			T11	4		T35	5		T134	1
values[2]	584	1			T5	32		T29	20		T170	8
values[3]	504	1			T29	2		T232	8		T127	3
values[4]	537	1			T2	9		T4	15		T5	15
values[5]	714	1			T8	1		T10	4		T12	3
values[6]	3247	1			T3	37		T12	1		T22	15
values[7]	574	1			T2	14		T8	1		T22	7
values[8]	758	1			T125	26		T170	12		T153	1
values[9]	153	1			T1	4		T7	1		T12	9
minimum	14355	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	1		T124	1		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T2	4		T124	22		T30	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	3		T35	5		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T137	1		T215	1		T144	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	16		T29	10		T170	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	12		T132	1		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	1		T232	8		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T164	1		T130	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	9		T4	1		T5	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T129	2		T131	8		T146	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	1		T12	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	1		T22	18		T133	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T3	3		T12	1		T24	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T22	15		T23	22		T36	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T127	1		T170	17		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T2	14		T8	1		T22	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T170	12		T143	6		T144	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T125	15		T153	1		T143	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T1	3		T7	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T154	7		T248	3		T258	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14251	1			T1	9		T6	125		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	11		T124	1		T150	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T124	16		T30	5		T125	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	1		T154	4		T97	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T240	1		T156	8		T158	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	16		T29	10		T221	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T259	2		T260	2		T261	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	1		T127	2		T152	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T130	8		T167	10		T132	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	14		T5	7		T167	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T129	15		T146	7		T151	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	2		T236	12		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	3		T224	21		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T3	34		T28	9		T36	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T36	7		T152	3		T143	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T127	2		T152	12		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T231	9		T262	9		T263	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T143	5		T144	6		T236	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T125	11		T143	5		T226	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T1	1		T12	8		T125	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T154	13		T248	2		T264	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T1	2		T8	1		T11	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T154	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T124	1		T256	16		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T265	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T150	15		T151	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	4		T124	17		T30	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	3		T32	3		T154	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T124	5		T30	1		T125	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	16		T35	5		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T215	1		T144	9		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T29	10		T127	1		T170	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T167	1		T155	12		T146	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	9		T4	1		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T164	1		T129	2		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T5	7		T8	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	1		T131	8		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T12	1		T35	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T22	33		T23	22		T36	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	1		T36	14		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	14		T8	1		T22	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1665	1			T1	3		T3	3		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T125	15		T153	1		T143	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T154	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T124	1		T256	12		T266	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	11		T150	16		T151	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T124	16		T30	5		T150	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T11	1		T154	4		T97	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T125	21		T240	1		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	16		T167	9		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T156	8		T260	2		T261	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	10		T127	2		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T167	10		T146	7		T132	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	14		T5	1		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T129	15		T130	8		T151	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	6		T167	5		T267	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	3		T224	14		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	2		T127	8		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T36	7		T152	3		T240	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	11		T127	2		T152	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T143	10		T160	12		T268	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T1	1		T3	34		T12	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T125	11		T143	5		T226	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	12		T124	2		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	1		T124	18		T30	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	3		T35	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T137	1		T215	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	17		T29	11		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T155	1		T132	1		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T29	2		T232	1		T127	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T164	1		T130	9		T167	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	1		T4	15		T5	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T129	17		T131	1		T146	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	1		T12	3		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	4		T22	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T3	37		T12	1		T24	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T22	1		T23	1		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T127	3		T170	1		T152	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T2	1		T8	1		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T170	1		T143	6		T144	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T125	12		T153	1		T143	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T1	3		T7	1		T12	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T154	14		T248	4		T258	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14340	1			T1	11		T6	125		T8	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T150	14		T151	8		T240	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	3		T124	20		T30	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T35	4		T154	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T144	8		T158	10		T235	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T5	15		T29	9		T170	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T155	11		T217	13		T259	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T232	7		T152	1		T131	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T187	10		T241	7		T219	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	8		T5	6		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T131	7		T146	7		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T187	13		T96	11		T239	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T22	17		T133	23		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T24	22		T36	13		T246	36
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T22	14		T23	21		T36	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T170	16		T152	7		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T2	13		T22	6		T238	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T170	11		T143	5		T144	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T125	14		T143	7		T154	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T1	1		T125	12		T239	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T154	6		T248	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T256	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T154	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T124	2		T256	13		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	12		T150	17		T151	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	1		T124	17		T30	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	3		T32	3		T154	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T124	1		T30	1		T125	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	17		T35	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T215	1		T144	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T29	11		T127	3		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T167	11		T155	1		T146	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	1		T4	15		T5	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T164	1		T129	17		T130	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	7		T8	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	4		T131	1		T224	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	3		T35	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	2		T23	1		T36	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T36	12		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T8	1		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T1	3		T3	37		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T125	12		T153	1		T143	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T154	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T256	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T265	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T150	14		T151	8		T240	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	3		T124	16		T30	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T11	1		T154	14		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T124	4		T125	16		T133	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	15		T35	4		T232	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T144	8		T269	4		T261	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	9		T170	7		T152	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T155	11		T146	7		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	8		T131	6		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T151	2		T241	7		T270	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	6		T187	13		T96	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T131	7		T247	17		T190	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T31	1		T239	9		T216	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T22	31		T23	21		T36	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T36	13		T170	16		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	13		T22	6		T143	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T1	1		T24	22		T246	36
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T125	14		T143	7		T154	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21