Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19471

1

T1

15

T2

27

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3425

1

T4

27

T5

34

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17232

1

T1

11

T2

13

T4

15

auto[1]

5664

1

T1

4

T2

14

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T271	1		-	-		-	-
values[0]	47	1			T145	23		T148	1		T272	22
values[1]	656	1			T4	15		T23	22		T134	1
values[2]	510	1			T22	18		T124	35		T136	1
values[3]	563	1			T7	1		T35	1		T36	25
values[4]	547	1			T2	9		T11	4		T12	9
values[5]	659	1			T2	18		T5	2		T8	1
values[6]	584	1			T1	4		T5	32		T29	2
values[7]	638	1			T8	1		T170	8		T152	20
values[8]	3075	1			T3	37		T5	13		T10	4
values[9]	1289	1			T4	12		T12	3		T22	7
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	686	1			T4	15		T22	18		T23	22
values[1]	613	1			T7	1		T124	35		T232	8
values[2]	575	1			T2	9		T35	6		T143	21
values[3]	599	1			T11	4		T12	9		T36	25
values[4]	565	1			T1	4		T2	18		T5	2
values[5]	638	1			T5	32		T8	1		T170	20
values[6]	3139	1			T3	37		T5	13		T24	24
values[7]	612	1			T10	4		T12	1		T124	5
values[8]	877	1			T4	12		T12	3		T22	7
values[9]	237	1			T29	20		T170	17		T31	1
minimum	14355	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	18		T137	1		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	1		T23	22		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	1		T154	7		T146	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T124	18		T232	8		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	9		T35	5		T133	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	1		T143	11		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	3		T12	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	14		T165	1		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	3		T2	18		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T22	15		T125	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	1		T170	8		T196	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	16		T170	12		T31	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T3	3		T5	7		T24	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T152	10		T154	32		T144	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	1		T128	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T124	5		T125	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T12	1		T136	1		T30	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	1		T22	7		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T29	10		T170	17		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T273	1		T274	30		T275	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14236	1			T1	9		T6	125		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T272	10		T276	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T158	5		T219	11		T259	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	14		T145	11		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T154	13		T146	7		T222	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T124	17		T221	11		T129	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T236	7		T225	5		T277	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T143	10		T236	12		T263	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	1		T12	8		T127	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T36	11		T165	14		T97	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T29	1		T36	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	1		T125	12		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T132	5		T151	12		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	16		T31	1		T226	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1146	1			T3	34		T5	6		T28	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T152	19		T154	22		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	3		T251	1		T278	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T125	9		T127	2		T143	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	2		T30	5		T125	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	11		T125	11		T152	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T29	10		T223	11		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T274	16		T275	7		T279	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T1	2		T8	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T272	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T271	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T148	1		T280	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T145	12		T272	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T215	1		T154	7		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T23	22		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T22	18		T137	1		T32	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T124	18		T136	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	1		T281	1		T96	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T35	1		T36	14		T232	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	9		T11	3		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T165	1		T230	1		T281	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	18		T8	1		T36	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T22	15		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	3		T29	1		T196	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	16		T125	10		T170	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T8	1		T170	8		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T152	8		T153	1		T154	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T3	3		T5	7		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T124	5		T125	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T12	1		T29	10		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T4	1		T22	7		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T145	11		T272	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T154	13		T146	7		T158	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	14		T18	1		T224	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T282	13		T72	9		T283	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T124	17		T221	11		T129	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T222	9		T225	5		T277	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T36	11		T143	10		T97	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	1		T12	8		T127	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T165	14		T151	6		T254	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T36	7		T127	8		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	1		T231	6		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T29	1		T132	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	16		T125	12		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T151	1		T231	9		T156	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T152	12		T154	4		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T3	34		T5	6		T10	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T125	11		T152	7		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T12	2		T29	10		T125	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T4	11		T125	9		T127	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T22	1		T137	1		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	15		T23	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T154	14		T146	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T124	19		T232	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	1		T35	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T35	1		T143	11		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	3		T12	9		T127	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	12		T165	15		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	3		T2	2		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	2		T22	1		T125	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	1		T170	1		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	17		T170	1		T31	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T3	37		T5	7		T24	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T152	21		T154	24		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	4		T128	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T124	1		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	3		T136	1		T30	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	12		T22	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T29	11		T170	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T273	1		T274	18		T275	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14332	1			T1	11		T6	125		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T272	13		T276	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T22	17		T241	9		T158	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T23	21		T145	11		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T154	6		T146	7		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T124	16		T232	7		T150	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	8		T35	4		T133	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T143	10		T239	9		T236	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	1		T146	7		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T36	13		T97	9		T151	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	1		T2	16		T36	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T22	14		T125	9		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T170	7		T196	25		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	15		T170	11		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T5	6		T24	22		T246	36
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T152	8		T154	30		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T239	17		T251	1		T284	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T124	4		T125	7		T143	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T30	13		T125	12		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	6		T125	14		T152	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T29	9		T170	16		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T274	28		T279	12		T218	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T272	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T271	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T148	1		T280	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T145	12		T272	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T215	1		T154	14		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	15		T23	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T22	1		T137	1		T32	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T124	19		T136	1		T221	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	1		T281	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	1		T36	12		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	1		T11	3		T12	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T165	15		T230	1		T281	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	2		T8	1		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	2		T22	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	3		T29	2		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	17		T125	13		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	1		T170	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T152	13		T153	1		T154	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T3	37		T5	7		T10	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T124	1		T125	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T12	3		T29	11		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T4	12		T22	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T145	11		T272	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T154	6		T146	7		T241	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T23	21		T18	1		T212	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T22	17		T285	15		T283	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T124	16		T150	7		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T96	11		T241	7		T222	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T36	13		T232	7		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	8		T11	1		T35	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T151	8		T247	11		T254	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	16		T36	10		T131	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T22	14		T231	6		T248	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T196	25		T187	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T5	15		T125	9		T170	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T170	7		T151	2		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T152	7		T154	14		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T5	6		T24	22		T246	36
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T124	4		T125	14		T152	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T29	9		T125	12		T170	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T22	6		T125	7		T152	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21