Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19617

1

T1

11

T2

14

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3279

1

T1

4

T2

13

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17520

1

T1

11

T2

13

T4

12

auto[1]

5376

1

T1

4

T2

14

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T217	16		-	-		-	-
values[0]	69	1			T8	1		T128	1		T150	12
values[1]	473	1			T11	4		T125	22		T127	12
values[2]	709	1			T10	4		T36	25		T124	5
values[3]	682	1			T2	4		T7	1		T22	7
values[4]	443	1			T5	13		T8	1		T12	4
values[5]	2806	1			T1	4		T3	37		T5	32
values[6]	769	1			T22	15		T124	35		T135	1
values[7]	685	1			T29	20		T35	5		T232	8
values[8]	591	1			T4	27		T5	2		T136	1
values[9]	1326	1			T2	23		T12	9		T22	18
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	722	1			T8	1		T11	4		T124	5
values[1]	650	1			T2	4		T10	4		T22	7
values[2]	689	1			T7	1		T134	1		T136	1
values[3]	2764	1			T1	4		T3	37		T5	13
values[4]	492	1			T12	1		T35	1		T36	18
values[5]	717	1			T5	32		T124	2		T125	17
values[6]	787	1			T4	12		T5	2		T22	15
values[7]	563	1			T4	15		T136	1		T137	1
values[8]	930	1			T12	9		T23	22		T29	2
values[9]	253	1			T2	23		T22	18		T96	12
minimum	14329	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	1		T125	10		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	3		T124	5		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T36	14		T132	1		T231	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	4		T10	1		T22	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	1		T136	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T134	1		T125	15		T170	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T3	3		T5	7		T24	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	3		T8	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	1		T35	1		T154	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T36	11		T124	17		T170	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	16		T125	8		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T124	1		T32	3		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	1		T5	1		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T22	15		T135	1		T232	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	1		T31	1		T238	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T136	1		T137	1		T143	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T29	1		T152	2		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T12	1		T23	22		T152	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T2	14		T151	3		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T2	9		T22	18		T96	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T128	1		T286	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T125	12		T127	2		T34	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	1		T127	8		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	11		T132	5		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T10	3		T150	16		T231	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T129	12		T130	8		T287	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T125	11		T251	1		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T3	34		T5	6		T28	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T1	1		T12	2		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T154	4		T89	1		T216	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T36	7		T124	16		T152	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	16		T125	9		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T124	1		T143	10		T129	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	11		T5	1		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T125	7		T167	5		T212	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	14		T288	2		T259	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T143	5		T223	11		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	1		T152	7		T224	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	8		T152	3		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T151	1		T138	10		T289	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T97	17		T197	1		T210	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T217	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T8	1		T150	11		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T128	1		T290	10		T291	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T125	10		T127	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	3		T127	1		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T36	14		T132	1		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	1		T124	5		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	1		T136	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	4		T22	7		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	7		T12	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	1		T12	1		T153	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T3	3		T5	16		T24	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	3		T36	11		T170	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T125	8		T137	1		T13	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T22	15		T124	18		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T29	10		T35	5		T30	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T232	8		T125	13		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	2		T5	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T136	1		T137	1		T143	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T2	14		T29	1		T152	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T2	9		T12	1		T22	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T150	1		T224	7		T292	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T290	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T125	12		T127	2		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	1		T127	8		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T36	11		T132	5		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T10	3		T150	16		T231	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T130	8		T146	6		T287	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T125	11		T165	12		T260	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	6		T127	2		T154	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T12	2		T251	1		T240	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T3	34		T5	16		T28	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	1		T36	7		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T125	9		T223	9		T293	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T124	17		T143	10		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T29	10		T30	5		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T125	7		T167	5		T267	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	25		T5	1		T154	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T143	5		T223	11		T212	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T29	1		T152	7		T151	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T12	8		T152	3		T143	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	1		T125	13		T127	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	3		T124	1		T127	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T36	12		T132	6		T231	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T2	1		T10	4		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	1		T136	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T134	1		T125	12		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T3	37		T5	7		T24	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	3		T8	1		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	1		T35	1		T154	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	8		T124	17		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	17		T125	10		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T124	2		T32	3		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T4	12		T5	2		T29	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T22	1		T135	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	15		T31	1		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T136	1		T137	1		T143	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T29	2		T152	8		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T12	9		T23	1		T152	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T2	1		T151	2		T138	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T2	1		T22	1		T96	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T128	1		T286	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T125	9		T150	10		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	1		T124	4		T170	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T36	13		T231	2		T217	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T2	3		T22	6		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T287	2		T236	14		T294	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T125	14		T170	16		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T5	6		T24	22		T246	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T1	1		T174	10		T255	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T154	14		T13	1		T187	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T36	10		T124	16		T170	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	15		T125	7		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T143	10		T196	25		T133	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	9		T35	4		T30	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T22	14		T232	7		T125	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T238	3		T131	7		T239	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T143	5		T233	9		T235	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T152	1		T239	9		T247	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T23	21		T152	9		T143	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T2	13		T151	2		T241	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T2	8		T22	17		T96	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T217	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T8	1		T150	2		T224	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T128	1		T290	14		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T125	13		T127	3		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	3		T127	9		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T36	12		T132	6		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	4		T124	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	1		T136	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T22	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	7		T12	1		T127	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T8	1		T12	3		T153	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T3	37		T5	17		T24	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	3		T36	8		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T125	10		T137	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T22	1		T124	19		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T29	11		T35	1		T30	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T232	1		T125	8		T167	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	27		T5	2		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T136	1		T137	1		T143	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T2	1		T29	2		T152	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	405	1			T2	1		T12	9		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T217	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T150	10		T295	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T290	9		T291	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T125	9		T190	10		T284	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T11	1		T31	1		T133	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T36	13		T18	1		T231	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T124	4		T170	11		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T146	7		T287	2		T236	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	3		T22	6		T125	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	6		T154	6		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T251	1		T255	1		T285	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T5	15		T24	22		T246	36
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	1		T36	10		T170	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T125	7		T13	1		T133	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T22	14		T124	16		T143	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T29	9		T35	4		T30	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T232	7		T125	12		T267	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T154	16		T238	3		T239	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T143	5		T212	8		T284	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T2	13		T152	1		T131	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T2	8		T22	17		T23	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21