Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19459

1

T1

11

T3

37

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

3437

1

T1

4

T2

27

T4

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17079

1

T1

11

T2

4

T4

12

auto[1]

5817

1

T1

4

T2

23

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T296	13		T297	24		-	-
values[0]	100	1			T152	9		T144	9		T298	3
values[1]	630	1			T29	2		T35	6		T36	25
values[2]	509	1			T1	4		T5	2		T12	1
values[3]	522	1			T136	1		T127	3		T154	19
values[4]	2990	1			T2	4		T3	37		T7	1
values[5]	662	1			T4	12		T8	1		T22	18
values[6]	674	1			T2	14		T4	15		T5	13
values[7]	603	1			T5	32		T36	18		T152	20
values[8]	679	1			T2	9		T23	22		T127	12
values[9]	1163	1			T10	4		T11	4		T12	12
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	815	1			T29	2		T35	6		T36	25
values[1]	610	1			T1	4		T5	2		T12	1
values[2]	455	1			T7	1		T136	2		T128	1
values[3]	3052	1			T2	4		T3	37		T24	24
values[4]	622	1			T4	12		T8	2		T22	33
values[5]	683	1			T2	14		T4	15		T5	45
values[6]	583	1			T2	9		T36	18		T152	20
values[7]	692	1			T11	4		T12	9		T23	22
values[8]	894	1			T10	4		T12	3		T124	40
values[9]	148	1			T22	7		T153	1		T163	1
minimum	14342	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T29	1		T35	6		T36	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T135	1		T125	8		T170	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T136	1		T30	14		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	3		T5	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T7	1		T136	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T136	1		T196	26		T133	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T3	3		T24	24		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	4		T127	1		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	1		T8	2		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T22	33		T29	10		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	16		T144	4		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	14		T4	1		T5	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T152	8		T226	1		T154	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	9		T36	11		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T23	22		T127	1		T238	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	3		T12	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	1		T124	22		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	1		T124	1		T232	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T22	7		T163	1		T216	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T153	1		T164	1		T128	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14246	1			T1	9		T6	125		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T29	1		T36	11		T125	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T125	9		T231	9		T253	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T30	5		T150	1		T73	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	1		T5	1		T154	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T167	5		T89	1		T294	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T231	6		T299	6		T300	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T3	34		T28	9		T180	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T127	2		T31	1		T221	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T4	11		T143	10		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T29	10		T221	4		T190	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	16		T144	6		T129	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	14		T5	6		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T152	12		T226	10		T154	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T36	7		T240	12		T288	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T127	8		T146	6		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T12	8		T127	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T12	2		T124	16		T125	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	3		T124	1		T125	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T216	1		T301	5		T297	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T282	13		T302	1		T303	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T1	2		T8	1		T11	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T296	13		T297	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T152	2		T298	1		T304	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T144	9		T305	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T29	1		T35	6		T36	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T125	8		T170	17		T131	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T136	1		T30	14		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	3		T5	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T128	1		T167	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T136	1		T127	1		T154	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T3	3		T7	1		T24	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	4		T31	1		T151	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	1		T8	1		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T22	18		T31	2		T221	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	1		T144	4		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	14		T4	1		T5	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	16		T152	8		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T36	11		T133	13		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T23	22		T127	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	9		T127	1		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T12	1		T22	7		T124	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T10	1		T11	3		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T297	22		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T152	7		T298	2		T304	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T305	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T29	1		T36	11		T125	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T125	9		T231	9		T233	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T30	5		T150	1		T206	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T5	1		T167	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T167	5		T89	1		T192	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	2		T154	4		T130	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T3	34		T28	9		T180	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T151	6		T224	14		T231	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T4	11		T143	10		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T31	1		T221	15		T151	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T144	6		T129	3		T146	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	14		T5	6		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	16		T152	12		T226	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T36	7		T223	9		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T127	8		T154	18		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T127	2		T223	11		T287	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	2		T124	16		T125	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T10	3		T11	1		T12	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T29	2		T35	2		T36	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T135	1		T125	10		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T136	1		T30	6		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	3		T5	2		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T7	1		T136	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T136	1		T196	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1418	1			T3	37		T24	2		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T127	3		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	12		T8	2		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T22	2		T29	11		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	17		T144	7		T129	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	1		T4	15		T5	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	13		T226	11		T154	33
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	1		T36	8		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T23	1		T127	9		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	3		T12	9		T127	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T12	3		T124	18		T125	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	4		T124	2		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T22	1		T163	1		T216	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T153	1		T164	1		T128	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14332	1			T1	11		T6	125		T8	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T35	4		T36	13		T125	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T125	7		T170	16		T144	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T30	13		T150	10		T73	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T154	14		T97	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T89	1		T294	4		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T196	25		T133	23		T231	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T24	22		T246	36		T170	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	3		T31	1		T151	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T143	10		T146	7		T187	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T22	31		T29	9		T190	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	15		T144	3		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	13		T5	6		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T152	7		T154	22		T219	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	8		T36	10		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T23	21		T238	3		T146	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	1		T287	2		T212	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T124	20		T125	14		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T232	7		T125	9		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T22	6		T216	1		T247	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T302	1		T303	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T174	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T296	1		T297	24		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T152	8		T298	3		T304	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T144	1		T305	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T29	2		T35	2		T36	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T125	10		T170	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T136	1		T30	6		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	3		T5	2		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T128	1		T167	6		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T136	1		T127	3		T154	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T3	37		T7	1		T24	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T31	1		T151	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	12		T8	1		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T22	1		T31	2		T221	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	1		T144	7		T129	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T4	15		T5	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	17		T152	13		T226	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T36	8		T133	1		T223	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T23	1		T127	9		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T127	3		T223	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T12	3		T22	1		T124	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T10	4		T11	3		T12	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T296	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T152	1		T304	2		T306	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T144	8		T305	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T35	4		T36	13		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T125	7		T170	16		T131	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T30	13		T155	11		T150	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T1	1		T197	1		T217	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T89	1		T141	2		T307	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T154	14		T196	25		T133	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T24	22		T246	36		T170	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	3		T151	8		T231	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T143	10		T187	13		T236	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T22	17		T31	1		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T144	3		T146	7		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	13		T5	6		T22	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	15		T152	7		T154	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	10		T133	12		T278	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T23	21		T154	16		T146	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T2	8		T287	2		T212	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T22	6		T124	20		T125	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	1		T232	7		T125	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21