Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20012

1

T1

11

T2

27

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

2884

1

T1

4

T4

12

T5

47

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17235

1

T1

11

T2

13

T4

12

auto[1]

5661

1

T1

4

T2

14

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	4	1			T308	4		-	-		-	-
values[0]	124	1			T150	12		T142	14		T300	2
values[1]	627	1			T35	5		T127	3		T170	12
values[2]	2830	1			T2	4		T3	37		T12	9
values[3]	539	1			T127	3		T31	3		T129	4
values[4]	692	1			T11	4		T22	22		T134	1
values[5]	681	1			T1	4		T4	12		T8	1
values[6]	674	1			T2	14		T5	13		T7	1
values[7]	527	1			T5	2		T36	18		T127	9
values[8]	678	1			T4	15		T5	32		T12	1
values[9]	1193	1			T2	9		T23	22		T29	2
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	806	1			T35	5		T137	2		T127	3
values[1]	2804	1			T2	4		T3	37		T12	9
values[2]	661	1			T22	22		T127	3		T31	3
values[3]	772	1			T11	4		T125	26		T137	1
values[4]	643	1			T1	4		T4	12		T8	1
values[5]	518	1			T2	14		T5	13		T7	1
values[6]	698	1			T5	2		T12	1		T29	20
values[7]	597	1			T4	15		T5	32		T35	1
values[8]	893	1			T2	9		T29	2		T36	25
values[9]	159	1			T23	22		T163	1		T138	11
minimum	14345	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T35	5		T127	1		T170	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T137	2		T153	1		T143	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T2	4		T3	3		T22	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T12	1		T214	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T22	15		T127	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	7		T31	2		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	3		T137	1		T170	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T125	15		T152	10		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	1		T12	1		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	3		T4	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T2	14		T7	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	7		T8	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T29	10		T36	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T127	1		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	1		T35	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	16		T124	17		T232	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T2	9		T29	1		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T36	14		T30	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T23	22		T191	10		T309	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T163	1		T138	1		T310	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14236	1			T1	9		T6	125		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T290	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T127	2		T154	13		T221	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T143	10		T154	4		T223	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T3	34		T28	9		T180	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	8		T132	5		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T127	2		T129	3		T130	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T31	1		T130	8		T146	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	1		T154	18		T97	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T125	11		T152	3		T167	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	2		T124	1		T125	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T1	1		T4	11		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T150	7		T224	7		T156	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	6		T10	3		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	10		T36	7		T30	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T127	8		T152	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	14		T129	12		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	16		T124	16		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T29	1		T125	12		T221	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T36	11		T226	10		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T191	9		T311	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T138	10		T310	8		T259	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T1	2		T8	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T290	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T308	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T150	11		T274	15		T270	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T142	1		T300	1		T194	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T35	5		T127	1		T170	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T153	1		T143	11		T154	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T2	4		T3	3		T22	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T12	1		T137	2		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T127	1		T129	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T31	2		T130	1		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	3		T22	15		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T22	7		T134	1		T125	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	1		T12	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	3		T4	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	14		T7	1		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	7		T8	1		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	11		T164	1		T131	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	1		T127	1		T152	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	1		T12	1		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	16		T124	17		T125	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T2	9		T23	22		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T36	14		T232	8		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T150	1		T274	2		T270	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T142	13		T300	1		T312	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T127	2		T212	8		T231	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T143	10		T154	4		T223	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1138	1			T3	34		T28	9		T180	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T12	8		T132	5		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T127	2		T129	3		T130	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T31	1		T130	8		T146	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	1		T34	1		T97	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T125	11		T190	10		T254	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	2		T154	18		T151	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	1		T4	11		T152	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T124	1		T125	7		T143	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	6		T10	3		T144	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T36	7		T150	23		T224	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	1		T127	8		T152	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	14		T29	10		T30	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	16		T124	16		T125	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T29	1		T125	12		T221	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T36	11		T226	10		T221	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T35	1		T127	3		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T137	2		T153	1		T143	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T2	1		T3	37		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	9		T214	1		T132	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T22	1		T127	3		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	1		T31	2		T130	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	3		T137	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T125	12		T152	4		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	1		T12	3		T124	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	3		T4	12		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	1		T7	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	7		T8	1		T10	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T29	11		T36	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	2		T127	9		T152	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	15		T35	1		T129	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	17		T124	17		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	1		T29	2		T125	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T36	12		T30	1		T226	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T23	1		T191	10		T309	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T163	1		T138	11		T310	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14332	1			T1	11		T6	125		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T290	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T35	4		T170	11		T154	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T143	10		T154	14		T233	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T2	3		T22	17		T24	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T147	2		T133	4		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T22	14		T131	6		T89	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T22	6		T31	1		T146	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T170	7		T154	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T125	14		T152	9		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T125	12		T170	16		T143	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T1	1		T16	1		T174	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T2	13		T131	7		T96	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T5	6		T152	1		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	9		T36	10		T124	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T152	7		T187	13		T236	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T151	15		T239	9		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	15		T124	16		T232	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	8		T125	9		T196	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	13		T238	3		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T23	21		T191	9		T311	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T310	7		T259	2		T274	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T290	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T308	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T150	2		T274	3		T270	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T142	14		T300	2		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T35	1		T127	3		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T153	1		T143	11		T154	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T2	1		T3	37		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	9		T137	2		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T127	3		T129	4		T130	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T31	2		T130	9		T146	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	3		T22	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T22	1		T134	1		T125	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	1		T12	3		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	3		T4	12		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	1		T7	1		T124	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	7		T8	1		T10	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T36	8		T164	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	2		T127	9		T152	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	15		T12	1		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	17		T124	17		T125	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T2	1		T23	1		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T36	12		T232	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T150	10		T274	14		T270	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T194	11		T312	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T35	4		T170	11		T212	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T143	10		T154	14		T233	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T2	3		T22	17		T24	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T147	2		T307	2		T313	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T89	1		T216	1		T217	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T31	1		T146	7		T133	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	1		T22	14		T170	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	6		T125	14		T133	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T170	16		T154	16		T151	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	1		T152	9		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	13		T125	12		T143	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	6		T144	3		T187	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T36	10		T131	7		T150	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T152	8		T13	1		T217	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T29	9		T124	4		T30	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	15		T124	16		T125	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T2	8		T23	21		T125	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T36	13		T232	7		T238	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21