Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19927

1

T1

15

T2

13

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

2969

1

T2

14

T5

45

T12

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17238

1

T1

15

T5

13

T6

124

auto[1]

5658

1

T2

27

T3

37

T4

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	316	1			T6	1		T37	2		T40	1
values[0]	47	1			T166	1		T240	2		T72	10
values[1]	578	1			T2	9		T4	12		T124	2
values[2]	2915	1			T2	4		T3	37		T8	1
values[3]	665	1			T5	2		T29	20		T135	1
values[4]	554	1			T5	32		T8	1		T22	15
values[5]	597	1			T35	1		T124	5		T134	1
values[6]	615	1			T1	4		T12	3		T136	2
values[7]	743	1			T4	15		T23	22		T29	2
values[8]	594	1			T7	1		T11	4		T22	7
values[9]	1244	1			T2	14		T5	13		T12	1
minimum	14028	1			T1	11		T6	124		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	815	1			T2	9		T4	12		T8	1
values[1]	2883	1			T2	4		T3	37		T5	2
values[2]	594	1			T5	32		T127	3		T170	17
values[3]	547	1			T8	1		T22	15		T35	1
values[4]	547	1			T1	4		T12	3		T124	5
values[5]	761	1			T29	2		T136	2		T125	26
values[6]	757	1			T4	15		T7	1		T23	22
values[7]	603	1			T2	14		T11	4		T12	1
values[8]	867	1			T5	13		T22	18		T36	18
values[9]	171	1			T35	5		T153	1		T154	19
minimum	14351	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T2	9		T4	1		T8	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T124	1		T137	1		T13	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T2	4		T3	3		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T29	10		T215	1		T187	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T144	9		T99	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	16		T127	1		T170	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	1		T22	15		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T125	8		T153	1		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	3		T124	5		T152	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T134	1		T152	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	1		T170	8		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T29	1		T136	1		T125	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	1		T7	1		T23	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T232	8		T30	1		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	3		T129	1		T187	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	14		T12	1		T22	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T125	23		T127	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	7		T22	18		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T35	5		T153	1		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T154	15		T221	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14247	1			T1	9		T6	125		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T215	1		T314	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	11		T10	3		T12	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T124	1		T221	9		T167	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T3	34		T5	1		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T29	10		T293	3		T262	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T231	9		T251	1		T222	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	16		T127	2		T143	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T36	11		T31	1		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T125	9		T130	8		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T1	1		T152	12		T287	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	2		T152	7		T144	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T152	3		T154	18		T221	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	1		T125	11		T226	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	14		T129	12		T151	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T145	11		T310	2		T160	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	1		T223	9		T294	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T124	16		T30	5		T150	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T125	19		T127	2		T143	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	6		T36	7		T127	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T224	7		T216	1		T315	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T154	4		T221	4		T218	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T314	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T6	1		T37	2		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T240	1		T191	10		T316	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T166	1		T72	1		T317	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	9		T4	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T124	1		T137	1		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T2	4		T3	3		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T32	3		T215	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T135	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	10		T170	17		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	1		T22	15		T36	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	16		T127	1		T152	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T35	1		T124	5		T170	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T134	1		T125	8		T230	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	3		T136	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T136	1		T125	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T4	1		T23	22		T170	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T29	1		T30	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	1		T11	3		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T22	7		T232	8		T30	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T35	5		T125	23		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T2	14		T5	7		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13936	1			T1	9		T6	124		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T224	7		T192	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T240	1		T191	9		T316	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T72	9		T317	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T4	11		T132	5		T97	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T124	1		T167	5		T256	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T3	34		T10	3		T12	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T221	9		T150	7		T293	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T130	10		T231	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T29	10		T167	9		T147	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T36	11		T154	13		T150	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	16		T127	2		T152	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T152	12		T31	1		T287	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T125	9		T97	17		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T154	18		T221	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	2		T125	11		T226	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	14		T152	3		T146	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	1		T145	11		T146	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T11	1		T294	6		T222	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T30	5		T310	10		T159	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T125	19		T127	2		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	6		T36	7		T124	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T2	1		T4	12		T8	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T124	2		T137	1		T13	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T2	1		T3	37		T5	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	11		T215	1		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T144	1		T99	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	17		T127	3		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T8	1		T22	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T125	10		T153	1		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	3		T124	1		T152	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	3		T134	1		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T136	1		T170	1		T152	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	2		T136	1		T125	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	15		T7	1		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T232	1		T30	1		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	3		T129	1		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	1		T12	1		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T125	21		T127	3		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	7		T22	1		T36	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T35	1		T153	1		T224	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T154	5		T221	5		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14328	1			T1	11		T6	125		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T215	1		T314	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	8		T238	3		T196	25
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T13	1		T155	11		T150	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T2	3		T24	22		T246	36
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T29	9		T187	13		T318	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T144	8		T231	2		T251	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	15		T170	16		T143	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T22	14		T36	13		T170	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T125	7		T18	1		T239	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	1		T124	4		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T152	1		T144	3		T89	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T170	7		T152	9		T154	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T125	14		T146	7		T241	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T23	21		T133	27		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T232	7		T145	11		T310	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	1		T187	10		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	13		T22	6		T124	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T125	21		T143	5		T131	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	6		T22	17		T36	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T35	4		T216	1		T315	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T154	14		T218	3		T319	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T247	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T314	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T6	1		T37	2		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T240	2		T191	10		T316	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T166	1		T72	10		T317	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	1		T4	12		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T124	2		T137	1		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T2	1		T3	37		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T32	3		T215	1		T221	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	2		T135	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T29	11		T170	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T8	1		T22	1		T36	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	17		T127	3		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T124	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	1		T125	10		T230	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	3		T136	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	3		T136	1		T125	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T4	15		T23	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	2		T30	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	1		T11	3		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T22	1		T232	1		T30	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T35	1		T125	21		T127	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	1		T5	7		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14028	1			T1	11		T6	124		T8	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T191	9		T316	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	8		T238	3		T196	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T13	1		T155	11		T187	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T2	3		T24	22		T246	36
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T150	7		T320	11		T304	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T231	2		T222	6		T255	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	9		T170	16		T131	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T22	14		T36	13		T154	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	15		T152	1		T143	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T124	4		T170	11		T152	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T125	7		T97	9		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T1	1		T154	16		T267	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T125	14		T144	3		T89	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T23	21		T170	7		T152	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T145	11		T146	7		T244	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	1		T133	23		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T22	6		T232	7		T30	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T35	4		T125	21		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	13		T5	6		T22	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21