Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22896

1

T1

15

T2

27

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19406

1

T1

15

T2

27

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3490

1

T4

27

T5

34

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17277

1

T1

11

T2

13

T4

15

auto[1]

5619

1

T1

4

T2

14

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19020

1

T1

12

T2

27

T3

3

auto[1]

3876

1

T1

3

T3

34

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	321	1			T29	20		T136	1		T170	17
values[0]	23	1			T23	22		T280	1		-	-
values[1]	637	1			T4	15		T134	1		T32	3
values[2]	498	1			T22	18		T124	35		T136	1
values[3]	560	1			T7	1		T35	6		T36	25
values[4]	604	1			T2	9		T11	4		T12	9
values[5]	636	1			T2	18		T5	2		T8	1
values[6]	633	1			T1	4		T5	32		T29	2
values[7]	632	1			T8	1		T152	20		T153	1
values[8]	3085	1			T3	37		T5	13		T10	4
values[9]	940	1			T4	12		T12	3		T22	7
minimum	14327	1			T1	11		T6	125		T8	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	569	1			T4	15		T22	18		T134	1
values[1]	636	1			T124	35		T232	8		T136	1
values[2]	578	1			T2	9		T7	1		T35	6
values[3]	569	1			T11	4		T12	9		T36	18
values[4]	539	1			T1	4		T2	18		T5	2
values[5]	665	1			T5	32		T125	22		T170	20
values[6]	3062	1			T3	37		T8	1		T24	24
values[7]	681	1			T5	13		T10	4		T12	1
values[8]	949	1			T4	12		T12	3		T22	7
values[9]	158	1			T170	17		T31	1		T13	5
minimum	14490	1			T1	11		T6	125		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

3827

1

T1

1

T2

24

T5

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T22	18		T137	1		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	1		T134	1		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T146	8		T222	13		T282	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T124	18		T232	8		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	9		T7	1		T35	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T35	1		T36	14		T143	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	3		T12	1		T36	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T165	1		T230	1		T281	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	3		T2	18		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	1		T22	15		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T170	8		T196	26		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	16		T125	10		T170	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1520	1			T3	3		T8	1		T24	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T152	10		T154	15		T144	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	7		T10	1		T30	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	1		T124	5		T125	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	1		T29	10		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	1		T22	7		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T170	17		T31	1		T13	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T275	1		T218	9		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14244	1			T1	9		T6	125		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T23	22		T224	2		T212	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T154	13		T158	5		T219	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	14		T145	11		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T146	7		T222	9		T282	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T124	17		T221	11		T129	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T89	1		T236	7		T225	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T36	11		T143	10		T236	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T11	1		T12	8		T36	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T165	14		T97	17		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	1		T29	1		T127	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T5	1		T231	6		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T132	5		T151	12		T231	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	16		T125	12		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1123	1			T3	34		T28	9		T180	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T152	19		T154	4		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	6		T10	3		T30	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T125	20		T127	2		T143	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	2		T29	10		T125	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T4	11		T152	3		T221	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T223	11		T235	11		T250	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T275	7		T218	10		T321	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T1	2		T8	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T224	21		T212	8		T160	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T29	10		T136	1		T170	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T223	1		T287	5		T190	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T23	22		T280	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T32	3		T215	1		T154	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	1		T134	1		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T22	18		T137	1		T146	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T124	18		T136	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	1		T35	5		T281	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T35	1		T36	14		T232	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	9		T11	3		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T165	1		T230	1		T281	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	18		T8	1		T36	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	1		T22	15		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	3		T29	1		T170	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	16		T125	10		T170	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T8	1		T215	1		T144	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T152	8		T153	1		T154	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T3	3		T5	7		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	1		T124	5		T125	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	1		T125	13		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	1		T22	7		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14235	1			T1	9		T6	125		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T29	10		T143	5		T235	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T223	9		T287	1		T190	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T154	13		T158	5		T219	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	14		T145	11		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T146	7		T282	13		T72	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T124	17		T221	11		T129	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T222	9		T225	5		T277	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T36	11		T143	10		T150	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	1		T12	8		T127	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T165	14		T97	17		T151	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T36	7		T127	8		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	1		T231	6		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T1	1		T29	1		T132	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	16		T125	12		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T144	6		T150	1		T151	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T152	12		T154	4		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1118	1			T3	34		T5	6		T10	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T125	11		T152	7		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	2		T125	7		T221	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	11		T125	9		T127	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T8	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T22	1		T137	1		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	15		T134	1		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T146	8		T222	10		T282	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T124	19		T232	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	1		T7	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T35	1		T36	12		T143	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	3		T12	9		T36	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T165	15		T230	1		T281	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	3		T2	2		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	2		T22	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T170	1		T196	1		T132	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	17		T125	13		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T3	37		T8	1		T24	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T152	21		T154	5		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	7		T10	4		T30	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T124	1		T125	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	3		T29	11		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T4	12		T22	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T170	1		T31	1		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T275	8		T218	11		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14334	1			T1	11		T6	125		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T23	1		T224	23		T212	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T22	17		T154	6		T241	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T145	11		T18	1		T217	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T146	7		T222	12		T277	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T124	16		T232	7		T150	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	8		T35	4		T133	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	13		T143	10		T239	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	1		T36	10		T146	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T97	9		T151	8		T247	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	1		T2	16		T131	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T22	14		T231	6		T248	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T170	7		T196	25		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	15		T125	9		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T24	22		T246	36		T238	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T152	8		T154	14		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	6		T30	13		T251	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T124	4		T125	21		T143	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T29	9		T125	12		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T22	6		T152	9		T147	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T170	16		T13	1		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T218	8		T322	5		T321	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T323	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T23	21		T212	8		T160	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T29	11		T136	1		T170	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T223	10		T287	4		T190	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T23	1		T280	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	3		T215	1		T154	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	15		T134	1		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T22	1		T137	1		T146	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T124	19		T136	1		T221	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T35	1		T281	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T35	1		T36	12		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	1		T11	3		T12	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T165	15		T230	1		T281	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	2		T8	1		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	2		T22	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	3		T29	2		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	17		T125	13		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	1		T215	1		T144	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T152	13		T153	1		T154	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T3	37		T5	7		T10	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T124	1		T125	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T12	3		T125	8		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T4	12		T22	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T1	11		T6	125		T8	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T29	9		T170	16		T143	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T287	2		T190	12		T300	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T23	21		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T154	6		T241	9		T158	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T145	11		T18	1		T212	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T22	17		T146	7		T285	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T124	16		T233	12		T217	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T35	4		T241	7		T222	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T36	13		T232	7		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	8		T11	1		T133	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T97	9		T151	8		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	16		T36	10		T131	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T22	14		T231	6		T248	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	1		T170	7		T196	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	15		T125	9		T170	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T144	3		T150	10		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T152	7		T154	14		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T5	6		T24	22		T246	36
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T124	4		T125	14		T152	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T125	12		T131	7		T240	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T22	6		T125	7		T152	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T1

14

T2

3

T3

37

auto[1]

auto[0]

3827

1

T1

1

T2

24

T5

21