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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 99.07 96.67 100.00 100.00 98.83 98.33 90.77


Total test records in report: 920
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T795 /workspace/coverage/default/10.adc_ctrl_smoke.2505817553 Aug 15 06:20:09 PM PDT 24 Aug 15 06:20:23 PM PDT 24 5747233086 ps
T796 /workspace/coverage/default/18.adc_ctrl_alert_test.1637401865 Aug 15 06:20:45 PM PDT 24 Aug 15 06:20:46 PM PDT 24 480985492 ps
T797 /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.744576160 Aug 15 06:21:02 PM PDT 24 Aug 15 06:33:28 PM PDT 24 325197400311 ps
T798 /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.91315694 Aug 15 06:21:03 PM PDT 24 Aug 15 06:22:43 PM PDT 24 165337909965 ps
T228 /workspace/coverage/default/41.adc_ctrl_filters_both.1381297272 Aug 15 06:23:37 PM PDT 24 Aug 15 06:42:30 PM PDT 24 495897268398 ps
T50 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.440814728 Aug 15 05:24:19 PM PDT 24 Aug 15 05:24:23 PM PDT 24 536906696 ps
T103 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.76337783 Aug 15 05:24:33 PM PDT 24 Aug 15 05:24:34 PM PDT 24 502925497 ps
T44 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2907119040 Aug 15 05:24:33 PM PDT 24 Aug 15 05:24:37 PM PDT 24 3948725821 ps
T104 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2699603720 Aug 15 05:24:46 PM PDT 24 Aug 15 05:24:47 PM PDT 24 432302606 ps
T51 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2685456927 Aug 15 05:24:34 PM PDT 24 Aug 15 05:24:37 PM PDT 24 733973409 ps
T56 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3172148560 Aug 15 05:24:46 PM PDT 24 Aug 15 05:24:50 PM PDT 24 478305964 ps
T799 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2657156647 Aug 15 05:24:52 PM PDT 24 Aug 15 05:24:54 PM PDT 24 450218375 ps
T105 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2300036012 Aug 15 05:24:13 PM PDT 24 Aug 15 05:24:15 PM PDT 24 1237052506 ps
T62 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2690870785 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:49 PM PDT 24 489108387 ps
T47 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.660966731 Aug 15 05:24:29 PM PDT 24 Aug 15 05:24:32 PM PDT 24 4602804094 ps
T57 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2203802121 Aug 15 05:24:36 PM PDT 24 Aug 15 05:24:38 PM PDT 24 689498667 ps
T800 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.271046835 Aug 15 05:24:42 PM PDT 24 Aug 15 05:24:43 PM PDT 24 509182528 ps
T801 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1590959165 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:49 PM PDT 24 309675587 ps
T106 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4121618213 Aug 15 05:24:19 PM PDT 24 Aug 15 05:24:20 PM PDT 24 1270612121 ps
T802 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.702015595 Aug 15 05:24:58 PM PDT 24 Aug 15 05:25:00 PM PDT 24 429444006 ps
T61 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4210866436 Aug 15 05:24:38 PM PDT 24 Aug 15 05:24:41 PM PDT 24 358132651 ps
T101 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2005998992 Aug 15 05:24:29 PM PDT 24 Aug 15 05:24:31 PM PDT 24 325494590 ps
T803 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.435150410 Aug 15 05:24:54 PM PDT 24 Aug 15 05:24:55 PM PDT 24 368003097 ps
T78 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1655284001 Aug 15 05:24:17 PM PDT 24 Aug 15 05:24:19 PM PDT 24 500385945 ps
T107 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3130215023 Aug 15 05:24:39 PM PDT 24 Aug 15 05:24:40 PM PDT 24 342501252 ps
T48 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2841028332 Aug 15 05:24:16 PM PDT 24 Aug 15 05:24:20 PM PDT 24 4427324842 ps
T804 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2527505780 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:50 PM PDT 24 354204133 ps
T79 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2505279821 Aug 15 05:24:24 PM PDT 24 Aug 15 05:24:25 PM PDT 24 568719783 ps
T49 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.564158073 Aug 15 05:24:39 PM PDT 24 Aug 15 05:24:51 PM PDT 24 8644346584 ps
T123 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2220432916 Aug 15 05:24:10 PM PDT 24 Aug 15 05:24:12 PM PDT 24 709416251 ps
T119 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1247657942 Aug 15 05:24:32 PM PDT 24 Aug 15 05:24:34 PM PDT 24 473796935 ps
T45 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1020020574 Aug 15 05:24:11 PM PDT 24 Aug 15 05:24:21 PM PDT 24 27296507261 ps
T46 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.634588661 Aug 15 05:24:53 PM PDT 24 Aug 15 05:25:04 PM PDT 24 4921322230 ps
T120 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2659587764 Aug 15 05:24:43 PM PDT 24 Aug 15 05:25:02 PM PDT 24 4637393829 ps
T52 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1494218623 Aug 15 05:24:13 PM PDT 24 Aug 15 05:24:18 PM PDT 24 4268321400 ps
T805 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1832778812 Aug 15 05:24:52 PM PDT 24 Aug 15 05:24:53 PM PDT 24 402528822 ps
T121 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2700630298 Aug 15 05:24:37 PM PDT 24 Aug 15 05:24:38 PM PDT 24 586296068 ps
T102 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3527007492 Aug 15 05:24:33 PM PDT 24 Aug 15 05:24:35 PM PDT 24 523805225 ps
T806 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1441559868 Aug 15 05:24:54 PM PDT 24 Aug 15 05:24:56 PM PDT 24 529337214 ps
T807 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1404604441 Aug 15 05:24:16 PM PDT 24 Aug 15 05:24:17 PM PDT 24 428764584 ps
T108 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3180282288 Aug 15 05:24:39 PM PDT 24 Aug 15 05:24:41 PM PDT 24 345005892 ps
T808 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3645623524 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:51 PM PDT 24 433804631 ps
T347 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.127399829 Aug 15 05:24:43 PM PDT 24 Aug 15 05:24:55 PM PDT 24 4389120972 ps
T809 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1722408934 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:50 PM PDT 24 403207523 ps
T109 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1686074255 Aug 15 05:24:15 PM PDT 24 Aug 15 05:24:17 PM PDT 24 476726642 ps
T810 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3339993565 Aug 15 05:24:39 PM PDT 24 Aug 15 05:24:40 PM PDT 24 623307633 ps
T811 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.384640506 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:50 PM PDT 24 406487788 ps
T812 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2123714341 Aug 15 05:24:35 PM PDT 24 Aug 15 05:24:36 PM PDT 24 382029119 ps
T813 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3575981685 Aug 15 05:24:14 PM PDT 24 Aug 15 05:24:15 PM PDT 24 512830168 ps
T122 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.401957793 Aug 15 05:24:30 PM PDT 24 Aug 15 05:24:40 PM PDT 24 4171192406 ps
T814 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3567966732 Aug 15 05:24:20 PM PDT 24 Aug 15 05:24:21 PM PDT 24 810284934 ps
T815 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2751461257 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:50 PM PDT 24 327471859 ps
T816 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2686945990 Aug 15 05:24:51 PM PDT 24 Aug 15 05:24:52 PM PDT 24 341144321 ps
T817 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.465198164 Aug 15 05:24:12 PM PDT 24 Aug 15 05:24:15 PM PDT 24 417839711 ps
T818 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.483464677 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:48 PM PDT 24 523298852 ps
T819 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3142072507 Aug 15 05:24:09 PM PDT 24 Aug 15 05:24:10 PM PDT 24 384879331 ps
T820 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1593425105 Aug 15 05:24:21 PM PDT 24 Aug 15 05:24:33 PM PDT 24 4837959456 ps
T821 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1678410285 Aug 15 05:24:53 PM PDT 24 Aug 15 05:24:54 PM PDT 24 447337604 ps
T822 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3200323141 Aug 15 05:24:51 PM PDT 24 Aug 15 05:25:02 PM PDT 24 2463800622 ps
T823 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.18516570 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:52 PM PDT 24 510488267 ps
T348 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4165275726 Aug 15 05:24:23 PM PDT 24 Aug 15 05:24:30 PM PDT 24 8328386243 ps
T110 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1187972766 Aug 15 05:24:15 PM PDT 24 Aug 15 05:24:16 PM PDT 24 310407762 ps
T63 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1265279130 Aug 15 05:24:28 PM PDT 24 Aug 15 05:24:34 PM PDT 24 8904242159 ps
T824 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3933120151 Aug 15 05:24:38 PM PDT 24 Aug 15 05:24:44 PM PDT 24 4474112786 ps
T825 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3596712053 Aug 15 05:24:38 PM PDT 24 Aug 15 05:24:39 PM PDT 24 394626227 ps
T826 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2121242271 Aug 15 05:24:24 PM PDT 24 Aug 15 05:24:25 PM PDT 24 355506185 ps
T827 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2912014967 Aug 15 05:24:37 PM PDT 24 Aug 15 05:24:38 PM PDT 24 416903594 ps
T828 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.931658449 Aug 15 05:24:29 PM PDT 24 Aug 15 05:24:30 PM PDT 24 488934520 ps
T111 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3270153987 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:49 PM PDT 24 451747016 ps
T829 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3648382396 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:50 PM PDT 24 594012733 ps
T830 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2720580269 Aug 15 05:24:46 PM PDT 24 Aug 15 05:24:47 PM PDT 24 419020202 ps
T831 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3173987002 Aug 15 05:24:39 PM PDT 24 Aug 15 05:24:40 PM PDT 24 733689715 ps
T832 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.41636373 Aug 15 05:24:34 PM PDT 24 Aug 15 05:24:36 PM PDT 24 329337892 ps
T833 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.142445592 Aug 15 05:24:45 PM PDT 24 Aug 15 05:24:52 PM PDT 24 4243881751 ps
T834 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3895524922 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:50 PM PDT 24 378741805 ps
T835 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1348215458 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:49 PM PDT 24 404742305 ps
T836 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1994147934 Aug 15 05:24:28 PM PDT 24 Aug 15 05:24:29 PM PDT 24 334662244 ps
T837 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3194219841 Aug 15 05:24:39 PM PDT 24 Aug 15 05:24:42 PM PDT 24 720359021 ps
T838 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1095720819 Aug 15 05:24:31 PM PDT 24 Aug 15 05:24:34 PM PDT 24 2451993615 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.848784726 Aug 15 05:24:22 PM PDT 24 Aug 15 05:24:23 PM PDT 24 363115723 ps
T839 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3229463639 Aug 15 05:24:40 PM PDT 24 Aug 15 05:24:42 PM PDT 24 517572180 ps
T840 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2231297566 Aug 15 05:24:24 PM PDT 24 Aug 15 05:24:26 PM PDT 24 530931548 ps
T841 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4222508279 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:49 PM PDT 24 351041231 ps
T842 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1767474493 Aug 15 05:24:45 PM PDT 24 Aug 15 05:24:52 PM PDT 24 4542929809 ps
T843 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2967647457 Aug 15 05:24:22 PM PDT 24 Aug 15 05:24:25 PM PDT 24 556899900 ps
T844 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1642167079 Aug 15 05:24:21 PM PDT 24 Aug 15 05:24:27 PM PDT 24 3772459414 ps
T845 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3061683739 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:49 PM PDT 24 478226219 ps
T846 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2580479810 Aug 15 05:24:31 PM PDT 24 Aug 15 05:24:33 PM PDT 24 377940352 ps
T847 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2412902983 Aug 15 05:24:17 PM PDT 24 Aug 15 05:24:18 PM PDT 24 326205672 ps
T848 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1651103952 Aug 15 05:24:37 PM PDT 24 Aug 15 05:24:38 PM PDT 24 344810479 ps
T849 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2573662952 Aug 15 05:24:39 PM PDT 24 Aug 15 05:24:42 PM PDT 24 466282583 ps
T113 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2325057222 Aug 15 05:25:10 PM PDT 24 Aug 15 05:25:17 PM PDT 24 23914666412 ps
T850 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.820288705 Aug 15 05:24:45 PM PDT 24 Aug 15 05:24:49 PM PDT 24 4582132196 ps
T851 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.159810437 Aug 15 05:24:29 PM PDT 24 Aug 15 05:24:34 PM PDT 24 4549122077 ps
T852 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3516958522 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:51 PM PDT 24 333455327 ps
T853 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2856037575 Aug 15 05:24:14 PM PDT 24 Aug 15 05:24:56 PM PDT 24 53147923803 ps
T854 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.680117789 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:53 PM PDT 24 2957361918 ps
T855 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.677802054 Aug 15 05:24:39 PM PDT 24 Aug 15 05:24:41 PM PDT 24 3770051040 ps
T856 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3808274506 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:54 PM PDT 24 8841318553 ps
T857 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.358380994 Aug 15 05:24:11 PM PDT 24 Aug 15 05:24:24 PM PDT 24 4715403940 ps
T858 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2627152213 Aug 15 05:24:46 PM PDT 24 Aug 15 05:24:48 PM PDT 24 523941415 ps
T859 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.749308760 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:51 PM PDT 24 448735849 ps
T860 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1686997509 Aug 15 05:24:26 PM PDT 24 Aug 15 05:24:28 PM PDT 24 408338237 ps
T114 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4288355215 Aug 15 05:24:15 PM PDT 24 Aug 15 05:24:19 PM PDT 24 681010672 ps
T861 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1224797695 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:50 PM PDT 24 473542321 ps
T862 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.708871308 Aug 15 05:24:32 PM PDT 24 Aug 15 05:24:35 PM PDT 24 2914956819 ps
T863 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2306217684 Aug 15 05:24:12 PM PDT 24 Aug 15 05:24:17 PM PDT 24 1863429906 ps
T864 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1396265943 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:50 PM PDT 24 5247478336 ps
T865 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3731922613 Aug 15 05:24:52 PM PDT 24 Aug 15 05:24:54 PM PDT 24 533080259 ps
T866 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2471475545 Aug 15 05:24:26 PM PDT 24 Aug 15 05:24:28 PM PDT 24 512523233 ps
T867 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1859638613 Aug 15 05:24:38 PM PDT 24 Aug 15 05:24:40 PM PDT 24 363396532 ps
T868 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1605588872 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:50 PM PDT 24 471607405 ps
T869 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4208731754 Aug 15 05:24:30 PM PDT 24 Aug 15 05:24:31 PM PDT 24 3217094886 ps
T118 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1346636262 Aug 15 05:24:17 PM PDT 24 Aug 15 05:24:18 PM PDT 24 438062999 ps
T870 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.942374250 Aug 15 05:24:44 PM PDT 24 Aug 15 05:24:45 PM PDT 24 393343803 ps
T871 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1942004509 Aug 15 05:24:31 PM PDT 24 Aug 15 05:24:33 PM PDT 24 372673735 ps
T872 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3762618858 Aug 15 05:24:21 PM PDT 24 Aug 15 05:24:23 PM PDT 24 621535411 ps
T873 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2076614622 Aug 15 05:24:54 PM PDT 24 Aug 15 05:24:55 PM PDT 24 374677067 ps
T874 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3417406272 Aug 15 05:24:31 PM PDT 24 Aug 15 05:24:37 PM PDT 24 4474192274 ps
T349 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1307065053 Aug 15 05:24:21 PM PDT 24 Aug 15 05:24:34 PM PDT 24 8550541074 ps
T875 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2875597357 Aug 15 05:24:53 PM PDT 24 Aug 15 05:24:54 PM PDT 24 447793217 ps
T876 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2365826631 Aug 15 05:24:28 PM PDT 24 Aug 15 05:24:30 PM PDT 24 542857700 ps
T877 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4226138908 Aug 15 05:24:14 PM PDT 24 Aug 15 05:24:16 PM PDT 24 770643809 ps
T115 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4086143819 Aug 15 05:24:09 PM PDT 24 Aug 15 05:24:11 PM PDT 24 369494463 ps
T878 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1856568947 Aug 15 05:24:40 PM PDT 24 Aug 15 05:24:41 PM PDT 24 318311015 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.740169193 Aug 15 05:24:10 PM PDT 24 Aug 15 05:24:12 PM PDT 24 1641206266 ps
T880 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4019806665 Aug 15 05:24:38 PM PDT 24 Aug 15 05:24:40 PM PDT 24 464827789 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.620946717 Aug 15 05:24:34 PM PDT 24 Aug 15 05:24:35 PM PDT 24 471481416 ps
T116 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2809985123 Aug 15 05:24:38 PM PDT 24 Aug 15 05:24:40 PM PDT 24 685011763 ps
T882 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2461647761 Aug 15 05:24:43 PM PDT 24 Aug 15 05:24:44 PM PDT 24 322980155 ps
T883 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2607049982 Aug 15 05:24:10 PM PDT 24 Aug 15 05:24:13 PM PDT 24 475107145 ps
T884 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1657593191 Aug 15 05:24:16 PM PDT 24 Aug 15 05:24:20 PM PDT 24 315619524 ps
T885 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.973643812 Aug 15 05:24:28 PM PDT 24 Aug 15 05:24:39 PM PDT 24 4194128384 ps
T886 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4183284957 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:50 PM PDT 24 297919605 ps
T887 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2402085857 Aug 15 05:24:40 PM PDT 24 Aug 15 05:24:41 PM PDT 24 445899217 ps
T888 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1706639663 Aug 15 05:24:44 PM PDT 24 Aug 15 05:25:05 PM PDT 24 8334695630 ps
T889 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1694361361 Aug 15 05:24:14 PM PDT 24 Aug 15 05:24:25 PM PDT 24 8455427367 ps
T890 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2818688541 Aug 15 05:24:18 PM PDT 24 Aug 15 05:24:21 PM PDT 24 981972807 ps
T891 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.928034961 Aug 15 05:24:24 PM PDT 24 Aug 15 05:24:26 PM PDT 24 491789219 ps
T892 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.28163384 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:51 PM PDT 24 514410153 ps
T893 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1298300306 Aug 15 05:24:23 PM PDT 24 Aug 15 05:24:43 PM PDT 24 5128472453 ps
T117 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2802306922 Aug 15 05:24:35 PM PDT 24 Aug 15 05:24:36 PM PDT 24 504666491 ps
T894 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3230809549 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:02 PM PDT 24 519270919 ps
T895 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3105686239 Aug 15 05:24:09 PM PDT 24 Aug 15 05:24:13 PM PDT 24 2094789337 ps
T896 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4284163664 Aug 15 05:24:24 PM PDT 24 Aug 15 05:24:26 PM PDT 24 559056365 ps
T897 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.314441611 Aug 15 05:24:28 PM PDT 24 Aug 15 05:24:32 PM PDT 24 4280382755 ps
T898 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.165737343 Aug 15 05:24:24 PM PDT 24 Aug 15 05:24:28 PM PDT 24 725007492 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2394064996 Aug 15 05:24:14 PM PDT 24 Aug 15 05:24:14 PM PDT 24 404226452 ps
T900 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3969383685 Aug 15 05:24:29 PM PDT 24 Aug 15 05:25:01 PM PDT 24 52630315487 ps
T901 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3870297987 Aug 15 05:24:33 PM PDT 24 Aug 15 05:24:34 PM PDT 24 493050568 ps
T346 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2112550862 Aug 15 05:24:40 PM PDT 24 Aug 15 05:25:02 PM PDT 24 8085362915 ps
T902 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3015247424 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:50 PM PDT 24 372475621 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4004220248 Aug 15 05:24:10 PM PDT 24 Aug 15 05:24:11 PM PDT 24 344832985 ps
T904 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1064303931 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:52 PM PDT 24 282626060 ps
T905 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.335901079 Aug 15 05:24:47 PM PDT 24 Aug 15 05:24:48 PM PDT 24 475722279 ps
T906 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.372445803 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:50 PM PDT 24 487844172 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.91884591 Aug 15 05:24:30 PM PDT 24 Aug 15 05:24:32 PM PDT 24 557252626 ps
T908 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.334499536 Aug 15 05:24:54 PM PDT 24 Aug 15 05:24:56 PM PDT 24 491654816 ps
T909 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3141989741 Aug 15 05:24:40 PM PDT 24 Aug 15 05:24:42 PM PDT 24 483009661 ps
T910 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3875051014 Aug 15 05:24:46 PM PDT 24 Aug 15 05:24:47 PM PDT 24 350006471 ps
T911 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4043151847 Aug 15 05:24:46 PM PDT 24 Aug 15 05:24:49 PM PDT 24 2358533050 ps
T912 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1241740822 Aug 15 05:24:23 PM PDT 24 Aug 15 05:24:25 PM PDT 24 628477281 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4135690380 Aug 15 05:24:11 PM PDT 24 Aug 15 05:24:30 PM PDT 24 4628172274 ps
T914 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.146682191 Aug 15 05:24:46 PM PDT 24 Aug 15 05:24:47 PM PDT 24 326023370 ps
T915 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.558712394 Aug 15 05:24:11 PM PDT 24 Aug 15 05:24:13 PM PDT 24 822084258 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.284148603 Aug 15 05:24:23 PM PDT 24 Aug 15 05:24:24 PM PDT 24 596441703 ps
T917 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4135068470 Aug 15 05:24:16 PM PDT 24 Aug 15 05:24:18 PM PDT 24 1230945853 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.545597736 Aug 15 05:24:28 PM PDT 24 Aug 15 05:24:32 PM PDT 24 10125919026 ps
T919 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2418893905 Aug 15 05:24:10 PM PDT 24 Aug 15 05:24:13 PM PDT 24 520562612 ps
T920 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3756096082 Aug 15 05:24:43 PM PDT 24 Aug 15 05:24:45 PM PDT 24 419446787 ps

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.397970956
Short name T5
Test name
Test status
Simulation time 506358701480 ps
CPU time 898.45 seconds
Started Aug 15 06:22:25 PM PDT 24
Finished Aug 15 06:37:24 PM PDT 24
Peak memory 202120 kb
Host smart-44689c06-8435-4a7e-b684-1adbcfa0bd6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397970956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.397970956
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3724140434
Short name T6
Test name
Test status
Simulation time 80055226802 ps
CPU time 366.9 seconds
Started Aug 15 06:20:24 PM PDT 24
Finished Aug 15 06:26:31 PM PDT 24
Peak memory 202424 kb
Host smart-7c9edf3f-b4aa-4385-bd93-34d81d7d52a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724140434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3724140434
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.899222387
Short name T11
Test name
Test status
Simulation time 13628350282 ps
CPU time 8.12 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:20:27 PM PDT 24
Peak memory 210508 kb
Host smart-73d8a0da-5612-4d69-aee1-0d6178013ba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899222387 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.899222387
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.391675421
Short name T125
Test name
Test status
Simulation time 723302054466 ps
CPU time 258.08 seconds
Started Aug 15 06:21:52 PM PDT 24
Finished Aug 15 06:26:10 PM PDT 24
Peak memory 202108 kb
Host smart-ed0fef68-57a5-47aa-a014-17ea1c31e921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391675421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
391675421
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1970905937
Short name T152
Test name
Test status
Simulation time 519489033671 ps
CPU time 272.36 seconds
Started Aug 15 06:21:10 PM PDT 24
Finished Aug 15 06:25:42 PM PDT 24
Peak memory 202124 kb
Host smart-5c8a675e-7e32-4770-b252-b2c17645fb4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970905937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1970905937
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.836738425
Short name T22
Test name
Test status
Simulation time 529249842883 ps
CPU time 1175.48 seconds
Started Aug 15 06:20:13 PM PDT 24
Finished Aug 15 06:39:49 PM PDT 24
Peak memory 202132 kb
Host smart-1c1f4981-2352-4932-aa73-cc49b0b8f36e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836738425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.836738425
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1874063655
Short name T151
Test name
Test status
Simulation time 521500693887 ps
CPU time 1202.16 seconds
Started Aug 15 06:20:31 PM PDT 24
Finished Aug 15 06:40:33 PM PDT 24
Peak memory 202144 kb
Host smart-83531bde-76bf-4ec5-b936-80fb5ada8cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874063655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1874063655
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.215284943
Short name T154
Test name
Test status
Simulation time 578988128543 ps
CPU time 348.5 seconds
Started Aug 15 06:20:16 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 202188 kb
Host smart-af7c054e-51e3-491c-95ee-6e3bb5733b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215284943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.215284943
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3371173597
Short name T36
Test name
Test status
Simulation time 344247292955 ps
CPU time 747.64 seconds
Started Aug 15 06:24:22 PM PDT 24
Finished Aug 15 06:36:50 PM PDT 24
Peak memory 202120 kb
Host smart-79147ff6-b6d7-4558-a5f1-4e0386048f7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371173597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3371173597
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3171239028
Short name T43
Test name
Test status
Simulation time 119838398597 ps
CPU time 343.54 seconds
Started Aug 15 06:22:53 PM PDT 24
Finished Aug 15 06:28:37 PM PDT 24
Peak memory 202392 kb
Host smart-6ae2a114-e4ce-45a1-a7a1-9695af8e1811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171239028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3171239028
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3172148560
Short name T56
Test name
Test status
Simulation time 478305964 ps
CPU time 3.43 seconds
Started Aug 15 05:24:46 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 217092 kb
Host smart-c49cb251-b1fd-4d35-b461-4117c539203e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172148560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3172148560
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.4257118141
Short name T150
Test name
Test status
Simulation time 525909547182 ps
CPU time 1154.43 seconds
Started Aug 15 06:23:24 PM PDT 24
Finished Aug 15 06:42:39 PM PDT 24
Peak memory 202116 kb
Host smart-f2735958-2f2c-45cd-a123-925e714e636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257118141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.4257118141
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1121304641
Short name T38
Test name
Test status
Simulation time 98047923201 ps
CPU time 325.79 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:25:44 PM PDT 24
Peak memory 202372 kb
Host smart-e139be8a-005d-485a-ad34-305983c69137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121304641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1121304641
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.4135137815
Short name T143
Test name
Test status
Simulation time 513400640395 ps
CPU time 1244.92 seconds
Started Aug 15 06:23:37 PM PDT 24
Finished Aug 15 06:44:22 PM PDT 24
Peak memory 202124 kb
Host smart-a601aa97-7f19-496e-9660-8a362e262f20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135137815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.4135137815
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2472876191
Short name T4
Test name
Test status
Simulation time 324119535438 ps
CPU time 257.53 seconds
Started Aug 15 06:22:10 PM PDT 24
Finished Aug 15 06:26:28 PM PDT 24
Peak memory 202088 kb
Host smart-ea6aab89-6200-4c0b-9a40-0c475f2f0a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472876191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2472876191
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2894041226
Short name T127
Test name
Test status
Simulation time 487342658382 ps
CPU time 251.58 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:24:22 PM PDT 24
Peak memory 202128 kb
Host smart-e778ad98-4a56-42de-8a42-7cd5bf03f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894041226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2894041226
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2447710429
Short name T64
Test name
Test status
Simulation time 441527734 ps
CPU time 1.57 seconds
Started Aug 15 06:20:30 PM PDT 24
Finished Aug 15 06:20:31 PM PDT 24
Peak memory 201988 kb
Host smart-e40a035f-e720-4b61-a60e-9c35342dcbb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447710429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2447710429
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2089477896
Short name T144
Test name
Test status
Simulation time 328612149892 ps
CPU time 184.8 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:23:24 PM PDT 24
Peak memory 202116 kb
Host smart-5ce79440-9695-48c1-ae35-fd8585403448
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089477896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2089477896
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1771109691
Short name T55
Test name
Test status
Simulation time 7854825335 ps
CPU time 4.04 seconds
Started Aug 15 06:19:59 PM PDT 24
Finished Aug 15 06:20:03 PM PDT 24
Peak memory 218572 kb
Host smart-f82d4778-601d-4ee0-8847-35e0112792c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771109691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1771109691
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3123176568
Short name T274
Test name
Test status
Simulation time 570610348396 ps
CPU time 613.69 seconds
Started Aug 15 06:20:07 PM PDT 24
Finished Aug 15 06:30:21 PM PDT 24
Peak memory 202088 kb
Host smart-15735b94-41b7-46d8-a18d-fce021aa01ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123176568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3123176568
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2699603720
Short name T104
Test name
Test status
Simulation time 432302606 ps
CPU time 1.01 seconds
Started Aug 15 05:24:46 PM PDT 24
Finished Aug 15 05:24:47 PM PDT 24
Peak memory 200868 kb
Host smart-58bb7f6c-5c74-4d42-9220-026dc74a3d46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699603720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2699603720
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3821831189
Short name T12
Test name
Test status
Simulation time 492327199327 ps
CPU time 255.71 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:25:09 PM PDT 24
Peak memory 202068 kb
Host smart-8f89a344-667f-4764-bde5-c92d9545a5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821831189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3821831189
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.623075036
Short name T142
Test name
Test status
Simulation time 676274043577 ps
CPU time 826.87 seconds
Started Aug 15 06:20:20 PM PDT 24
Finished Aug 15 06:34:07 PM PDT 24
Peak memory 202132 kb
Host smart-dd568ac8-f6fd-45a9-8e90-ffcbbbdb7b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623075036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
623075036
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.759064743
Short name T290
Test name
Test status
Simulation time 515593305983 ps
CPU time 246.86 seconds
Started Aug 15 06:20:20 PM PDT 24
Finished Aug 15 06:24:27 PM PDT 24
Peak memory 202180 kb
Host smart-9c2b503e-509b-43a6-8c93-cb2cc96527db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759064743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.759064743
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1783243149
Short name T244
Test name
Test status
Simulation time 626040203968 ps
CPU time 1470.3 seconds
Started Aug 15 06:20:38 PM PDT 24
Finished Aug 15 06:45:09 PM PDT 24
Peak memory 202052 kb
Host smart-5a5a03a5-69bf-4b80-abcf-84589554b72b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783243149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1783243149
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.661046704
Short name T170
Test name
Test status
Simulation time 543339124224 ps
CPU time 313.14 seconds
Started Aug 15 06:20:14 PM PDT 24
Finished Aug 15 06:25:27 PM PDT 24
Peak memory 202112 kb
Host smart-6354650e-0dc6-4cc7-8524-eb81314534de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661046704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.661046704
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1650091433
Short name T146
Test name
Test status
Simulation time 346787065699 ps
CPU time 75.95 seconds
Started Aug 15 06:23:29 PM PDT 24
Finished Aug 15 06:24:45 PM PDT 24
Peak memory 202136 kb
Host smart-71613f2b-8907-4675-9647-49184f341793
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650091433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1650091433
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1430865545
Short name T224
Test name
Test status
Simulation time 495847033511 ps
CPU time 391.5 seconds
Started Aug 15 06:24:15 PM PDT 24
Finished Aug 15 06:30:47 PM PDT 24
Peak memory 202164 kb
Host smart-9b007682-23fb-49e3-bb12-3303a6ec0fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430865545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1430865545
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1902930287
Short name T167
Test name
Test status
Simulation time 491411369306 ps
CPU time 1165.24 seconds
Started Aug 15 06:23:45 PM PDT 24
Finished Aug 15 06:43:10 PM PDT 24
Peak memory 202064 kb
Host smart-d91185ba-9e21-47a2-ac12-cc85948ec3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902930287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1902930287
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1368212869
Short name T217
Test name
Test status
Simulation time 547978961477 ps
CPU time 1296.17 seconds
Started Aug 15 06:24:17 PM PDT 24
Finished Aug 15 06:45:53 PM PDT 24
Peak memory 202112 kb
Host smart-8d55b8ac-0ee8-410b-87ad-035525c05e71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368212869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1368212869
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1691891441
Short name T249
Test name
Test status
Simulation time 331618298176 ps
CPU time 58.82 seconds
Started Aug 15 06:19:54 PM PDT 24
Finished Aug 15 06:20:53 PM PDT 24
Peak memory 202124 kb
Host smart-1c69e633-bf18-4447-8e8d-079b2f49570a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691891441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1691891441
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2973623945
Short name T191
Test name
Test status
Simulation time 524593358871 ps
CPU time 239.21 seconds
Started Aug 15 06:20:09 PM PDT 24
Finished Aug 15 06:24:09 PM PDT 24
Peak memory 202112 kb
Host smart-09daa203-0793-4c65-a050-fb2190798bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973623945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2973623945
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2907119040
Short name T44
Test name
Test status
Simulation time 3948725821 ps
CPU time 3.33 seconds
Started Aug 15 05:24:33 PM PDT 24
Finished Aug 15 05:24:37 PM PDT 24
Peak memory 201124 kb
Host smart-d79ac731-e5ba-4f33-9964-ebda51a5d452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907119040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2907119040
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4165275726
Short name T348
Test name
Test status
Simulation time 8328386243 ps
CPU time 6.95 seconds
Started Aug 15 05:24:23 PM PDT 24
Finished Aug 15 05:24:30 PM PDT 24
Peak memory 201128 kb
Host smart-0da9199c-3ca0-486a-97f2-710015563d0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165275726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4165275726
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2836709137
Short name T210
Test name
Test status
Simulation time 349133792264 ps
CPU time 1329.76 seconds
Started Aug 15 06:19:58 PM PDT 24
Finished Aug 15 06:42:08 PM PDT 24
Peak memory 210604 kb
Host smart-63110f2f-163b-4c1b-9a05-1eea9d98a9c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836709137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2836709137
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1016290134
Short name T345
Test name
Test status
Simulation time 513517429566 ps
CPU time 279.16 seconds
Started Aug 15 06:23:36 PM PDT 24
Finished Aug 15 06:28:15 PM PDT 24
Peak memory 202108 kb
Host smart-a6fd6154-fbac-4e0f-8d16-3809a1b75517
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016290134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1016290134
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1497243524
Short name T128
Test name
Test status
Simulation time 486394854594 ps
CPU time 166.95 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:22:57 PM PDT 24
Peak memory 202124 kb
Host smart-74baa139-886b-406e-86ac-456d677d6bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497243524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1497243524
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4093452137
Short name T304
Test name
Test status
Simulation time 329321130382 ps
CPU time 772.29 seconds
Started Aug 15 06:24:43 PM PDT 24
Finished Aug 15 06:37:36 PM PDT 24
Peak memory 202152 kb
Host smart-fa28f21a-cc2b-4078-84dd-7ba793239828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093452137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4093452137
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3353432810
Short name T272
Test name
Test status
Simulation time 550697394749 ps
CPU time 1191.29 seconds
Started Aug 15 06:23:59 PM PDT 24
Finished Aug 15 06:43:50 PM PDT 24
Peak memory 202172 kb
Host smart-726b6534-dfe9-4985-954d-f640d590a3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353432810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3353432810
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3004510863
Short name T287
Test name
Test status
Simulation time 4590114152 ps
CPU time 6.86 seconds
Started Aug 15 06:20:19 PM PDT 24
Finished Aug 15 06:20:26 PM PDT 24
Peak memory 202240 kb
Host smart-9117cd7d-1fd6-4fd3-bdbb-7ea88532a2d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004510863 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3004510863
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1707699920
Short name T133
Test name
Test status
Simulation time 530861983456 ps
CPU time 1255.56 seconds
Started Aug 15 06:20:19 PM PDT 24
Finished Aug 15 06:41:15 PM PDT 24
Peak memory 202104 kb
Host smart-f0623026-73cf-4b9f-8803-f5c1fd1adf3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707699920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1707699920
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3677762
Short name T3
Test name
Test status
Simulation time 493204287212 ps
CPU time 1063.66 seconds
Started Aug 15 06:20:25 PM PDT 24
Finished Aug 15 06:38:09 PM PDT 24
Peak memory 202148 kb
Host smart-fba2f6cc-6c9b-400e-b333-33f329b9a629
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_
fixed.3677762
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1013168781
Short name T190
Test name
Test status
Simulation time 360974250607 ps
CPU time 284.49 seconds
Started Aug 15 06:20:07 PM PDT 24
Finished Aug 15 06:24:52 PM PDT 24
Peak memory 202052 kb
Host smart-5639d057-a6f4-4f71-985a-3f869da55653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013168781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1013168781
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2166043942
Short name T216
Test name
Test status
Simulation time 6770691399 ps
CPU time 8.96 seconds
Started Aug 15 06:21:09 PM PDT 24
Finished Aug 15 06:21:18 PM PDT 24
Peak memory 210380 kb
Host smart-c343d8a0-b98e-420d-9ac5-1044ba9cdeef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166043942 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2166043942
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1171163136
Short name T218
Test name
Test status
Simulation time 503638051904 ps
CPU time 419.69 seconds
Started Aug 15 06:22:26 PM PDT 24
Finished Aug 15 06:29:26 PM PDT 24
Peak memory 202200 kb
Host smart-0178e62c-a786-4771-b70a-a249863daf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171163136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1171163136
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3336255157
Short name T219
Test name
Test status
Simulation time 333223853827 ps
CPU time 127.93 seconds
Started Aug 15 06:20:52 PM PDT 24
Finished Aug 15 06:23:00 PM PDT 24
Peak memory 202140 kb
Host smart-fc7bba4e-a7e9-43ce-8eab-20ef6d962b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336255157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3336255157
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3039327666
Short name T317
Test name
Test status
Simulation time 165777373782 ps
CPU time 65.56 seconds
Started Aug 15 06:21:03 PM PDT 24
Finished Aug 15 06:22:08 PM PDT 24
Peak memory 202168 kb
Host smart-ecf4cdaa-90a0-4dd8-a6a1-475b21691b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039327666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3039327666
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3344922588
Short name T18
Test name
Test status
Simulation time 14163078166 ps
CPU time 19 seconds
Started Aug 15 06:21:53 PM PDT 24
Finished Aug 15 06:22:12 PM PDT 24
Peak memory 210712 kb
Host smart-0bf52445-64b3-49f4-ae54-40fc4b5b3c70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344922588 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3344922588
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.318357604
Short name T206
Test name
Test status
Simulation time 359041966797 ps
CPU time 984.22 seconds
Started Aug 15 06:22:30 PM PDT 24
Finished Aug 15 06:38:54 PM PDT 24
Peak memory 210496 kb
Host smart-203cdf72-e054-44a4-bd88-03396c557d76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318357604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
318357604
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.91389125
Short name T160
Test name
Test status
Simulation time 505930001331 ps
CPU time 164.84 seconds
Started Aug 15 06:22:01 PM PDT 24
Finished Aug 15 06:24:46 PM PDT 24
Peak memory 202180 kb
Host smart-02876b33-fd9b-4cb5-8a3f-364a0f7ca9ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91389125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gatin
g.91389125
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.793202747
Short name T256
Test name
Test status
Simulation time 362421541942 ps
CPU time 849.85 seconds
Started Aug 15 06:23:48 PM PDT 24
Finished Aug 15 06:37:58 PM PDT 24
Peak memory 202096 kb
Host smart-a04d732b-93f7-475e-9608-56a4ae385688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793202747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.793202747
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.103076422
Short name T89
Test name
Test status
Simulation time 33742673134 ps
CPU time 11.85 seconds
Started Aug 15 06:23:45 PM PDT 24
Finished Aug 15 06:23:57 PM PDT 24
Peak memory 212096 kb
Host smart-557ca742-4f61-4a8e-9518-0434a910a134
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103076422 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.103076422
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3721505352
Short name T250
Test name
Test status
Simulation time 547680736391 ps
CPU time 1271.17 seconds
Started Aug 15 06:20:05 PM PDT 24
Finished Aug 15 06:41:16 PM PDT 24
Peak memory 202188 kb
Host smart-bd96f092-948a-457d-9e5d-aa535d80789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721505352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3721505352
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.661559822
Short name T280
Test name
Test status
Simulation time 168181727745 ps
CPU time 99.94 seconds
Started Aug 15 06:21:46 PM PDT 24
Finished Aug 15 06:23:26 PM PDT 24
Peak memory 202124 kb
Host smart-356c602d-a721-4d4d-a838-75726c78a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661559822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.661559822
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1323640498
Short name T314
Test name
Test status
Simulation time 163959617112 ps
CPU time 94.03 seconds
Started Aug 15 06:23:57 PM PDT 24
Finished Aug 15 06:25:31 PM PDT 24
Peak memory 202116 kb
Host smart-f6c2e4ee-2bd6-46e2-a52d-4b00add7b26e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323640498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1323640498
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2573662952
Short name T849
Test name
Test status
Simulation time 466282583 ps
CPU time 3.11 seconds
Started Aug 15 05:24:39 PM PDT 24
Finished Aug 15 05:24:42 PM PDT 24
Peak memory 210348 kb
Host smart-4b69a553-92b0-43cc-8f5e-2acd8202c6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573662952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2573662952
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3665992814
Short name T265
Test name
Test status
Simulation time 183469445167 ps
CPU time 113.3 seconds
Started Aug 15 06:19:48 PM PDT 24
Finished Aug 15 06:21:41 PM PDT 24
Peak memory 202164 kb
Host smart-8e5c84bc-75a7-4f0a-ad00-e9a49593537f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665992814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3665992814
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3027091522
Short name T302
Test name
Test status
Simulation time 10322197702 ps
CPU time 19.2 seconds
Started Aug 15 06:19:55 PM PDT 24
Finished Aug 15 06:20:15 PM PDT 24
Peak memory 210648 kb
Host smart-6288d75f-1d15-459a-8e2d-5b7d26577ba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027091522 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3027091522
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.427351375
Short name T297
Test name
Test status
Simulation time 494082461242 ps
CPU time 235.43 seconds
Started Aug 15 06:22:46 PM PDT 24
Finished Aug 15 06:26:42 PM PDT 24
Peak memory 202152 kb
Host smart-c9843131-ae3e-4b19-b06f-89b7f051d554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427351375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.427351375
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.303119613
Short name T261
Test name
Test status
Simulation time 349598374694 ps
CPU time 808.29 seconds
Started Aug 15 06:20:16 PM PDT 24
Finished Aug 15 06:33:45 PM PDT 24
Peak memory 202080 kb
Host smart-940d6879-8ada-4f22-beeb-c7702791b8f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303119613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.303119613
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3988951058
Short name T199
Test name
Test status
Simulation time 117124889956 ps
CPU time 598.26 seconds
Started Aug 15 06:20:36 PM PDT 24
Finished Aug 15 06:30:34 PM PDT 24
Peak memory 202316 kb
Host smart-a01839cb-70c2-4b83-999f-2ca73fa975ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988951058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3988951058
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1852672366
Short name T313
Test name
Test status
Simulation time 547248693878 ps
CPU time 101.16 seconds
Started Aug 15 06:21:33 PM PDT 24
Finished Aug 15 06:23:14 PM PDT 24
Peak memory 202136 kb
Host smart-1de31dc2-5eef-4190-999e-1efc9ab9216d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852672366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1852672366
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.624218263
Short name T292
Test name
Test status
Simulation time 330947335129 ps
CPU time 169.77 seconds
Started Aug 15 06:21:45 PM PDT 24
Finished Aug 15 06:24:35 PM PDT 24
Peak memory 202124 kb
Host smart-aba36782-1b9a-4b94-b22c-c54025f39f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624218263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.624218263
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1190394990
Short name T308
Test name
Test status
Simulation time 11393419192 ps
CPU time 9.02 seconds
Started Aug 15 06:22:32 PM PDT 24
Finished Aug 15 06:22:41 PM PDT 24
Peak memory 210476 kb
Host smart-c9cd327c-66bd-47e6-8fe7-2121fdedd71d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190394990 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1190394990
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4148378001
Short name T271
Test name
Test status
Simulation time 490617145868 ps
CPU time 115.36 seconds
Started Aug 15 06:23:36 PM PDT 24
Finished Aug 15 06:25:31 PM PDT 24
Peak memory 202104 kb
Host smart-d74377e2-2243-4465-87d3-65420ef1c445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148378001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4148378001
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1265279130
Short name T63
Test name
Test status
Simulation time 8904242159 ps
CPU time 6.05 seconds
Started Aug 15 05:24:28 PM PDT 24
Finished Aug 15 05:24:34 PM PDT 24
Peak memory 201112 kb
Host smart-ed121226-ed85-4e76-9d94-9f2969b6a4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265279130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1265279130
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3220788414
Short name T301
Test name
Test status
Simulation time 495659769031 ps
CPU time 1189.74 seconds
Started Aug 15 06:20:26 PM PDT 24
Finished Aug 15 06:40:16 PM PDT 24
Peak memory 202088 kb
Host smart-8298e901-b678-40ca-a674-73f50eefdb2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220788414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3220788414
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.46327858
Short name T131
Test name
Test status
Simulation time 381710072542 ps
CPU time 89.51 seconds
Started Aug 15 06:20:35 PM PDT 24
Finished Aug 15 06:22:04 PM PDT 24
Peak memory 202128 kb
Host smart-e8daf142-c479-424a-8782-80c52de78681
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46327858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_w
akeup.46327858
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3276511685
Short name T319
Test name
Test status
Simulation time 77719163065 ps
CPU time 23.53 seconds
Started Aug 15 06:20:52 PM PDT 24
Finished Aug 15 06:21:15 PM PDT 24
Peak memory 210504 kb
Host smart-23b1b22c-4744-4ee2-8111-5652f4b2d3c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276511685 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3276511685
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1731514606
Short name T174
Test name
Test status
Simulation time 332023639885 ps
CPU time 795.42 seconds
Started Aug 15 06:22:15 PM PDT 24
Finished Aug 15 06:35:30 PM PDT 24
Peak memory 202140 kb
Host smart-6a8253cc-51b4-4efe-8638-b72b05bf0e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731514606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1731514606
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.4004639456
Short name T247
Test name
Test status
Simulation time 361451261189 ps
CPU time 210.55 seconds
Started Aug 15 06:23:57 PM PDT 24
Finished Aug 15 06:27:28 PM PDT 24
Peak memory 202136 kb
Host smart-6e82b0ec-c64b-4006-806e-efbeb4dd7ded
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004639456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.4004639456
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2609931613
Short name T201
Test name
Test status
Simulation time 79596921981 ps
CPU time 295.76 seconds
Started Aug 15 06:24:22 PM PDT 24
Finished Aug 15 06:29:18 PM PDT 24
Peak memory 202340 kb
Host smart-5f72ddb8-045f-4664-aa90-e98c573f59c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609931613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2609931613
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1494218623
Short name T52
Test name
Test status
Simulation time 4268321400 ps
CPU time 4.05 seconds
Started Aug 15 05:24:13 PM PDT 24
Finished Aug 15 05:24:18 PM PDT 24
Peak memory 201132 kb
Host smart-8d86efcc-353e-4092-847b-17c1a86ece15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494218623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1494218623
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1313322557
Short name T311
Test name
Test status
Simulation time 328164978538 ps
CPU time 181.08 seconds
Started Aug 15 06:19:49 PM PDT 24
Finished Aug 15 06:22:50 PM PDT 24
Peak memory 202120 kb
Host smart-5e474a41-ebdc-481d-944d-6d7d9013af96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313322557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1313322557
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3257666970
Short name T41
Test name
Test status
Simulation time 116050790707 ps
CPU time 574.58 seconds
Started Aug 15 06:20:19 PM PDT 24
Finished Aug 15 06:29:54 PM PDT 24
Peak memory 202372 kb
Host smart-f0127b46-ec87-407e-ae07-ff60f7644f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257666970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3257666970
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.350184841
Short name T614
Test name
Test status
Simulation time 529688706299 ps
CPU time 926.13 seconds
Started Aug 15 06:20:24 PM PDT 24
Finished Aug 15 06:35:50 PM PDT 24
Peak memory 212928 kb
Host smart-62f44870-6123-4c6c-adbc-b2ae356fb279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350184841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
350184841
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1167042875
Short name T335
Test name
Test status
Simulation time 269323200006 ps
CPU time 319.59 seconds
Started Aug 15 06:20:34 PM PDT 24
Finished Aug 15 06:25:54 PM PDT 24
Peak memory 202108 kb
Host smart-cfb0974d-9fb8-4fe7-b131-54dee303a7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167042875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1167042875
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3838638096
Short name T223
Test name
Test status
Simulation time 325967960997 ps
CPU time 532.08 seconds
Started Aug 15 06:20:36 PM PDT 24
Finished Aug 15 06:29:28 PM PDT 24
Peak memory 202052 kb
Host smart-854c3dcf-cdb7-4fb1-8934-48971eda7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838638096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3838638096
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3240783533
Short name T354
Test name
Test status
Simulation time 84007620211 ps
CPU time 338.26 seconds
Started Aug 15 06:21:00 PM PDT 24
Finished Aug 15 06:26:39 PM PDT 24
Peak memory 202316 kb
Host smart-76e4a19a-e686-4415-bdd0-3f68de23a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240783533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3240783533
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3189029167
Short name T350
Test name
Test status
Simulation time 88028333067 ps
CPU time 253.07 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:25:29 PM PDT 24
Peak memory 202376 kb
Host smart-077daaf6-0d8c-4b69-aa76-e1de9d5d881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189029167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3189029167
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1121422521
Short name T194
Test name
Test status
Simulation time 342864179700 ps
CPU time 196.93 seconds
Started Aug 15 06:21:30 PM PDT 24
Finished Aug 15 06:24:47 PM PDT 24
Peak memory 202124 kb
Host smart-20c22cfd-24ba-452c-b793-04a855530a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121422521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1121422521
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3511082379
Short name T323
Test name
Test status
Simulation time 180786662125 ps
CPU time 194.68 seconds
Started Aug 15 06:22:00 PM PDT 24
Finished Aug 15 06:25:15 PM PDT 24
Peak memory 202112 kb
Host smart-db3fdc52-02e7-459e-a8f3-87e9e8867eac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511082379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3511082379
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2214839595
Short name T40
Test name
Test status
Simulation time 111347766583 ps
CPU time 560.24 seconds
Started Aug 15 06:22:23 PM PDT 24
Finished Aug 15 06:31:43 PM PDT 24
Peak memory 202416 kb
Host smart-dd42eb12-29f1-4a51-950a-05c49405d74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214839595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2214839595
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.563132942
Short name T207
Test name
Test status
Simulation time 466354675255 ps
CPU time 437.12 seconds
Started Aug 15 06:23:17 PM PDT 24
Finished Aug 15 06:30:34 PM PDT 24
Peak memory 202396 kb
Host smart-0c6ea51b-9f8a-4a13-8af8-8a38ca1d440c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563132942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
563132942
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.338339347
Short name T23
Test name
Test status
Simulation time 201543781806 ps
CPU time 116.6 seconds
Started Aug 15 06:23:24 PM PDT 24
Finished Aug 15 06:25:21 PM PDT 24
Peak memory 202200 kb
Host smart-518dcbcf-6b9d-4f89-bd43-f56cb41e8c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338339347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
338339347
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1307739834
Short name T291
Test name
Test status
Simulation time 337561548221 ps
CPU time 397.43 seconds
Started Aug 15 06:23:24 PM PDT 24
Finished Aug 15 06:30:02 PM PDT 24
Peak memory 202124 kb
Host smart-bda012e9-f001-4c85-a3b8-05dafcc150af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307739834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1307739834
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2364387601
Short name T305
Test name
Test status
Simulation time 196931744061 ps
CPU time 112.28 seconds
Started Aug 15 06:24:27 PM PDT 24
Finished Aug 15 06:26:19 PM PDT 24
Peak memory 202184 kb
Host smart-f666f0ea-d331-448d-b97e-2c27f3eb7c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364387601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2364387601
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2219919006
Short name T296
Test name
Test status
Simulation time 176556782834 ps
CPU time 182.21 seconds
Started Aug 15 06:24:28 PM PDT 24
Finished Aug 15 06:27:30 PM PDT 24
Peak memory 202056 kb
Host smart-4a8faaed-3e94-4abb-acad-5d5eb1e0280f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219919006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2219919006
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.320152766
Short name T270
Test name
Test status
Simulation time 357608296630 ps
CPU time 203.99 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:23:34 PM PDT 24
Peak memory 202084 kb
Host smart-3e0f7e14-cfd5-41ef-9432-b6f599d34b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320152766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.320152766
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.558712394
Short name T915
Test name
Test status
Simulation time 822084258 ps
CPU time 2.06 seconds
Started Aug 15 05:24:11 PM PDT 24
Finished Aug 15 05:24:13 PM PDT 24
Peak memory 201324 kb
Host smart-283f3df3-91fa-4a19-8de9-c8d5961a9bfe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558712394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.558712394
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3105686239
Short name T895
Test name
Test status
Simulation time 2094789337 ps
CPU time 4.3 seconds
Started Aug 15 05:24:09 PM PDT 24
Finished Aug 15 05:24:13 PM PDT 24
Peak memory 200940 kb
Host smart-b5a015eb-c65a-4c08-a009-0a4b3201c1ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105686239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3105686239
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2220432916
Short name T123
Test name
Test status
Simulation time 709416251 ps
CPU time 2.19 seconds
Started Aug 15 05:24:10 PM PDT 24
Finished Aug 15 05:24:12 PM PDT 24
Peak memory 200932 kb
Host smart-fb101fc5-5c3e-49dc-b18e-333072798f81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220432916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2220432916
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.465198164
Short name T817
Test name
Test status
Simulation time 417839711 ps
CPU time 2.03 seconds
Started Aug 15 05:24:12 PM PDT 24
Finished Aug 15 05:24:15 PM PDT 24
Peak memory 200988 kb
Host smart-aef00a65-904e-41f0-be90-3b09f8713adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465198164 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.465198164
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4086143819
Short name T115
Test name
Test status
Simulation time 369494463 ps
CPU time 1.56 seconds
Started Aug 15 05:24:09 PM PDT 24
Finished Aug 15 05:24:11 PM PDT 24
Peak memory 200880 kb
Host smart-5d203927-0f0f-4846-9854-fbc7ca69869f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086143819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4086143819
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3142072507
Short name T819
Test name
Test status
Simulation time 384879331 ps
CPU time 0.91 seconds
Started Aug 15 05:24:09 PM PDT 24
Finished Aug 15 05:24:10 PM PDT 24
Peak memory 200816 kb
Host smart-fc9489ab-fac6-4b80-94ce-d082a8a31f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142072507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3142072507
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.740169193
Short name T879
Test name
Test status
Simulation time 1641206266 ps
CPU time 1.63 seconds
Started Aug 15 05:24:10 PM PDT 24
Finished Aug 15 05:24:12 PM PDT 24
Peak memory 200940 kb
Host smart-01547199-c3f1-4a4c-b28e-3ed58d89db6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740169193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.740169193
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2607049982
Short name T883
Test name
Test status
Simulation time 475107145 ps
CPU time 2.63 seconds
Started Aug 15 05:24:10 PM PDT 24
Finished Aug 15 05:24:13 PM PDT 24
Peak memory 216948 kb
Host smart-7e5a84af-95f1-4039-b0e3-6dce318df471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607049982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2607049982
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1694361361
Short name T889
Test name
Test status
Simulation time 8455427367 ps
CPU time 11.13 seconds
Started Aug 15 05:24:14 PM PDT 24
Finished Aug 15 05:24:25 PM PDT 24
Peak memory 201128 kb
Host smart-a18018b9-8b84-4c5a-85b9-44e8d42e065d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694361361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1694361361
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4226138908
Short name T877
Test name
Test status
Simulation time 770643809 ps
CPU time 1.89 seconds
Started Aug 15 05:24:14 PM PDT 24
Finished Aug 15 05:24:16 PM PDT 24
Peak memory 201056 kb
Host smart-6fd7efca-9ce7-4f85-8ff9-ff0154d8f325
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226138908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4226138908
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2856037575
Short name T853
Test name
Test status
Simulation time 53147923803 ps
CPU time 41.32 seconds
Started Aug 15 05:24:14 PM PDT 24
Finished Aug 15 05:24:56 PM PDT 24
Peak memory 201100 kb
Host smart-0009f5fc-20b5-4d34-9cda-53f38a668893
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856037575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2856037575
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2300036012
Short name T105
Test name
Test status
Simulation time 1237052506 ps
CPU time 1.56 seconds
Started Aug 15 05:24:13 PM PDT 24
Finished Aug 15 05:24:15 PM PDT 24
Peak memory 200924 kb
Host smart-0b97589b-d838-490f-a37a-4b14388562ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300036012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2300036012
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1404604441
Short name T807
Test name
Test status
Simulation time 428764584 ps
CPU time 1.4 seconds
Started Aug 15 05:24:16 PM PDT 24
Finished Aug 15 05:24:17 PM PDT 24
Peak memory 200936 kb
Host smart-769495d1-718e-4a37-aad7-dd7e7b58a513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404604441 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1404604441
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1686074255
Short name T109
Test name
Test status
Simulation time 476726642 ps
CPU time 1.79 seconds
Started Aug 15 05:24:15 PM PDT 24
Finished Aug 15 05:24:17 PM PDT 24
Peak memory 200896 kb
Host smart-0bb1e663-5c3f-4661-b1e3-985e7996fbfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686074255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1686074255
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2394064996
Short name T899
Test name
Test status
Simulation time 404226452 ps
CPU time 0.77 seconds
Started Aug 15 05:24:14 PM PDT 24
Finished Aug 15 05:24:14 PM PDT 24
Peak memory 200800 kb
Host smart-c0b5d366-b2ad-49c4-a66a-91bc2f933856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394064996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2394064996
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4135690380
Short name T913
Test name
Test status
Simulation time 4628172274 ps
CPU time 18.93 seconds
Started Aug 15 05:24:11 PM PDT 24
Finished Aug 15 05:24:30 PM PDT 24
Peak memory 201136 kb
Host smart-10f5bdbb-8982-488e-b302-1b6c378fba99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135690380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.4135690380
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1657593191
Short name T884
Test name
Test status
Simulation time 315619524 ps
CPU time 3.36 seconds
Started Aug 15 05:24:16 PM PDT 24
Finished Aug 15 05:24:20 PM PDT 24
Peak memory 217408 kb
Host smart-85ed0a83-8295-42d4-8a03-e5998eb2e544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657593191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1657593191
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.928034961
Short name T891
Test name
Test status
Simulation time 491789219 ps
CPU time 2.07 seconds
Started Aug 15 05:24:24 PM PDT 24
Finished Aug 15 05:24:26 PM PDT 24
Peak memory 201004 kb
Host smart-4392e78a-16f0-4377-961c-9308a0453ec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928034961 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.928034961
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.91884591
Short name T907
Test name
Test status
Simulation time 557252626 ps
CPU time 2.02 seconds
Started Aug 15 05:24:30 PM PDT 24
Finished Aug 15 05:24:32 PM PDT 24
Peak memory 200864 kb
Host smart-8a5d7d4c-2225-4f96-b41b-b05bfb541f9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91884591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.91884591
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3756096082
Short name T920
Test name
Test status
Simulation time 419446787 ps
CPU time 1.52 seconds
Started Aug 15 05:24:43 PM PDT 24
Finished Aug 15 05:24:45 PM PDT 24
Peak memory 200856 kb
Host smart-68323c20-5785-4de4-8106-8f12e6801d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756096082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3756096082
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.564158073
Short name T49
Test name
Test status
Simulation time 8644346584 ps
CPU time 11.8 seconds
Started Aug 15 05:24:39 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 201160 kb
Host smart-67a020c2-5f6c-48cd-90d3-cbb747be1c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564158073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.564158073
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1241740822
Short name T912
Test name
Test status
Simulation time 628477281 ps
CPU time 1.15 seconds
Started Aug 15 05:24:23 PM PDT 24
Finished Aug 15 05:24:25 PM PDT 24
Peak memory 200996 kb
Host smart-4f057b55-5f51-40ba-ab20-d5c6b2cb66a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241740822 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1241740822
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1247657942
Short name T119
Test name
Test status
Simulation time 473796935 ps
CPU time 1.89 seconds
Started Aug 15 05:24:32 PM PDT 24
Finished Aug 15 05:24:34 PM PDT 24
Peak memory 200856 kb
Host smart-58e767a3-815b-4add-a4e9-faecd2109ede
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247657942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1247657942
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.931658449
Short name T828
Test name
Test status
Simulation time 488934520 ps
CPU time 1.33 seconds
Started Aug 15 05:24:29 PM PDT 24
Finished Aug 15 05:24:30 PM PDT 24
Peak memory 200852 kb
Host smart-ba932a4d-0fd1-4f87-bbe1-0b7a942746ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931658449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.931658449
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1095720819
Short name T838
Test name
Test status
Simulation time 2451993615 ps
CPU time 2.94 seconds
Started Aug 15 05:24:31 PM PDT 24
Finished Aug 15 05:24:34 PM PDT 24
Peak memory 200912 kb
Host smart-7c7f02c6-2755-4dbe-8907-05f4e64dedb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095720819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1095720819
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2203802121
Short name T57
Test name
Test status
Simulation time 689498667 ps
CPU time 1.61 seconds
Started Aug 15 05:24:36 PM PDT 24
Finished Aug 15 05:24:38 PM PDT 24
Peak memory 201136 kb
Host smart-457b05cb-f568-4c9f-b3b5-e72bb21295f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203802121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2203802121
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.973643812
Short name T885
Test name
Test status
Simulation time 4194128384 ps
CPU time 10.49 seconds
Started Aug 15 05:24:28 PM PDT 24
Finished Aug 15 05:24:39 PM PDT 24
Peak memory 201160 kb
Host smart-7acc2ed7-55c1-428b-a744-ed943ea6cc95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973643812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.973643812
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2912014967
Short name T827
Test name
Test status
Simulation time 416903594 ps
CPU time 1.53 seconds
Started Aug 15 05:24:37 PM PDT 24
Finished Aug 15 05:24:38 PM PDT 24
Peak memory 200996 kb
Host smart-8be057df-408a-4112-8312-5739da0960b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912014967 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2912014967
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3180282288
Short name T108
Test name
Test status
Simulation time 345005892 ps
CPU time 1.58 seconds
Started Aug 15 05:24:39 PM PDT 24
Finished Aug 15 05:24:41 PM PDT 24
Peak memory 200892 kb
Host smart-f21c560b-9720-4909-8a81-319430160d7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180282288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3180282288
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1651103952
Short name T848
Test name
Test status
Simulation time 344810479 ps
CPU time 0.86 seconds
Started Aug 15 05:24:37 PM PDT 24
Finished Aug 15 05:24:38 PM PDT 24
Peak memory 199588 kb
Host smart-a8d7a839-e28a-44d2-bad9-3c47cd17b011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651103952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1651103952
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.677802054
Short name T855
Test name
Test status
Simulation time 3770051040 ps
CPU time 2.03 seconds
Started Aug 15 05:24:39 PM PDT 24
Finished Aug 15 05:24:41 PM PDT 24
Peak memory 201144 kb
Host smart-0b2f0a21-958c-41f0-9892-47c2e813fa15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677802054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.677802054
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3194219841
Short name T837
Test name
Test status
Simulation time 720359021 ps
CPU time 2.98 seconds
Started Aug 15 05:24:39 PM PDT 24
Finished Aug 15 05:24:42 PM PDT 24
Peak memory 210348 kb
Host smart-01142946-3c01-4880-8d03-bd5754e05612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194219841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3194219841
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2112550862
Short name T346
Test name
Test status
Simulation time 8085362915 ps
CPU time 21.38 seconds
Started Aug 15 05:24:40 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 201168 kb
Host smart-67a10c41-d338-4fc4-9727-50ee7a0edc22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112550862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2112550862
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3527007492
Short name T102
Test name
Test status
Simulation time 523805225 ps
CPU time 1.15 seconds
Started Aug 15 05:24:33 PM PDT 24
Finished Aug 15 05:24:35 PM PDT 24
Peak memory 200980 kb
Host smart-65b19bd4-73b8-4abd-8538-3e751c032ad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527007492 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3527007492
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3130215023
Short name T107
Test name
Test status
Simulation time 342501252 ps
CPU time 1.44 seconds
Started Aug 15 05:24:39 PM PDT 24
Finished Aug 15 05:24:40 PM PDT 24
Peak memory 199656 kb
Host smart-e5616b6a-04ef-49fc-986b-71a011b63c9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130215023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3130215023
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1994147934
Short name T836
Test name
Test status
Simulation time 334662244 ps
CPU time 0.82 seconds
Started Aug 15 05:24:28 PM PDT 24
Finished Aug 15 05:24:29 PM PDT 24
Peak memory 199584 kb
Host smart-3c611ded-b8f1-49cd-8621-171f98762763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994147934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1994147934
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.401957793
Short name T122
Test name
Test status
Simulation time 4171192406 ps
CPU time 9.25 seconds
Started Aug 15 05:24:30 PM PDT 24
Finished Aug 15 05:24:40 PM PDT 24
Peak memory 201096 kb
Host smart-f25fe307-2a53-44d0-a92a-527fd109ae72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401957793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.401957793
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2580479810
Short name T846
Test name
Test status
Simulation time 377940352 ps
CPU time 2.38 seconds
Started Aug 15 05:24:31 PM PDT 24
Finished Aug 15 05:24:33 PM PDT 24
Peak memory 201088 kb
Host smart-b51f25b8-9748-4731-ae3f-37c523462fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580479810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2580479810
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.660966731
Short name T47
Test name
Test status
Simulation time 4602804094 ps
CPU time 2.89 seconds
Started Aug 15 05:24:29 PM PDT 24
Finished Aug 15 05:24:32 PM PDT 24
Peak memory 201124 kb
Host smart-9ab413df-1a9d-495c-b444-ac26262e8100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660966731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.660966731
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1856568947
Short name T878
Test name
Test status
Simulation time 318311015 ps
CPU time 1.18 seconds
Started Aug 15 05:24:40 PM PDT 24
Finished Aug 15 05:24:41 PM PDT 24
Peak memory 200988 kb
Host smart-29a55925-9449-4712-8be3-f387a5d589db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856568947 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1856568947
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2700630298
Short name T121
Test name
Test status
Simulation time 586296068 ps
CPU time 1.24 seconds
Started Aug 15 05:24:37 PM PDT 24
Finished Aug 15 05:24:38 PM PDT 24
Peak memory 200872 kb
Host smart-6e74cbb6-d886-41ce-8be0-44e49b4dce89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700630298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2700630298
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3596712053
Short name T825
Test name
Test status
Simulation time 394626227 ps
CPU time 0.94 seconds
Started Aug 15 05:24:38 PM PDT 24
Finished Aug 15 05:24:39 PM PDT 24
Peak memory 200844 kb
Host smart-9ccec6e1-1d33-4771-bee7-8e91a1a30666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596712053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3596712053
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2659587764
Short name T120
Test name
Test status
Simulation time 4637393829 ps
CPU time 18.94 seconds
Started Aug 15 05:24:43 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 201040 kb
Host smart-441c29fc-8594-43eb-a3c3-da08c8877ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659587764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2659587764
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4019806665
Short name T880
Test name
Test status
Simulation time 464827789 ps
CPU time 2.29 seconds
Started Aug 15 05:24:38 PM PDT 24
Finished Aug 15 05:24:40 PM PDT 24
Peak memory 217180 kb
Host smart-44cc8885-eb4a-4996-b284-2277a45e7e56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019806665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4019806665
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3933120151
Short name T824
Test name
Test status
Simulation time 4474112786 ps
CPU time 6.58 seconds
Started Aug 15 05:24:38 PM PDT 24
Finished Aug 15 05:24:44 PM PDT 24
Peak memory 201172 kb
Host smart-650dc7fe-4b13-4148-9a39-d008c96f34ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933120151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3933120151
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2402085857
Short name T887
Test name
Test status
Simulation time 445899217 ps
CPU time 1.05 seconds
Started Aug 15 05:24:40 PM PDT 24
Finished Aug 15 05:24:41 PM PDT 24
Peak memory 200996 kb
Host smart-3bb705a5-b8f9-4d98-a16b-650df2fc7bb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402085857 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2402085857
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3270153987
Short name T111
Test name
Test status
Simulation time 451747016 ps
CPU time 1.43 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 200912 kb
Host smart-33fbfc6a-dc89-4824-979d-da9561e5a1b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270153987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3270153987
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.942374250
Short name T870
Test name
Test status
Simulation time 393343803 ps
CPU time 0.75 seconds
Started Aug 15 05:24:44 PM PDT 24
Finished Aug 15 05:24:45 PM PDT 24
Peak memory 200856 kb
Host smart-3cd491ef-8933-4cab-baeb-e1c562237857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942374250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.942374250
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.680117789
Short name T854
Test name
Test status
Simulation time 2957361918 ps
CPU time 5.93 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:53 PM PDT 24
Peak memory 200956 kb
Host smart-4da09fbb-789a-46cd-8784-ffff7709772d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680117789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.680117789
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3645623524
Short name T808
Test name
Test status
Simulation time 433804631 ps
CPU time 3.02 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 217524 kb
Host smart-8d1e846a-49df-4ae5-850f-15735d48edda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645623524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3645623524
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.127399829
Short name T347
Test name
Test status
Simulation time 4389120972 ps
CPU time 11.26 seconds
Started Aug 15 05:24:43 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 201084 kb
Host smart-113a48d6-225d-41e0-8b7a-55c1550adb7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127399829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.127399829
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3173987002
Short name T831
Test name
Test status
Simulation time 733689715 ps
CPU time 1.18 seconds
Started Aug 15 05:24:39 PM PDT 24
Finished Aug 15 05:24:40 PM PDT 24
Peak memory 200932 kb
Host smart-d80a93a8-f2c4-4344-a1b7-55e8da25e1c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173987002 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3173987002
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.372445803
Short name T906
Test name
Test status
Simulation time 487844172 ps
CPU time 1.08 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 200888 kb
Host smart-bbbf817f-7663-43be-b0fc-55a426699c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372445803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.372445803
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.146682191
Short name T914
Test name
Test status
Simulation time 326023370 ps
CPU time 0.83 seconds
Started Aug 15 05:24:46 PM PDT 24
Finished Aug 15 05:24:47 PM PDT 24
Peak memory 200816 kb
Host smart-ea709040-c559-48ba-81eb-1683dfe4131a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146682191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.146682191
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1396265943
Short name T864
Test name
Test status
Simulation time 5247478336 ps
CPU time 2.82 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 201112 kb
Host smart-d78b4364-5b79-4c27-bfb1-8abbfdd0e1b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396265943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1396265943
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1706639663
Short name T888
Test name
Test status
Simulation time 8334695630 ps
CPU time 20.32 seconds
Started Aug 15 05:24:44 PM PDT 24
Finished Aug 15 05:25:05 PM PDT 24
Peak memory 201148 kb
Host smart-a9ef1467-4f83-4af6-90ef-5ac18dbdddfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706639663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1706639663
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3339993565
Short name T810
Test name
Test status
Simulation time 623307633 ps
CPU time 1.37 seconds
Started Aug 15 05:24:39 PM PDT 24
Finished Aug 15 05:24:40 PM PDT 24
Peak memory 200976 kb
Host smart-7085b9e9-9a13-475d-ada1-a87cfdd2d974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339993565 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3339993565
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3875051014
Short name T910
Test name
Test status
Simulation time 350006471 ps
CPU time 1.3 seconds
Started Aug 15 05:24:46 PM PDT 24
Finished Aug 15 05:24:47 PM PDT 24
Peak memory 200928 kb
Host smart-7d5a40c6-b46f-4b97-bd6a-168d205f4964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875051014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3875051014
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.271046835
Short name T800
Test name
Test status
Simulation time 509182528 ps
CPU time 1.13 seconds
Started Aug 15 05:24:42 PM PDT 24
Finished Aug 15 05:24:43 PM PDT 24
Peak memory 200860 kb
Host smart-3506ea1c-2592-4afd-84b6-188877d94179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271046835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.271046835
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4043151847
Short name T911
Test name
Test status
Simulation time 2358533050 ps
CPU time 3.27 seconds
Started Aug 15 05:24:46 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 200920 kb
Host smart-b73d2661-f817-43e5-b155-731c51e0cf26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043151847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.4043151847
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2627152213
Short name T858
Test name
Test status
Simulation time 523941415 ps
CPU time 2.16 seconds
Started Aug 15 05:24:46 PM PDT 24
Finished Aug 15 05:24:48 PM PDT 24
Peak memory 201128 kb
Host smart-abf2f859-732e-4645-8df3-b4d3f45a97f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627152213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2627152213
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.820288705
Short name T850
Test name
Test status
Simulation time 4582132196 ps
CPU time 4.19 seconds
Started Aug 15 05:24:45 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 201112 kb
Host smart-e9502fb8-ab23-4b2f-9912-07a957cf0c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820288705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.820288705
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3648382396
Short name T829
Test name
Test status
Simulation time 594012733 ps
CPU time 2.11 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 200988 kb
Host smart-b937f353-003d-434f-a91a-47dfd6803b30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648382396 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3648382396
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3141989741
Short name T909
Test name
Test status
Simulation time 483009661 ps
CPU time 1.16 seconds
Started Aug 15 05:24:40 PM PDT 24
Finished Aug 15 05:24:42 PM PDT 24
Peak memory 200920 kb
Host smart-daa6c4b1-6428-4880-aa19-4fb49fbb74fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141989741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3141989741
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2461647761
Short name T882
Test name
Test status
Simulation time 322980155 ps
CPU time 0.93 seconds
Started Aug 15 05:24:43 PM PDT 24
Finished Aug 15 05:24:44 PM PDT 24
Peak memory 200844 kb
Host smart-6076f3ec-6a21-4dbf-af07-6adc7732e964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461647761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2461647761
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3200323141
Short name T822
Test name
Test status
Simulation time 2463800622 ps
CPU time 10.23 seconds
Started Aug 15 05:24:51 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 200936 kb
Host smart-412f540b-2d68-47d3-8fa6-adb6d59ec085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200323141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3200323141
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3015247424
Short name T902
Test name
Test status
Simulation time 372475621 ps
CPU time 2.52 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 209280 kb
Host smart-20035f7c-2906-4249-b615-12f1580a2962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015247424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3015247424
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1767474493
Short name T842
Test name
Test status
Simulation time 4542929809 ps
CPU time 6.49 seconds
Started Aug 15 05:24:45 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 201100 kb
Host smart-7cbeb830-a00e-4cb3-aa2e-76b40b71231b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767474493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1767474493
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2690870785
Short name T62
Test name
Test status
Simulation time 489108387 ps
CPU time 2.01 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 200996 kb
Host smart-9442ecad-b88e-48cc-b523-3be018d35334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690870785 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2690870785
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1590959165
Short name T801
Test name
Test status
Simulation time 309675587 ps
CPU time 0.8 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 200776 kb
Host smart-53f815ca-fac0-476e-8262-c4c10bc17254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590959165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1590959165
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.634588661
Short name T46
Test name
Test status
Simulation time 4921322230 ps
CPU time 11.41 seconds
Started Aug 15 05:24:53 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 201184 kb
Host smart-b53d3d84-d8c8-460a-b389-9c43213052fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634588661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.634588661
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1224797695
Short name T861
Test name
Test status
Simulation time 473542321 ps
CPU time 2.58 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 201152 kb
Host smart-16fac2a5-2ef7-4657-b9c1-fe35a12c225c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224797695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1224797695
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3808274506
Short name T856
Test name
Test status
Simulation time 8841318553 ps
CPU time 4.95 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:54 PM PDT 24
Peak memory 201120 kb
Host smart-4ce290e6-8e4f-435d-adfc-e107ba3b74fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808274506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3808274506
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4288355215
Short name T114
Test name
Test status
Simulation time 681010672 ps
CPU time 3.37 seconds
Started Aug 15 05:24:15 PM PDT 24
Finished Aug 15 05:24:19 PM PDT 24
Peak memory 201044 kb
Host smart-87667715-83a6-4779-b10f-9f11b222f06a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288355215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.4288355215
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1020020574
Short name T45
Test name
Test status
Simulation time 27296507261 ps
CPU time 9.01 seconds
Started Aug 15 05:24:11 PM PDT 24
Finished Aug 15 05:24:21 PM PDT 24
Peak memory 201124 kb
Host smart-b6749e01-85ba-4d8e-88f0-35b527098892
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020020574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1020020574
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4135068470
Short name T917
Test name
Test status
Simulation time 1230945853 ps
CPU time 1.9 seconds
Started Aug 15 05:24:16 PM PDT 24
Finished Aug 15 05:24:18 PM PDT 24
Peak memory 200816 kb
Host smart-f2f03dbd-4736-4599-9666-a78fc3bd21c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135068470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.4135068470
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3575981685
Short name T813
Test name
Test status
Simulation time 512830168 ps
CPU time 1.15 seconds
Started Aug 15 05:24:14 PM PDT 24
Finished Aug 15 05:24:15 PM PDT 24
Peak memory 200992 kb
Host smart-e2b41a1a-6715-4772-888a-80552777b185
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575981685 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3575981685
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1187972766
Short name T110
Test name
Test status
Simulation time 310407762 ps
CPU time 1.1 seconds
Started Aug 15 05:24:15 PM PDT 24
Finished Aug 15 05:24:16 PM PDT 24
Peak memory 200888 kb
Host smart-71c4326d-9159-48bc-8141-79edd06b778e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187972766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1187972766
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4004220248
Short name T903
Test name
Test status
Simulation time 344832985 ps
CPU time 1.46 seconds
Started Aug 15 05:24:10 PM PDT 24
Finished Aug 15 05:24:11 PM PDT 24
Peak memory 200796 kb
Host smart-a4188c51-ae3f-4287-8c6b-014d30129498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004220248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.4004220248
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2306217684
Short name T863
Test name
Test status
Simulation time 1863429906 ps
CPU time 4.98 seconds
Started Aug 15 05:24:12 PM PDT 24
Finished Aug 15 05:24:17 PM PDT 24
Peak memory 200920 kb
Host smart-facc3ee7-d78d-4130-bbb7-b517f43f8e93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306217684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2306217684
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2418893905
Short name T919
Test name
Test status
Simulation time 520562612 ps
CPU time 2.08 seconds
Started Aug 15 05:24:10 PM PDT 24
Finished Aug 15 05:24:13 PM PDT 24
Peak memory 200952 kb
Host smart-9d854a67-abaa-4f92-afb5-3cdee1ced880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418893905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2418893905
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2841028332
Short name T48
Test name
Test status
Simulation time 4427324842 ps
CPU time 3.42 seconds
Started Aug 15 05:24:16 PM PDT 24
Finished Aug 15 05:24:20 PM PDT 24
Peak memory 201124 kb
Host smart-2206816f-5fd1-4ea7-bb09-bdbb5b49b3a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841028332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2841028332
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4222508279
Short name T841
Test name
Test status
Simulation time 351041231 ps
CPU time 0.85 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 200844 kb
Host smart-08c6ac84-e228-458c-bd8f-7e9b64430c6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222508279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4222508279
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2720580269
Short name T830
Test name
Test status
Simulation time 419020202 ps
CPU time 1.07 seconds
Started Aug 15 05:24:46 PM PDT 24
Finished Aug 15 05:24:47 PM PDT 24
Peak memory 200828 kb
Host smart-e6a0dc2c-9f66-4d08-8cd0-98610116b4db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720580269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2720580269
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1722408934
Short name T809
Test name
Test status
Simulation time 403207523 ps
CPU time 0.89 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 200816 kb
Host smart-c72eadd2-7535-4636-9039-67ce9e548e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722408934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1722408934
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.483464677
Short name T818
Test name
Test status
Simulation time 523298852 ps
CPU time 0.93 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:48 PM PDT 24
Peak memory 200832 kb
Host smart-652c5d33-4436-4540-b164-6830dbe7f5ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483464677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.483464677
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.335901079
Short name T905
Test name
Test status
Simulation time 475722279 ps
CPU time 0.83 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:48 PM PDT 24
Peak memory 200824 kb
Host smart-89f756fd-dfe5-49af-81d8-75da51e58c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335901079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.335901079
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3061683739
Short name T845
Test name
Test status
Simulation time 478226219 ps
CPU time 0.79 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 200792 kb
Host smart-ac2c172a-fb4f-49d3-8735-614fddfe758c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061683739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3061683739
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1441559868
Short name T806
Test name
Test status
Simulation time 529337214 ps
CPU time 1.85 seconds
Started Aug 15 05:24:54 PM PDT 24
Finished Aug 15 05:24:56 PM PDT 24
Peak memory 200840 kb
Host smart-de0aa5ae-0bd7-4296-a465-ef2ed07345f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441559868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1441559868
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2076614622
Short name T873
Test name
Test status
Simulation time 374677067 ps
CPU time 0.84 seconds
Started Aug 15 05:24:54 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 200832 kb
Host smart-1df56090-bb6b-443c-87ce-911ddd798750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076614622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2076614622
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.334499536
Short name T908
Test name
Test status
Simulation time 491654816 ps
CPU time 1.76 seconds
Started Aug 15 05:24:54 PM PDT 24
Finished Aug 15 05:24:56 PM PDT 24
Peak memory 200852 kb
Host smart-5bfb06b1-593b-499b-977c-6a9e322ef584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334499536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.334499536
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.18516570
Short name T823
Test name
Test status
Simulation time 510488267 ps
CPU time 0.94 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 200840 kb
Host smart-ff60acc0-3ee7-4f11-b696-74f0054782ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18516570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.18516570
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2809985123
Short name T116
Test name
Test status
Simulation time 685011763 ps
CPU time 1.8 seconds
Started Aug 15 05:24:38 PM PDT 24
Finished Aug 15 05:24:40 PM PDT 24
Peak memory 201076 kb
Host smart-fdec08ee-8897-468a-8a7b-f3890a4e524c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809985123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2809985123
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2325057222
Short name T113
Test name
Test status
Simulation time 23914666412 ps
CPU time 6.79 seconds
Started Aug 15 05:25:10 PM PDT 24
Finished Aug 15 05:25:17 PM PDT 24
Peak memory 201164 kb
Host smart-72bf1999-7360-423b-88f5-90a53103902d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325057222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2325057222
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3567966732
Short name T814
Test name
Test status
Simulation time 810284934 ps
CPU time 1.19 seconds
Started Aug 15 05:24:20 PM PDT 24
Finished Aug 15 05:24:21 PM PDT 24
Peak memory 200896 kb
Host smart-a1f309ef-9a75-46ca-82b2-bca8c0ec79fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567966732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3567966732
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.284148603
Short name T916
Test name
Test status
Simulation time 596441703 ps
CPU time 1.12 seconds
Started Aug 15 05:24:23 PM PDT 24
Finished Aug 15 05:24:24 PM PDT 24
Peak memory 200996 kb
Host smart-84bb7d81-c9a1-4051-8ca0-6758c4382195
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284148603 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.284148603
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.848784726
Short name T112
Test name
Test status
Simulation time 363115723 ps
CPU time 0.98 seconds
Started Aug 15 05:24:22 PM PDT 24
Finished Aug 15 05:24:23 PM PDT 24
Peak memory 200848 kb
Host smart-9a4495cf-ae9e-4f7e-bf3d-a8219294658e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848784726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.848784726
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1686997509
Short name T860
Test name
Test status
Simulation time 408338237 ps
CPU time 1.52 seconds
Started Aug 15 05:24:26 PM PDT 24
Finished Aug 15 05:24:28 PM PDT 24
Peak memory 200848 kb
Host smart-38c65038-e098-4198-b2ec-be3094a8416d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686997509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1686997509
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.708871308
Short name T862
Test name
Test status
Simulation time 2914956819 ps
CPU time 2.28 seconds
Started Aug 15 05:24:32 PM PDT 24
Finished Aug 15 05:24:35 PM PDT 24
Peak memory 200972 kb
Host smart-4c952b32-ebb1-4d14-b740-1b9c21da03f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708871308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.708871308
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1655284001
Short name T78
Test name
Test status
Simulation time 500385945 ps
CPU time 2.29 seconds
Started Aug 15 05:24:17 PM PDT 24
Finished Aug 15 05:24:19 PM PDT 24
Peak memory 201164 kb
Host smart-4e560b99-a03b-4586-bcfb-155280764d10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655284001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1655284001
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.358380994
Short name T857
Test name
Test status
Simulation time 4715403940 ps
CPU time 12.59 seconds
Started Aug 15 05:24:11 PM PDT 24
Finished Aug 15 05:24:24 PM PDT 24
Peak memory 201144 kb
Host smart-c1294d9e-3d32-4be1-9ba3-17c9f9e89722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358380994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.358380994
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.702015595
Short name T802
Test name
Test status
Simulation time 429444006 ps
CPU time 1 seconds
Started Aug 15 05:24:58 PM PDT 24
Finished Aug 15 05:25:00 PM PDT 24
Peak memory 200820 kb
Host smart-644471b5-15e0-427b-af7c-430827733069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702015595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.702015595
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1678410285
Short name T821
Test name
Test status
Simulation time 447337604 ps
CPU time 0.73 seconds
Started Aug 15 05:24:53 PM PDT 24
Finished Aug 15 05:24:54 PM PDT 24
Peak memory 200820 kb
Host smart-cf231f1f-225e-43f2-bd35-82a5abc38bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678410285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1678410285
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4183284957
Short name T886
Test name
Test status
Simulation time 297919605 ps
CPU time 0.79 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 200840 kb
Host smart-b0f36bad-c33e-4374-ad57-aab589c8e729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183284957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.4183284957
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1348215458
Short name T835
Test name
Test status
Simulation time 404742305 ps
CPU time 1.56 seconds
Started Aug 15 05:24:47 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 200836 kb
Host smart-718d0868-617b-45e0-aec4-0ed86f7ee616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348215458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1348215458
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2657156647
Short name T799
Test name
Test status
Simulation time 450218375 ps
CPU time 1.64 seconds
Started Aug 15 05:24:52 PM PDT 24
Finished Aug 15 05:24:54 PM PDT 24
Peak memory 200764 kb
Host smart-f79f75a3-07bd-4ac4-baf1-607ac18bc69b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657156647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2657156647
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2751461257
Short name T815
Test name
Test status
Simulation time 327471859 ps
CPU time 1.37 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 200788 kb
Host smart-926ae87f-e251-4eda-91fa-6b63982b411a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751461257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2751461257
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2527505780
Short name T804
Test name
Test status
Simulation time 354204133 ps
CPU time 0.82 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 200776 kb
Host smart-c204ccc2-006f-4c54-b58f-bf91c4b257ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527505780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2527505780
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1064303931
Short name T904
Test name
Test status
Simulation time 282626060 ps
CPU time 1.3 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 200840 kb
Host smart-64ffd4d2-d819-4dc6-a9ba-414c19df49cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064303931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1064303931
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1605588872
Short name T868
Test name
Test status
Simulation time 471607405 ps
CPU time 1.68 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 200760 kb
Host smart-b147b1db-00ee-42a4-89cd-b5a12f26c225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605588872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1605588872
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.384640506
Short name T811
Test name
Test status
Simulation time 406487788 ps
CPU time 0.8 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 200812 kb
Host smart-5e0908c0-6222-43c7-88b9-7788d415bac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384640506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.384640506
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.165737343
Short name T898
Test name
Test status
Simulation time 725007492 ps
CPU time 3.29 seconds
Started Aug 15 05:24:24 PM PDT 24
Finished Aug 15 05:24:28 PM PDT 24
Peak memory 201080 kb
Host smart-020582f5-b1d7-46d2-843b-33e3c567849a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165737343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.165737343
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3969383685
Short name T900
Test name
Test status
Simulation time 52630315487 ps
CPU time 31.62 seconds
Started Aug 15 05:24:29 PM PDT 24
Finished Aug 15 05:25:01 PM PDT 24
Peak memory 201128 kb
Host smart-56b8ea13-4a7d-4fdd-9ad3-b9c5766d8f4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969383685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3969383685
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4121618213
Short name T106
Test name
Test status
Simulation time 1270612121 ps
CPU time 0.93 seconds
Started Aug 15 05:24:19 PM PDT 24
Finished Aug 15 05:24:20 PM PDT 24
Peak memory 200912 kb
Host smart-e6dab8eb-667f-4d7e-b32d-07d941b51386
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121618213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4121618213
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2505279821
Short name T79
Test name
Test status
Simulation time 568719783 ps
CPU time 1.12 seconds
Started Aug 15 05:24:24 PM PDT 24
Finished Aug 15 05:24:25 PM PDT 24
Peak memory 200992 kb
Host smart-5a2ff6cf-d07f-45f3-b704-1828afc4b449
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505279821 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2505279821
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2802306922
Short name T117
Test name
Test status
Simulation time 504666491 ps
CPU time 1.06 seconds
Started Aug 15 05:24:35 PM PDT 24
Finished Aug 15 05:24:36 PM PDT 24
Peak memory 200868 kb
Host smart-ba923ead-2149-4c07-a7a4-db334b249886
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802306922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2802306922
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.620946717
Short name T881
Test name
Test status
Simulation time 471481416 ps
CPU time 0.91 seconds
Started Aug 15 05:24:34 PM PDT 24
Finished Aug 15 05:24:35 PM PDT 24
Peak memory 200828 kb
Host smart-8eedcb83-abd3-47a2-9bc2-4cc82820384d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620946717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.620946717
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1593425105
Short name T820
Test name
Test status
Simulation time 4837959456 ps
CPU time 12.24 seconds
Started Aug 15 05:24:21 PM PDT 24
Finished Aug 15 05:24:33 PM PDT 24
Peak memory 201184 kb
Host smart-f1961a15-a4d9-427b-96c5-9a21eddadb2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593425105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1593425105
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.440814728
Short name T50
Test name
Test status
Simulation time 536906696 ps
CPU time 3.48 seconds
Started Aug 15 05:24:19 PM PDT 24
Finished Aug 15 05:24:23 PM PDT 24
Peak memory 210356 kb
Host smart-e80bda4b-bd9e-463c-822f-6142788b7455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440814728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.440814728
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3230809549
Short name T894
Test name
Test status
Simulation time 519270919 ps
CPU time 1.17 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 200828 kb
Host smart-b8e06059-5753-46de-9858-f4596df059f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230809549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3230809549
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3731922613
Short name T865
Test name
Test status
Simulation time 533080259 ps
CPU time 1.84 seconds
Started Aug 15 05:24:52 PM PDT 24
Finished Aug 15 05:24:54 PM PDT 24
Peak memory 200780 kb
Host smart-abf1f5bf-f1db-4292-a820-cd019e2c0ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731922613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3731922613
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1832778812
Short name T805
Test name
Test status
Simulation time 402528822 ps
CPU time 1.58 seconds
Started Aug 15 05:24:52 PM PDT 24
Finished Aug 15 05:24:53 PM PDT 24
Peak memory 200820 kb
Host smart-e5219159-69af-4168-a581-fcd48d48a592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832778812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1832778812
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2875597357
Short name T875
Test name
Test status
Simulation time 447793217 ps
CPU time 0.89 seconds
Started Aug 15 05:24:53 PM PDT 24
Finished Aug 15 05:24:54 PM PDT 24
Peak memory 200800 kb
Host smart-48960dc0-32de-4931-bb5b-926c2b3334c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875597357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2875597357
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.28163384
Short name T892
Test name
Test status
Simulation time 514410153 ps
CPU time 1.33 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 200820 kb
Host smart-1d2215f4-1e50-41d3-bad7-d68fff9c5e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28163384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.28163384
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.435150410
Short name T803
Test name
Test status
Simulation time 368003097 ps
CPU time 1.06 seconds
Started Aug 15 05:24:54 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 200784 kb
Host smart-a9448522-52a6-4152-889f-9e9d2f9bf939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435150410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.435150410
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3895524922
Short name T834
Test name
Test status
Simulation time 378741805 ps
CPU time 1.2 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 200828 kb
Host smart-93fd0749-e625-4067-bebd-1e55188a85b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895524922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3895524922
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3516958522
Short name T852
Test name
Test status
Simulation time 333455327 ps
CPU time 0.81 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 200796 kb
Host smart-2864410d-369e-4e7b-8595-b05299d2b2d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516958522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3516958522
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2686945990
Short name T816
Test name
Test status
Simulation time 341144321 ps
CPU time 0.7 seconds
Started Aug 15 05:24:51 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 200796 kb
Host smart-e18f7b2e-2ab4-4582-8b58-190f218326e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686945990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2686945990
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.749308760
Short name T859
Test name
Test status
Simulation time 448735849 ps
CPU time 1.72 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 200820 kb
Host smart-cf16069e-0de9-4ead-ad4a-aebe95e4c9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749308760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.749308760
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2231297566
Short name T840
Test name
Test status
Simulation time 530931548 ps
CPU time 2.01 seconds
Started Aug 15 05:24:24 PM PDT 24
Finished Aug 15 05:24:26 PM PDT 24
Peak memory 200988 kb
Host smart-4c9dea72-910d-42aa-8577-f892edd95b5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231297566 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2231297566
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2412902983
Short name T847
Test name
Test status
Simulation time 326205672 ps
CPU time 0.9 seconds
Started Aug 15 05:24:17 PM PDT 24
Finished Aug 15 05:24:18 PM PDT 24
Peak memory 200908 kb
Host smart-a4c52c75-ea33-4bd7-a194-39e243f77b29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412902983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2412902983
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2121242271
Short name T826
Test name
Test status
Simulation time 355506185 ps
CPU time 1.37 seconds
Started Aug 15 05:24:24 PM PDT 24
Finished Aug 15 05:24:25 PM PDT 24
Peak memory 200812 kb
Host smart-d757daa2-d143-4d15-b825-dcf09c86f4dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121242271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2121242271
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.314441611
Short name T897
Test name
Test status
Simulation time 4280382755 ps
CPU time 3.87 seconds
Started Aug 15 05:24:28 PM PDT 24
Finished Aug 15 05:24:32 PM PDT 24
Peak memory 201108 kb
Host smart-a7a31638-a105-4798-8b3c-1470355c03e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314441611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.314441611
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2685456927
Short name T51
Test name
Test status
Simulation time 733973409 ps
CPU time 2.13 seconds
Started Aug 15 05:24:34 PM PDT 24
Finished Aug 15 05:24:37 PM PDT 24
Peak memory 201164 kb
Host smart-891f8300-bc52-4b48-b180-495c34694de7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685456927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2685456927
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1307065053
Short name T349
Test name
Test status
Simulation time 8550541074 ps
CPU time 12.26 seconds
Started Aug 15 05:24:21 PM PDT 24
Finished Aug 15 05:24:34 PM PDT 24
Peak memory 201184 kb
Host smart-72b5fe50-7e5a-4ee1-b43d-aca55c997f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307065053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1307065053
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1859638613
Short name T867
Test name
Test status
Simulation time 363396532 ps
CPU time 1.78 seconds
Started Aug 15 05:24:38 PM PDT 24
Finished Aug 15 05:24:40 PM PDT 24
Peak memory 200968 kb
Host smart-acc3a414-3571-49c2-ba2c-9a8e29972c14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859638613 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1859638613
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1346636262
Short name T118
Test name
Test status
Simulation time 438062999 ps
CPU time 1.09 seconds
Started Aug 15 05:24:17 PM PDT 24
Finished Aug 15 05:24:18 PM PDT 24
Peak memory 200888 kb
Host smart-d2a214d2-34b1-47a6-b8a9-69ef251a61fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346636262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1346636262
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2471475545
Short name T866
Test name
Test status
Simulation time 512523233 ps
CPU time 1.88 seconds
Started Aug 15 05:24:26 PM PDT 24
Finished Aug 15 05:24:28 PM PDT 24
Peak memory 200800 kb
Host smart-67b59357-0002-4c3b-83b7-1276e5ee39ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471475545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2471475545
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1298300306
Short name T893
Test name
Test status
Simulation time 5128472453 ps
CPU time 19.66 seconds
Started Aug 15 05:24:23 PM PDT 24
Finished Aug 15 05:24:43 PM PDT 24
Peak memory 201100 kb
Host smart-eed6ea99-9917-43f4-94eb-f92556250a4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298300306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1298300306
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1942004509
Short name T871
Test name
Test status
Simulation time 372673735 ps
CPU time 1.81 seconds
Started Aug 15 05:24:31 PM PDT 24
Finished Aug 15 05:24:33 PM PDT 24
Peak memory 201120 kb
Host smart-29c8636e-2c09-4a68-84d1-f5af81fa7c14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942004509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1942004509
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3762618858
Short name T872
Test name
Test status
Simulation time 621535411 ps
CPU time 1.56 seconds
Started Aug 15 05:24:21 PM PDT 24
Finished Aug 15 05:24:23 PM PDT 24
Peak memory 201008 kb
Host smart-3b55ea60-e0d9-4379-aa65-accbc90826b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762618858 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3762618858
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.76337783
Short name T103
Test name
Test status
Simulation time 502925497 ps
CPU time 0.94 seconds
Started Aug 15 05:24:33 PM PDT 24
Finished Aug 15 05:24:34 PM PDT 24
Peak memory 200896 kb
Host smart-aa482ea8-32de-4f37-8cca-78def761a301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76337783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.76337783
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.41636373
Short name T832
Test name
Test status
Simulation time 329337892 ps
CPU time 1.33 seconds
Started Aug 15 05:24:34 PM PDT 24
Finished Aug 15 05:24:36 PM PDT 24
Peak memory 200824 kb
Host smart-3566cf85-ea2a-40e5-90a5-38ccc0585242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41636373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.41636373
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.159810437
Short name T851
Test name
Test status
Simulation time 4549122077 ps
CPU time 5.42 seconds
Started Aug 15 05:24:29 PM PDT 24
Finished Aug 15 05:24:34 PM PDT 24
Peak memory 201136 kb
Host smart-3b8dd36a-a7cd-4334-b158-48cec4029916
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159810437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.159810437
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2818688541
Short name T890
Test name
Test status
Simulation time 981972807 ps
CPU time 2.38 seconds
Started Aug 15 05:24:18 PM PDT 24
Finished Aug 15 05:24:21 PM PDT 24
Peak memory 217100 kb
Host smart-1679fa5f-0f90-4bd8-8f45-a36bd4c999a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818688541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2818688541
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.545597736
Short name T918
Test name
Test status
Simulation time 10125919026 ps
CPU time 3.66 seconds
Started Aug 15 05:24:28 PM PDT 24
Finished Aug 15 05:24:32 PM PDT 24
Peak memory 200980 kb
Host smart-4a97bbab-6795-431d-824e-684ade55c7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545597736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.545597736
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3229463639
Short name T839
Test name
Test status
Simulation time 517572180 ps
CPU time 1.46 seconds
Started Aug 15 05:24:40 PM PDT 24
Finished Aug 15 05:24:42 PM PDT 24
Peak memory 200992 kb
Host smart-d277eb4f-a258-4d96-8924-8f72a672b330
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229463639 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3229463639
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2365826631
Short name T876
Test name
Test status
Simulation time 542857700 ps
CPU time 2.02 seconds
Started Aug 15 05:24:28 PM PDT 24
Finished Aug 15 05:24:30 PM PDT 24
Peak memory 200920 kb
Host smart-871a28ea-942a-41cc-9ca4-58d39418f2b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365826631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2365826631
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3870297987
Short name T901
Test name
Test status
Simulation time 493050568 ps
CPU time 0.8 seconds
Started Aug 15 05:24:33 PM PDT 24
Finished Aug 15 05:24:34 PM PDT 24
Peak memory 200784 kb
Host smart-92c9c40f-371d-426d-b952-2d3f9a7e3932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870297987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3870297987
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3417406272
Short name T874
Test name
Test status
Simulation time 4474192274 ps
CPU time 6.32 seconds
Started Aug 15 05:24:31 PM PDT 24
Finished Aug 15 05:24:37 PM PDT 24
Peak memory 201168 kb
Host smart-aa9426bf-2f24-4b99-8e3e-28fdaa335b7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417406272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3417406272
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2967647457
Short name T843
Test name
Test status
Simulation time 556899900 ps
CPU time 2.68 seconds
Started Aug 15 05:24:22 PM PDT 24
Finished Aug 15 05:24:25 PM PDT 24
Peak memory 201172 kb
Host smart-96fcf524-ce10-4718-8f0a-9b7a3b8f5fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967647457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2967647457
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1642167079
Short name T844
Test name
Test status
Simulation time 3772459414 ps
CPU time 5.87 seconds
Started Aug 15 05:24:21 PM PDT 24
Finished Aug 15 05:24:27 PM PDT 24
Peak memory 201184 kb
Host smart-e26010d6-5ef6-42f7-9162-abbdb7318e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642167079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1642167079
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2005998992
Short name T101
Test name
Test status
Simulation time 325494590 ps
CPU time 1.18 seconds
Started Aug 15 05:24:29 PM PDT 24
Finished Aug 15 05:24:31 PM PDT 24
Peak memory 200936 kb
Host smart-504477e8-5313-4b6c-b49f-b6d077f40192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005998992 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2005998992
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4284163664
Short name T896
Test name
Test status
Simulation time 559056365 ps
CPU time 1.9 seconds
Started Aug 15 05:24:24 PM PDT 24
Finished Aug 15 05:24:26 PM PDT 24
Peak memory 200868 kb
Host smart-acd1bd7d-c25c-48b3-8e74-5a7f81efc2e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284163664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4284163664
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2123714341
Short name T812
Test name
Test status
Simulation time 382029119 ps
CPU time 1.06 seconds
Started Aug 15 05:24:35 PM PDT 24
Finished Aug 15 05:24:36 PM PDT 24
Peak memory 200868 kb
Host smart-ef0c5a5f-67e9-4a20-8ee2-997c1c9f5b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123714341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2123714341
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4208731754
Short name T869
Test name
Test status
Simulation time 3217094886 ps
CPU time 1.29 seconds
Started Aug 15 05:24:30 PM PDT 24
Finished Aug 15 05:24:31 PM PDT 24
Peak memory 201108 kb
Host smart-afc5b9d2-d895-4cc4-94c3-48d4823e161d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208731754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4208731754
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4210866436
Short name T61
Test name
Test status
Simulation time 358132651 ps
CPU time 2.34 seconds
Started Aug 15 05:24:38 PM PDT 24
Finished Aug 15 05:24:41 PM PDT 24
Peak memory 201136 kb
Host smart-304424c8-7aab-48ba-be6a-ee5e923ae84d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210866436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.4210866436
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.142445592
Short name T833
Test name
Test status
Simulation time 4243881751 ps
CPU time 6.39 seconds
Started Aug 15 05:24:45 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 201084 kb
Host smart-8786a4bf-daa3-4b21-889e-738912913f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142445592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.142445592
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3370003412
Short name T397
Test name
Test status
Simulation time 390613472 ps
CPU time 1.56 seconds
Started Aug 15 06:19:57 PM PDT 24
Finished Aug 15 06:19:58 PM PDT 24
Peak memory 201928 kb
Host smart-da05ef5e-9f78-4f2a-8688-f19bb67b3c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370003412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3370003412
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3019588872
Short name T695
Test name
Test status
Simulation time 546480068888 ps
CPU time 194.17 seconds
Started Aug 15 06:19:48 PM PDT 24
Finished Aug 15 06:23:03 PM PDT 24
Peak memory 202140 kb
Host smart-0f166af9-0a3a-4540-8c57-04eb6890918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019588872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3019588872
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3121118057
Short name T192
Test name
Test status
Simulation time 500625956749 ps
CPU time 282.77 seconds
Started Aug 15 06:19:47 PM PDT 24
Finished Aug 15 06:24:30 PM PDT 24
Peak memory 202116 kb
Host smart-0caf821b-3171-4c8d-bae9-ae8bdc5fb177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121118057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3121118057
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1615727486
Short name T557
Test name
Test status
Simulation time 325369576661 ps
CPU time 410.1 seconds
Started Aug 15 06:19:49 PM PDT 24
Finished Aug 15 06:26:40 PM PDT 24
Peak memory 202068 kb
Host smart-d46383fe-4d89-4d55-b331-65c3062f6e09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615727486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1615727486
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.632646482
Short name T193
Test name
Test status
Simulation time 487498224131 ps
CPU time 1149.89 seconds
Started Aug 15 06:19:48 PM PDT 24
Finished Aug 15 06:38:59 PM PDT 24
Peak memory 202124 kb
Host smart-bd80b4d4-e594-4114-9c4f-b8c40b715756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632646482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.632646482
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1287615150
Short name T743
Test name
Test status
Simulation time 160752850096 ps
CPU time 382.45 seconds
Started Aug 15 06:19:46 PM PDT 24
Finished Aug 15 06:26:08 PM PDT 24
Peak memory 202056 kb
Host smart-7773d703-2107-4ff0-89c8-602a1f2d7a81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287615150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1287615150
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1698606349
Short name T402
Test name
Test status
Simulation time 392656495734 ps
CPU time 233.13 seconds
Started Aug 15 06:19:51 PM PDT 24
Finished Aug 15 06:23:44 PM PDT 24
Peak memory 202140 kb
Host smart-3a708608-a5d0-454c-9545-718352079c06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698606349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1698606349
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.4060219279
Short name T573
Test name
Test status
Simulation time 105275161502 ps
CPU time 358.03 seconds
Started Aug 15 06:19:55 PM PDT 24
Finished Aug 15 06:25:53 PM PDT 24
Peak memory 202344 kb
Host smart-47e404c1-0a85-4d12-bbd2-fc180ac93e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060219279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.4060219279
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2576792351
Short name T393
Test name
Test status
Simulation time 35199893796 ps
CPU time 82.88 seconds
Started Aug 15 06:19:55 PM PDT 24
Finished Aug 15 06:21:18 PM PDT 24
Peak memory 201900 kb
Host smart-6766a3d8-7074-40e2-b3f1-97ab6f1d038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576792351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2576792351
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3422097369
Short name T757
Test name
Test status
Simulation time 4299472227 ps
CPU time 5.7 seconds
Started Aug 15 06:19:45 PM PDT 24
Finished Aug 15 06:19:51 PM PDT 24
Peak memory 201912 kb
Host smart-fc8240bb-e594-4f68-bde2-f3fb30540720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422097369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3422097369
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2929570332
Short name T363
Test name
Test status
Simulation time 5909480970 ps
CPU time 4.25 seconds
Started Aug 15 06:19:46 PM PDT 24
Finished Aug 15 06:19:50 PM PDT 24
Peak memory 201876 kb
Host smart-14dec495-498c-4dd9-95f1-35d02e0a4475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929570332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2929570332
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2420757753
Short name T674
Test name
Test status
Simulation time 235495918060 ps
CPU time 563.54 seconds
Started Aug 15 06:19:56 PM PDT 24
Finished Aug 15 06:29:19 PM PDT 24
Peak memory 202116 kb
Host smart-202d42c7-d66b-4bc1-b287-fe50701e2571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420757753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2420757753
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3740108362
Short name T91
Test name
Test status
Simulation time 4246955287 ps
CPU time 11.71 seconds
Started Aug 15 06:19:55 PM PDT 24
Finished Aug 15 06:20:06 PM PDT 24
Peak memory 210460 kb
Host smart-db4384b0-fa70-42f8-9237-5fbe0788d042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740108362 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3740108362
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2748373214
Short name T455
Test name
Test status
Simulation time 454973589 ps
CPU time 1.62 seconds
Started Aug 15 06:19:55 PM PDT 24
Finished Aug 15 06:19:57 PM PDT 24
Peak memory 201940 kb
Host smart-351bea23-4b96-4837-8387-28ea264b5370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748373214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2748373214
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3392231656
Short name T263
Test name
Test status
Simulation time 522795593844 ps
CPU time 1225.29 seconds
Started Aug 15 06:19:56 PM PDT 24
Finished Aug 15 06:40:21 PM PDT 24
Peak memory 202108 kb
Host smart-33cd242c-a7ca-43c5-8e24-2aed2037d8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392231656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3392231656
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3072163787
Short name T770
Test name
Test status
Simulation time 322106119823 ps
CPU time 170.27 seconds
Started Aug 15 06:19:56 PM PDT 24
Finished Aug 15 06:22:46 PM PDT 24
Peak memory 202144 kb
Host smart-69d30966-681f-4fc7-9839-8f1538963491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072163787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3072163787
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4052955400
Short name T507
Test name
Test status
Simulation time 320731607164 ps
CPU time 156.74 seconds
Started Aug 15 06:19:56 PM PDT 24
Finished Aug 15 06:22:33 PM PDT 24
Peak memory 202156 kb
Host smart-48f43c7c-79c7-4da5-964d-f1d991180542
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052955400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.4052955400
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1289904199
Short name T476
Test name
Test status
Simulation time 165599530146 ps
CPU time 99.14 seconds
Started Aug 15 06:19:57 PM PDT 24
Finished Aug 15 06:21:36 PM PDT 24
Peak memory 202132 kb
Host smart-91bd3093-0a82-4bb3-87ca-62d04a3debe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289904199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1289904199
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2602248226
Short name T401
Test name
Test status
Simulation time 168817036509 ps
CPU time 116.16 seconds
Started Aug 15 06:19:55 PM PDT 24
Finished Aug 15 06:21:51 PM PDT 24
Peak memory 202120 kb
Host smart-30b74109-c335-4736-b2eb-f52928d3dc68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602248226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2602248226
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2162237340
Short name T322
Test name
Test status
Simulation time 342540084884 ps
CPU time 185.23 seconds
Started Aug 15 06:19:55 PM PDT 24
Finished Aug 15 06:23:01 PM PDT 24
Peak memory 202068 kb
Host smart-03eeca30-aad7-4b7b-927d-2055bd3e7584
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162237340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2162237340
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.80016316
Short name T742
Test name
Test status
Simulation time 196907841677 ps
CPU time 450.51 seconds
Started Aug 15 06:19:55 PM PDT 24
Finished Aug 15 06:27:26 PM PDT 24
Peak memory 202120 kb
Host smart-24ba1583-0202-4329-a7de-092cc0968440
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80016316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ad
c_ctrl_filters_wakeup_fixed.80016316
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2783982407
Short name T652
Test name
Test status
Simulation time 89182378941 ps
CPU time 323.1 seconds
Started Aug 15 06:19:57 PM PDT 24
Finished Aug 15 06:25:20 PM PDT 24
Peak memory 202420 kb
Host smart-8715151d-3eb2-4581-9367-30573e37ad25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783982407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2783982407
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.239390094
Short name T475
Test name
Test status
Simulation time 34998004635 ps
CPU time 38.99 seconds
Started Aug 15 06:19:56 PM PDT 24
Finished Aug 15 06:20:35 PM PDT 24
Peak memory 201912 kb
Host smart-89e2cbe1-cc3e-4a6b-89af-20d916d3ab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239390094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.239390094
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2103789567
Short name T71
Test name
Test status
Simulation time 4068301558 ps
CPU time 10.43 seconds
Started Aug 15 06:19:56 PM PDT 24
Finished Aug 15 06:20:07 PM PDT 24
Peak memory 201960 kb
Host smart-e15516e5-e618-4bfd-91b9-88f9af721234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103789567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2103789567
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.4257481063
Short name T65
Test name
Test status
Simulation time 7787786426 ps
CPU time 19.61 seconds
Started Aug 15 06:19:57 PM PDT 24
Finished Aug 15 06:20:17 PM PDT 24
Peak memory 218528 kb
Host smart-a8fa1219-a698-4abb-819c-c77368e4aa54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257481063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4257481063
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3964383411
Short name T531
Test name
Test status
Simulation time 5956707939 ps
CPU time 4.74 seconds
Started Aug 15 06:19:59 PM PDT 24
Finished Aug 15 06:20:04 PM PDT 24
Peak memory 201956 kb
Host smart-0e7552de-8f26-4ec1-9d36-d32504efaf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964383411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3964383411
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1392155302
Short name T434
Test name
Test status
Simulation time 335480900 ps
CPU time 1.39 seconds
Started Aug 15 06:20:19 PM PDT 24
Finished Aug 15 06:20:20 PM PDT 24
Peak memory 201920 kb
Host smart-31467eec-d172-4099-b724-52bcda4f0a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392155302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1392155302
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.5721534
Short name T758
Test name
Test status
Simulation time 527733079047 ps
CPU time 54.18 seconds
Started Aug 15 06:21:17 PM PDT 24
Finished Aug 15 06:22:11 PM PDT 24
Peak memory 202156 kb
Host smart-9168fd2e-c335-4bc9-87af-deb0db343f18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5721534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.5721534
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2262070630
Short name T710
Test name
Test status
Simulation time 163201459730 ps
CPU time 386.58 seconds
Started Aug 15 06:20:17 PM PDT 24
Finished Aug 15 06:26:44 PM PDT 24
Peak memory 202148 kb
Host smart-fc68e048-128c-4c69-8cdb-31aded02caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262070630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2262070630
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.79203591
Short name T610
Test name
Test status
Simulation time 480179212846 ps
CPU time 1189.22 seconds
Started Aug 15 06:20:16 PM PDT 24
Finished Aug 15 06:40:06 PM PDT 24
Peak memory 202168 kb
Host smart-7346ae31-e8e2-46cb-83ab-63830c28ba96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=79203591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt
_fixed.79203591
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2060166122
Short name T611
Test name
Test status
Simulation time 327730269895 ps
CPU time 353.66 seconds
Started Aug 15 06:20:11 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 202136 kb
Host smart-48afc628-7da8-468d-9105-48233e8bb497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060166122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2060166122
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3903606554
Short name T411
Test name
Test status
Simulation time 169296599480 ps
CPU time 212.9 seconds
Started Aug 15 06:20:14 PM PDT 24
Finished Aug 15 06:23:47 PM PDT 24
Peak memory 202132 kb
Host smart-c294db58-4faf-49b1-9017-5bdd361cfcf0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903606554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3903606554
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.806115300
Short name T83
Test name
Test status
Simulation time 177967726667 ps
CPU time 192.24 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:23:33 PM PDT 24
Peak memory 202188 kb
Host smart-8ff4dd3e-4d7e-45a6-bb49-d988ef1aa5cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806115300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.806115300
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2004707346
Short name T195
Test name
Test status
Simulation time 623591820274 ps
CPU time 390.61 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:26:49 PM PDT 24
Peak memory 202108 kb
Host smart-c16e4067-28a6-43e0-a877-a08f826b60f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004707346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2004707346
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3628924096
Short name T357
Test name
Test status
Simulation time 38917351707 ps
CPU time 22.91 seconds
Started Aug 15 06:20:40 PM PDT 24
Finished Aug 15 06:21:03 PM PDT 24
Peak memory 201960 kb
Host smart-b0b0dc32-9da3-4e10-94fe-43b44b8ece3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628924096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3628924096
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1543898196
Short name T362
Test name
Test status
Simulation time 4512476446 ps
CPU time 5.78 seconds
Started Aug 15 06:20:17 PM PDT 24
Finished Aug 15 06:20:23 PM PDT 24
Peak memory 201956 kb
Host smart-415d7e5e-d343-4969-8ab9-7b30055d8c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543898196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1543898196
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2505817553
Short name T795
Test name
Test status
Simulation time 5747233086 ps
CPU time 14.24 seconds
Started Aug 15 06:20:09 PM PDT 24
Finished Aug 15 06:20:23 PM PDT 24
Peak memory 201964 kb
Host smart-e1cc99c4-8294-4338-ba9e-2458b4a84464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505817553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2505817553
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3521923654
Short name T33
Test name
Test status
Simulation time 6212727909 ps
CPU time 4.02 seconds
Started Aug 15 06:20:16 PM PDT 24
Finished Aug 15 06:20:20 PM PDT 24
Peak memory 202088 kb
Host smart-98d1f393-f0c0-4f14-b2dd-b4f3e405bc2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521923654 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3521923654
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.190126653
Short name T698
Test name
Test status
Simulation time 498943124 ps
CPU time 1.91 seconds
Started Aug 15 06:20:16 PM PDT 24
Finished Aug 15 06:20:18 PM PDT 24
Peak memory 201948 kb
Host smart-524e4fb5-1514-4868-923d-4b1630c23b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190126653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.190126653
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3093484508
Short name T714
Test name
Test status
Simulation time 174318368263 ps
CPU time 97.81 seconds
Started Aug 15 06:20:19 PM PDT 24
Finished Aug 15 06:21:57 PM PDT 24
Peak memory 202120 kb
Host smart-bc7e5806-e419-4f14-be57-547a9f4b073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093484508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3093484508
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3226051022
Short name T326
Test name
Test status
Simulation time 172115691439 ps
CPU time 29.59 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:20:48 PM PDT 24
Peak memory 202132 kb
Host smart-04a553f8-8f76-4424-a768-ba89ae1d1f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226051022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3226051022
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1629465767
Short name T372
Test name
Test status
Simulation time 335815442946 ps
CPU time 131.79 seconds
Started Aug 15 06:20:16 PM PDT 24
Finished Aug 15 06:22:28 PM PDT 24
Peak memory 202160 kb
Host smart-804b1303-f54f-4caf-b265-04ba79a04830
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629465767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1629465767
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2885952082
Short name T664
Test name
Test status
Simulation time 168903478642 ps
CPU time 99.88 seconds
Started Aug 15 06:20:17 PM PDT 24
Finished Aug 15 06:21:58 PM PDT 24
Peak memory 202168 kb
Host smart-79b59a1d-39ec-42ed-bc64-dfe09be1f71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885952082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2885952082
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.160507463
Short name T525
Test name
Test status
Simulation time 168170875829 ps
CPU time 204.73 seconds
Started Aug 15 06:20:19 PM PDT 24
Finished Aug 15 06:23:44 PM PDT 24
Peak memory 202120 kb
Host smart-8ca1e6a3-04a9-4379-a610-144fd0c832d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=160507463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.160507463
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.720491485
Short name T139
Test name
Test status
Simulation time 181926941388 ps
CPU time 420.73 seconds
Started Aug 15 06:20:17 PM PDT 24
Finished Aug 15 06:27:18 PM PDT 24
Peak memory 202164 kb
Host smart-6a2e7323-f233-47f1-8fc3-5f9283b1344e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720491485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.720491485
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.16498280
Short name T541
Test name
Test status
Simulation time 399182195708 ps
CPU time 223.66 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:24:02 PM PDT 24
Peak memory 202060 kb
Host smart-26b12581-f9a8-44a4-97b0-532446ad03ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16498280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.a
dc_ctrl_filters_wakeup_fixed.16498280
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2816481548
Short name T676
Test name
Test status
Simulation time 123366110766 ps
CPU time 639.82 seconds
Started Aug 15 06:20:16 PM PDT 24
Finished Aug 15 06:30:56 PM PDT 24
Peak memory 202364 kb
Host smart-f9c5da70-5ef8-4054-921e-1db4bfaedac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816481548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2816481548
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.815723402
Short name T529
Test name
Test status
Simulation time 26434015529 ps
CPU time 4.07 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:20:22 PM PDT 24
Peak memory 201964 kb
Host smart-b1dc95df-b85b-4826-b13d-8e30fdba92f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815723402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.815723402
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3129195574
Short name T623
Test name
Test status
Simulation time 4032772133 ps
CPU time 9.63 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:20:28 PM PDT 24
Peak memory 201956 kb
Host smart-d7ffe800-5ac1-47d2-aef7-9b07c286ee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129195574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3129195574
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3600527980
Short name T527
Test name
Test status
Simulation time 6052022808 ps
CPU time 4.37 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:20:26 PM PDT 24
Peak memory 201956 kb
Host smart-1e8f6933-07ba-4ea5-b984-55644ca3a983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600527980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3600527980
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.408594640
Short name T328
Test name
Test status
Simulation time 181060842993 ps
CPU time 109.86 seconds
Started Aug 15 06:20:19 PM PDT 24
Finished Aug 15 06:22:09 PM PDT 24
Peak memory 202192 kb
Host smart-cca0ac73-0a42-4e97-925d-0d757a7c82a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408594640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
408594640
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2005413730
Short name T400
Test name
Test status
Simulation time 302843841 ps
CPU time 1.32 seconds
Started Aug 15 06:20:19 PM PDT 24
Finished Aug 15 06:20:21 PM PDT 24
Peak memory 201976 kb
Host smart-593384b2-3f86-4dcd-afad-e0d0d1b73c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005413730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2005413730
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3837312469
Short name T283
Test name
Test status
Simulation time 495957370545 ps
CPU time 295.6 seconds
Started Aug 15 06:20:22 PM PDT 24
Finished Aug 15 06:25:18 PM PDT 24
Peak memory 202188 kb
Host smart-dc4ba4b4-622e-4772-94d0-4fe1d2e9a6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837312469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3837312469
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.755526139
Short name T672
Test name
Test status
Simulation time 162516859014 ps
CPU time 351.04 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:26:12 PM PDT 24
Peak memory 202128 kb
Host smart-b740daa3-bcb8-4f57-9749-36682cba47dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755526139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.755526139
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1285109866
Short name T667
Test name
Test status
Simulation time 327439891744 ps
CPU time 608.89 seconds
Started Aug 15 06:20:20 PM PDT 24
Finished Aug 15 06:30:29 PM PDT 24
Peak memory 202164 kb
Host smart-c68a37b9-1856-4755-a7f7-17b83401c70c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285109866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1285109866
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1466690671
Short name T309
Test name
Test status
Simulation time 327942164056 ps
CPU time 61.63 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:21:23 PM PDT 24
Peak memory 202128 kb
Host smart-d32aced5-1611-435e-9c93-0aa60dcb0d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466690671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1466690671
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1067644336
Short name T749
Test name
Test status
Simulation time 487388286049 ps
CPU time 263.85 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:24:46 PM PDT 24
Peak memory 202144 kb
Host smart-a3803ee2-9d7c-4d91-ae9b-75dad81e843b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067644336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1067644336
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.543459549
Short name T720
Test name
Test status
Simulation time 199988588027 ps
CPU time 454.89 seconds
Started Aug 15 06:20:16 PM PDT 24
Finished Aug 15 06:27:51 PM PDT 24
Peak memory 202092 kb
Host smart-33f58cef-e3a3-41ca-9178-3bc786f13049
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543459549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.543459549
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.182761143
Short name T532
Test name
Test status
Simulation time 41185629043 ps
CPU time 16.91 seconds
Started Aug 15 06:20:20 PM PDT 24
Finished Aug 15 06:20:37 PM PDT 24
Peak memory 201880 kb
Host smart-b62f4231-d4c2-419c-af56-8f82917e772c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182761143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.182761143
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3371006977
Short name T367
Test name
Test status
Simulation time 5305343703 ps
CPU time 3.93 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:20:22 PM PDT 24
Peak memory 201884 kb
Host smart-a58fc5d1-f63d-441f-9080-d904e2319457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371006977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3371006977
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.544188140
Short name T583
Test name
Test status
Simulation time 5659730047 ps
CPU time 15.13 seconds
Started Aug 15 06:20:20 PM PDT 24
Finished Aug 15 06:20:36 PM PDT 24
Peak memory 201972 kb
Host smart-2cbc83b3-8d0f-4527-97d4-a6718496ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544188140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.544188140
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1977373261
Short name T719
Test name
Test status
Simulation time 202573535514 ps
CPU time 318.71 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:25:37 PM PDT 24
Peak memory 202068 kb
Host smart-ca9f48f5-1559-4f79-9211-d3e195e9664b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977373261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1977373261
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.516208397
Short name T381
Test name
Test status
Simulation time 500927880 ps
CPU time 1.62 seconds
Started Aug 15 06:20:25 PM PDT 24
Finished Aug 15 06:20:27 PM PDT 24
Peak memory 201976 kb
Host smart-ffb7c790-5aae-4195-acb9-1a5b7fb955a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516208397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.516208397
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1235422311
Short name T763
Test name
Test status
Simulation time 175354485997 ps
CPU time 403.35 seconds
Started Aug 15 06:20:20 PM PDT 24
Finished Aug 15 06:27:03 PM PDT 24
Peak memory 202064 kb
Host smart-7f36bd98-ef7a-4315-bc92-48a841fb15df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235422311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1235422311
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3624900841
Short name T275
Test name
Test status
Simulation time 482595736898 ps
CPU time 1126.98 seconds
Started Aug 15 06:20:17 PM PDT 24
Finished Aug 15 06:39:05 PM PDT 24
Peak memory 202096 kb
Host smart-4606cd4f-e55b-4d0d-97f2-5408a1606258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624900841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3624900841
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1130649199
Short name T537
Test name
Test status
Simulation time 169875131672 ps
CPU time 386.31 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:26:45 PM PDT 24
Peak memory 202072 kb
Host smart-c5c6695b-3a8b-46f2-9439-288454675575
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130649199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1130649199
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1280699026
Short name T135
Test name
Test status
Simulation time 169032627370 ps
CPU time 103.8 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:22:03 PM PDT 24
Peak memory 202124 kb
Host smart-fc76d1b5-8b93-4594-970a-0c7aff522e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280699026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1280699026
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3124413566
Short name T82
Test name
Test status
Simulation time 499516798297 ps
CPU time 275.64 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:24:54 PM PDT 24
Peak memory 202084 kb
Host smart-fda3614a-c387-496b-aaad-fb8355e1f0ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124413566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3124413566
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3608323085
Short name T285
Test name
Test status
Simulation time 397145302536 ps
CPU time 463.32 seconds
Started Aug 15 06:20:19 PM PDT 24
Finished Aug 15 06:28:02 PM PDT 24
Peak memory 202120 kb
Host smart-73cfa0b8-6bf8-4af7-8f6e-cbdb67e33c22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608323085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3608323085
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3128816175
Short name T590
Test name
Test status
Simulation time 200958534940 ps
CPU time 451.58 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:27:53 PM PDT 24
Peak memory 202144 kb
Host smart-0e0240b9-5f84-4df5-b7c6-c062f3f97e5a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128816175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3128816175
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.73524142
Short name T211
Test name
Test status
Simulation time 134736105951 ps
CPU time 383.6 seconds
Started Aug 15 06:20:20 PM PDT 24
Finished Aug 15 06:26:44 PM PDT 24
Peak memory 202424 kb
Host smart-0e8f0d85-fd8c-4294-b84d-cca581dd9ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73524142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.73524142
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.310921786
Short name T377
Test name
Test status
Simulation time 27640918307 ps
CPU time 9.89 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:20:31 PM PDT 24
Peak memory 201956 kb
Host smart-6d98408e-b9e8-4956-9be3-6e82a23a6789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310921786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.310921786
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2983928718
Short name T413
Test name
Test status
Simulation time 4705856062 ps
CPU time 1.87 seconds
Started Aug 15 06:20:20 PM PDT 24
Finished Aug 15 06:20:22 PM PDT 24
Peak memory 201972 kb
Host smart-f75fb386-23b2-496b-8ee2-b2663d489315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983928718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2983928718
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1899178810
Short name T706
Test name
Test status
Simulation time 6001006579 ps
CPU time 13.41 seconds
Started Aug 15 06:20:18 PM PDT 24
Finished Aug 15 06:20:32 PM PDT 24
Peak memory 201896 kb
Host smart-b55512a1-829c-41d3-a6d1-6e4eec86dcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899178810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1899178810
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3077053218
Short name T717
Test name
Test status
Simulation time 143361393296 ps
CPU time 423.73 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:27:25 PM PDT 24
Peak memory 202384 kb
Host smart-3eb3b769-127a-4070-a42c-cf6f89955435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077053218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3077053218
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.685484636
Short name T429
Test name
Test status
Simulation time 2824818707 ps
CPU time 9.96 seconds
Started Aug 15 06:20:25 PM PDT 24
Finished Aug 15 06:20:35 PM PDT 24
Peak memory 210700 kb
Host smart-54b4ab59-23ee-48b8-a952-0de191edeed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685484636 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.685484636
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.418080263
Short name T747
Test name
Test status
Simulation time 330163896162 ps
CPU time 229.44 seconds
Started Aug 15 06:20:25 PM PDT 24
Finished Aug 15 06:24:15 PM PDT 24
Peak memory 202156 kb
Host smart-11457733-3b83-476c-b2a3-454f1f20fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418080263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.418080263
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2529865473
Short name T340
Test name
Test status
Simulation time 486534567831 ps
CPU time 293.75 seconds
Started Aug 15 06:20:23 PM PDT 24
Finished Aug 15 06:25:17 PM PDT 24
Peak memory 202148 kb
Host smart-fedb8688-3b29-43da-88aa-e13db04e3d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529865473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2529865473
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.440190882
Short name T551
Test name
Test status
Simulation time 490478441538 ps
CPU time 559.51 seconds
Started Aug 15 06:20:23 PM PDT 24
Finished Aug 15 06:29:43 PM PDT 24
Peak memory 202068 kb
Host smart-3b152191-a180-47e5-bb0d-9cd8e98d160c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=440190882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.440190882
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1314024450
Short name T96
Test name
Test status
Simulation time 193197353250 ps
CPU time 241.35 seconds
Started Aug 15 06:20:31 PM PDT 24
Finished Aug 15 06:24:33 PM PDT 24
Peak memory 202100 kb
Host smart-a75fa301-93c4-4078-ad0a-753a2f25bb77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314024450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1314024450
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1792773740
Short name T711
Test name
Test status
Simulation time 420231747646 ps
CPU time 940.62 seconds
Started Aug 15 06:20:24 PM PDT 24
Finished Aug 15 06:36:05 PM PDT 24
Peak memory 202148 kb
Host smart-bea8ffe7-0153-44be-a56e-2f146d8a96e7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792773740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1792773740
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1128010214
Short name T578
Test name
Test status
Simulation time 103319534050 ps
CPU time 368.28 seconds
Started Aug 15 06:20:22 PM PDT 24
Finished Aug 15 06:26:31 PM PDT 24
Peak memory 202428 kb
Host smart-68328e3d-382b-4146-9e2d-adb379058879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128010214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1128010214
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.128436818
Short name T785
Test name
Test status
Simulation time 38103399594 ps
CPU time 19.17 seconds
Started Aug 15 06:20:22 PM PDT 24
Finished Aug 15 06:20:41 PM PDT 24
Peak memory 201932 kb
Host smart-082843d2-5871-4939-acb5-a7ca86344d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128436818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.128436818
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3691908533
Short name T700
Test name
Test status
Simulation time 3633504876 ps
CPU time 2.81 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:20:24 PM PDT 24
Peak memory 201944 kb
Host smart-7ef276e1-8a52-4e4d-bf1b-671a3d382b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691908533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3691908533
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1129783701
Short name T681
Test name
Test status
Simulation time 6011783562 ps
CPU time 4.25 seconds
Started Aug 15 06:20:21 PM PDT 24
Finished Aug 15 06:20:26 PM PDT 24
Peak memory 201972 kb
Host smart-2493bee2-f3e8-4ee8-962b-8dde3c6a08bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129783701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1129783701
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3170492112
Short name T15
Test name
Test status
Simulation time 2969808428 ps
CPU time 4.34 seconds
Started Aug 15 06:20:23 PM PDT 24
Finished Aug 15 06:20:27 PM PDT 24
Peak memory 202064 kb
Host smart-f825160c-cf4a-499b-8caf-b56fcb890c76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170492112 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3170492112
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.221153122
Short name T406
Test name
Test status
Simulation time 519177506 ps
CPU time 0.86 seconds
Started Aug 15 06:20:24 PM PDT 24
Finished Aug 15 06:20:25 PM PDT 24
Peak memory 201992 kb
Host smart-90c1b747-5579-4f4c-a25d-eaa542180106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221153122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.221153122
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.892745415
Short name T316
Test name
Test status
Simulation time 327628949179 ps
CPU time 693.83 seconds
Started Aug 15 06:20:30 PM PDT 24
Finished Aug 15 06:32:05 PM PDT 24
Peak memory 202068 kb
Host smart-5606e8d5-227f-495e-8a01-03f78b213886
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892745415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.892745415
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1448032209
Short name T233
Test name
Test status
Simulation time 337657738680 ps
CPU time 167.27 seconds
Started Aug 15 06:20:34 PM PDT 24
Finished Aug 15 06:23:21 PM PDT 24
Peak memory 202092 kb
Host smart-4aa1ff1a-f08c-490b-96c2-18066a089826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448032209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1448032209
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2465231577
Short name T542
Test name
Test status
Simulation time 332172201957 ps
CPU time 162.66 seconds
Started Aug 15 06:20:24 PM PDT 24
Finished Aug 15 06:23:07 PM PDT 24
Peak memory 202128 kb
Host smart-f12ae0c8-b29c-4c37-9cfc-1ccaa42b1c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465231577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2465231577
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4134622599
Short name T511
Test name
Test status
Simulation time 164699710025 ps
CPU time 94.63 seconds
Started Aug 15 06:20:22 PM PDT 24
Finished Aug 15 06:21:57 PM PDT 24
Peak memory 202096 kb
Host smart-7a8aa3f7-c548-4ec2-ba65-4ee548a32355
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134622599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.4134622599
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2595776922
Short name T602
Test name
Test status
Simulation time 166767019640 ps
CPU time 379.28 seconds
Started Aug 15 06:20:32 PM PDT 24
Finished Aug 15 06:26:51 PM PDT 24
Peak memory 202120 kb
Host smart-a5efc4fe-b679-4d6e-ad1d-6ccd958156a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595776922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2595776922
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3732391786
Short name T679
Test name
Test status
Simulation time 331495813843 ps
CPU time 137.18 seconds
Started Aug 15 06:20:23 PM PDT 24
Finished Aug 15 06:22:41 PM PDT 24
Peak memory 202144 kb
Host smart-66e42703-05cd-464b-aea8-c97c4244703e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732391786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3732391786
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3350450961
Short name T658
Test name
Test status
Simulation time 267767647029 ps
CPU time 143.89 seconds
Started Aug 15 06:20:36 PM PDT 24
Finished Aug 15 06:23:00 PM PDT 24
Peak memory 202092 kb
Host smart-29cb10fc-f88b-40cc-ac76-8356890ab490
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350450961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3350450961
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1128271941
Short name T686
Test name
Test status
Simulation time 410257798277 ps
CPU time 238.75 seconds
Started Aug 15 06:20:23 PM PDT 24
Finished Aug 15 06:24:22 PM PDT 24
Peak memory 202140 kb
Host smart-683f1cba-a694-421e-bc1e-f907d0a9ca9f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128271941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1128271941
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.555352145
Short name T440
Test name
Test status
Simulation time 36513456008 ps
CPU time 5.73 seconds
Started Aug 15 06:20:25 PM PDT 24
Finished Aug 15 06:20:31 PM PDT 24
Peak memory 201952 kb
Host smart-1b3548b6-e751-4444-9bf5-98dd7c364649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555352145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.555352145
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2714329655
Short name T452
Test name
Test status
Simulation time 2610596158 ps
CPU time 3.77 seconds
Started Aug 15 06:20:36 PM PDT 24
Finished Aug 15 06:20:40 PM PDT 24
Peak memory 201936 kb
Host smart-13a7bba4-a7bf-44a0-8fb3-922ba16e66ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714329655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2714329655
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.688007446
Short name T361
Test name
Test status
Simulation time 5510144635 ps
CPU time 4.25 seconds
Started Aug 15 06:20:24 PM PDT 24
Finished Aug 15 06:20:28 PM PDT 24
Peak memory 201948 kb
Host smart-489d8533-aadd-42ae-ac8e-9d0accf38163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688007446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.688007446
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.702214040
Short name T134
Test name
Test status
Simulation time 162416991221 ps
CPU time 388.52 seconds
Started Aug 15 06:20:30 PM PDT 24
Finished Aug 15 06:26:59 PM PDT 24
Peak memory 202116 kb
Host smart-3b403415-af22-448f-8afd-4cded8ca691b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702214040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
702214040
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.453535330
Short name T77
Test name
Test status
Simulation time 11441249070 ps
CPU time 9.8 seconds
Started Aug 15 06:20:26 PM PDT 24
Finished Aug 15 06:20:36 PM PDT 24
Peak memory 210432 kb
Host smart-8a0830c5-2604-4656-8337-f18ae642ca09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453535330 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.453535330
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.535657928
Short name T359
Test name
Test status
Simulation time 355923896 ps
CPU time 0.85 seconds
Started Aug 15 06:20:30 PM PDT 24
Finished Aug 15 06:20:31 PM PDT 24
Peak memory 201996 kb
Host smart-10bc7ead-2be9-4d6e-a46d-fc7f8c3d8c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535657928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.535657928
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2949644317
Short name T699
Test name
Test status
Simulation time 534846428269 ps
CPU time 343.7 seconds
Started Aug 15 06:20:25 PM PDT 24
Finished Aug 15 06:26:09 PM PDT 24
Peak memory 202120 kb
Host smart-839798dc-bbd4-4047-8ddf-4dc53486b9de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949644317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2949644317
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.726108880
Short name T691
Test name
Test status
Simulation time 323272130365 ps
CPU time 352.89 seconds
Started Aug 15 06:20:26 PM PDT 24
Finished Aug 15 06:26:19 PM PDT 24
Peak memory 202120 kb
Host smart-cfd364f6-0b12-44e0-a5f8-6a5a5516a9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726108880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.726108880
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2028471471
Short name T620
Test name
Test status
Simulation time 159837566367 ps
CPU time 193.23 seconds
Started Aug 15 06:20:25 PM PDT 24
Finished Aug 15 06:23:38 PM PDT 24
Peak memory 202188 kb
Host smart-b81f6177-d6f0-4fa6-940b-bb50ff44c1d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028471471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2028471471
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3257624915
Short name T163
Test name
Test status
Simulation time 161210962439 ps
CPU time 110.2 seconds
Started Aug 15 06:20:31 PM PDT 24
Finished Aug 15 06:22:21 PM PDT 24
Peak memory 202080 kb
Host smart-1016aec4-9f9f-4ec6-8d5a-f20d2eae6c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257624915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3257624915
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.4283224561
Short name T399
Test name
Test status
Simulation time 487283188183 ps
CPU time 296.41 seconds
Started Aug 15 06:20:23 PM PDT 24
Finished Aug 15 06:25:19 PM PDT 24
Peak memory 202076 kb
Host smart-024f2433-3696-41f5-b25d-163b6cd4ca22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283224561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.4283224561
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1939902318
Short name T384
Test name
Test status
Simulation time 402340977350 ps
CPU time 484.66 seconds
Started Aug 15 06:20:26 PM PDT 24
Finished Aug 15 06:28:31 PM PDT 24
Peak memory 202072 kb
Host smart-5845b9e7-5493-4cdb-9295-c95e2d436cea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939902318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1939902318
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2541345890
Short name T738
Test name
Test status
Simulation time 33618940600 ps
CPU time 68.03 seconds
Started Aug 15 06:20:25 PM PDT 24
Finished Aug 15 06:21:33 PM PDT 24
Peak memory 201960 kb
Host smart-02f2c2e7-bbda-44e9-988e-a0b3701801c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541345890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2541345890
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3131169824
Short name T631
Test name
Test status
Simulation time 3993289721 ps
CPU time 2.57 seconds
Started Aug 15 06:20:37 PM PDT 24
Finished Aug 15 06:20:40 PM PDT 24
Peak memory 201912 kb
Host smart-db460c5c-ea82-4114-a03e-db1177e658a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131169824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3131169824
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.4255406298
Short name T448
Test name
Test status
Simulation time 6032570730 ps
CPU time 15.2 seconds
Started Aug 15 06:20:24 PM PDT 24
Finished Aug 15 06:20:40 PM PDT 24
Peak memory 201952 kb
Host smart-0bd466c0-c92f-43bd-8ef7-4bdb5d322903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255406298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.4255406298
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2246990444
Short name T594
Test name
Test status
Simulation time 210002382146 ps
CPU time 118.39 seconds
Started Aug 15 06:20:32 PM PDT 24
Finished Aug 15 06:22:30 PM PDT 24
Peak memory 202204 kb
Host smart-be7406d6-297d-4b3b-97de-b396d2f38c4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246990444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2246990444
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1595388787
Short name T94
Test name
Test status
Simulation time 2612003086 ps
CPU time 14.58 seconds
Started Aug 15 06:20:33 PM PDT 24
Finished Aug 15 06:20:48 PM PDT 24
Peak memory 210520 kb
Host smart-7b6fb9c2-6051-441f-ab6e-a7b107a9b584
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595388787 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1595388787
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.4073105124
Short name T513
Test name
Test status
Simulation time 385488670 ps
CPU time 0.8 seconds
Started Aug 15 06:20:43 PM PDT 24
Finished Aug 15 06:20:43 PM PDT 24
Peak memory 201908 kb
Host smart-9c60c720-b59b-4f53-8759-2f0596343947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073105124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.4073105124
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.793905505
Short name T772
Test name
Test status
Simulation time 176187371934 ps
CPU time 159.12 seconds
Started Aug 15 06:20:36 PM PDT 24
Finished Aug 15 06:23:15 PM PDT 24
Peak memory 202092 kb
Host smart-7aa4bad6-be4f-4dfa-b432-4db172b47a05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793905505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.793905505
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.906362486
Short name T254
Test name
Test status
Simulation time 333599157234 ps
CPU time 766.34 seconds
Started Aug 15 06:20:37 PM PDT 24
Finished Aug 15 06:33:24 PM PDT 24
Peak memory 202132 kb
Host smart-028959ab-34e9-4a2c-9c84-f87eafe07c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906362486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.906362486
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1853018445
Short name T630
Test name
Test status
Simulation time 489141462264 ps
CPU time 83.3 seconds
Started Aug 15 06:20:31 PM PDT 24
Finished Aug 15 06:21:54 PM PDT 24
Peak memory 202324 kb
Host smart-3c49a02c-8087-4deb-a98e-e6b35510be6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853018445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1853018445
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.353464042
Short name T276
Test name
Test status
Simulation time 326550754566 ps
CPU time 181.7 seconds
Started Aug 15 06:20:33 PM PDT 24
Finished Aug 15 06:23:35 PM PDT 24
Peak memory 202084 kb
Host smart-110bea12-4018-4b32-8b42-8e8437574702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353464042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.353464042
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3487879203
Short name T741
Test name
Test status
Simulation time 162529271174 ps
CPU time 185.86 seconds
Started Aug 15 06:20:32 PM PDT 24
Finished Aug 15 06:23:38 PM PDT 24
Peak memory 202128 kb
Host smart-aa817cf3-6732-4158-836b-085aaff4f088
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487879203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3487879203
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2134857910
Short name T382
Test name
Test status
Simulation time 405382245712 ps
CPU time 437.52 seconds
Started Aug 15 06:20:30 PM PDT 24
Finished Aug 15 06:27:48 PM PDT 24
Peak memory 202140 kb
Host smart-7f96e61e-3289-4fc5-a6b0-7c24c0304d15
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134857910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2134857910
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3588172301
Short name T200
Test name
Test status
Simulation time 96845482133 ps
CPU time 524.93 seconds
Started Aug 15 06:20:39 PM PDT 24
Finished Aug 15 06:29:24 PM PDT 24
Peak memory 202328 kb
Host smart-9f00ac34-0835-475a-a979-5fa0e42065dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588172301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3588172301
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1011680659
Short name T729
Test name
Test status
Simulation time 39114227640 ps
CPU time 94.55 seconds
Started Aug 15 06:20:39 PM PDT 24
Finished Aug 15 06:22:14 PM PDT 24
Peak memory 201912 kb
Host smart-4cc7ed9b-881a-496b-a0e9-1cead205de73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011680659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1011680659
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1453707053
Short name T584
Test name
Test status
Simulation time 4960271697 ps
CPU time 3.75 seconds
Started Aug 15 06:20:38 PM PDT 24
Finished Aug 15 06:20:42 PM PDT 24
Peak memory 201892 kb
Host smart-50a65467-a366-45c8-a610-066d809003c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453707053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1453707053
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.526751236
Short name T665
Test name
Test status
Simulation time 5772099703 ps
CPU time 13.18 seconds
Started Aug 15 06:20:31 PM PDT 24
Finished Aug 15 06:20:45 PM PDT 24
Peak memory 201952 kb
Host smart-353ab365-6643-4213-ab80-064fc1b00bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526751236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.526751236
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2094436110
Short name T278
Test name
Test status
Simulation time 331370027354 ps
CPU time 165.49 seconds
Started Aug 15 06:20:41 PM PDT 24
Finished Aug 15 06:23:27 PM PDT 24
Peak memory 202092 kb
Host smart-36cb03b4-b898-412e-bd08-f14ead1b04d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094436110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2094436110
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.58496739
Short name T21
Test name
Test status
Simulation time 4636960221 ps
CPU time 15.61 seconds
Started Aug 15 06:20:38 PM PDT 24
Finished Aug 15 06:20:53 PM PDT 24
Peak memory 210404 kb
Host smart-6041b98a-fc07-4ab3-8f18-9d9613d0097d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58496739 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.58496739
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1637401865
Short name T796
Test name
Test status
Simulation time 480985492 ps
CPU time 1.19 seconds
Started Aug 15 06:20:45 PM PDT 24
Finished Aug 15 06:20:46 PM PDT 24
Peak memory 201968 kb
Host smart-78df861b-441b-4d8e-9da0-7f7c898039e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637401865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1637401865
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3439629924
Short name T563
Test name
Test status
Simulation time 164973121850 ps
CPU time 378.28 seconds
Started Aug 15 06:20:44 PM PDT 24
Finished Aug 15 06:27:03 PM PDT 24
Peak memory 202092 kb
Host smart-274552b6-0532-4fa9-9b5d-82645aa7037d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439629924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3439629924
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2643134944
Short name T773
Test name
Test status
Simulation time 180331425363 ps
CPU time 331.71 seconds
Started Aug 15 06:20:45 PM PDT 24
Finished Aug 15 06:26:17 PM PDT 24
Peak memory 202108 kb
Host smart-f6fd81b1-9ffe-4cc1-81f3-f5d787fc4dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643134944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2643134944
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1576648765
Short name T298
Test name
Test status
Simulation time 323269629946 ps
CPU time 751.95 seconds
Started Aug 15 06:20:44 PM PDT 24
Finished Aug 15 06:33:16 PM PDT 24
Peak memory 202092 kb
Host smart-051ecfe5-a753-4b70-bb9c-5730916f63fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576648765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1576648765
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.855042618
Short name T596
Test name
Test status
Simulation time 488196311106 ps
CPU time 279.06 seconds
Started Aug 15 06:20:46 PM PDT 24
Finished Aug 15 06:25:25 PM PDT 24
Peak memory 202176 kb
Host smart-13ea878b-ef84-4547-9b32-887358f94aeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=855042618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.855042618
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2349576558
Short name T214
Test name
Test status
Simulation time 163995218161 ps
CPU time 366.3 seconds
Started Aug 15 06:20:49 PM PDT 24
Finished Aug 15 06:26:56 PM PDT 24
Peak memory 202104 kb
Host smart-fa814175-c84e-48b6-9ad0-ab568d127bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349576558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2349576558
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2974873573
Short name T778
Test name
Test status
Simulation time 164968642245 ps
CPU time 98.67 seconds
Started Aug 15 06:20:45 PM PDT 24
Finished Aug 15 06:22:24 PM PDT 24
Peak memory 202092 kb
Host smart-631c8b94-8257-49b1-a9a8-7a0d9d5b169b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974873573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2974873573
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.4192689914
Short name T187
Test name
Test status
Simulation time 378746476854 ps
CPU time 450.65 seconds
Started Aug 15 06:20:45 PM PDT 24
Finished Aug 15 06:28:16 PM PDT 24
Peak memory 202112 kb
Host smart-49eaa213-2f7e-407d-a5d0-7ac561132f7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192689914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.4192689914
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4119559158
Short name T427
Test name
Test status
Simulation time 196140072724 ps
CPU time 427.73 seconds
Started Aug 15 06:20:44 PM PDT 24
Finished Aug 15 06:27:52 PM PDT 24
Peak memory 202104 kb
Host smart-11ce956b-b7c3-418e-9c61-7d8933b436a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119559158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4119559158
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.945155881
Short name T776
Test name
Test status
Simulation time 136203843295 ps
CPU time 407.04 seconds
Started Aug 15 06:20:45 PM PDT 24
Finished Aug 15 06:27:32 PM PDT 24
Peak memory 202380 kb
Host smart-6536f27d-7af8-4ca7-9566-77d9086e7aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945155881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.945155881
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1910812838
Short name T396
Test name
Test status
Simulation time 46167463564 ps
CPU time 55.32 seconds
Started Aug 15 06:20:45 PM PDT 24
Finished Aug 15 06:21:40 PM PDT 24
Peak memory 201972 kb
Host smart-4a89eda4-80af-4eab-bb9e-cdf201b66b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910812838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1910812838
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2531751038
Short name T416
Test name
Test status
Simulation time 4219998089 ps
CPU time 9.06 seconds
Started Aug 15 06:20:43 PM PDT 24
Finished Aug 15 06:20:53 PM PDT 24
Peak memory 201972 kb
Host smart-6b046659-8f2e-4037-a759-6072192497a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531751038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2531751038
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4097330796
Short name T622
Test name
Test status
Simulation time 5721731129 ps
CPU time 3.25 seconds
Started Aug 15 06:20:39 PM PDT 24
Finished Aug 15 06:20:42 PM PDT 24
Peak memory 201960 kb
Host smart-fa4bf84a-40e2-49f1-a404-1a4404e28b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097330796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4097330796
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.835478378
Short name T299
Test name
Test status
Simulation time 243236512920 ps
CPU time 603.12 seconds
Started Aug 15 06:20:47 PM PDT 24
Finished Aug 15 06:30:50 PM PDT 24
Peak memory 202104 kb
Host smart-a35b0d2c-31ce-4e03-a031-0791f24e7893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835478378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
835478378
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1942681188
Short name T32
Test name
Test status
Simulation time 16178731033 ps
CPU time 15.96 seconds
Started Aug 15 06:20:46 PM PDT 24
Finished Aug 15 06:21:02 PM PDT 24
Peak memory 210676 kb
Host smart-bd712880-0728-4c62-9218-cf95b6d4485e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942681188 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1942681188
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1070407415
Short name T483
Test name
Test status
Simulation time 441136160 ps
CPU time 1.12 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:20:55 PM PDT 24
Peak memory 201924 kb
Host smart-99470b71-9a82-494e-8a5b-9656774ecbc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070407415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1070407415
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1127278369
Short name T159
Test name
Test status
Simulation time 390182864961 ps
CPU time 841.66 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:34:55 PM PDT 24
Peak memory 202092 kb
Host smart-dcf8753b-2545-49fb-9ef1-f43bcff5c4d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127278369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1127278369
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1877583656
Short name T220
Test name
Test status
Simulation time 180533465725 ps
CPU time 104.41 seconds
Started Aug 15 06:20:51 PM PDT 24
Finished Aug 15 06:22:36 PM PDT 24
Peak memory 202168 kb
Host smart-9ee85370-e12b-458d-8e8f-aa421af1434f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877583656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1877583656
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3949956755
Short name T156
Test name
Test status
Simulation time 337811365065 ps
CPU time 196.14 seconds
Started Aug 15 06:20:44 PM PDT 24
Finished Aug 15 06:24:01 PM PDT 24
Peak memory 201988 kb
Host smart-6ce9fda5-767a-489e-aa83-1d83131bbba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949956755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3949956755
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1117764912
Short name T391
Test name
Test status
Simulation time 491153093263 ps
CPU time 997.13 seconds
Started Aug 15 06:20:52 PM PDT 24
Finished Aug 15 06:37:29 PM PDT 24
Peak memory 202188 kb
Host smart-9badc7e8-8c1c-4e84-a51b-ac9d8a3584b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117764912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1117764912
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2315932450
Short name T7
Test name
Test status
Simulation time 166102460922 ps
CPU time 101.61 seconds
Started Aug 15 06:20:43 PM PDT 24
Finished Aug 15 06:22:25 PM PDT 24
Peak memory 202168 kb
Host smart-803c77a3-30e4-43fa-8fcf-bf0ebef2ad88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315932450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2315932450
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.4086433909
Short name T728
Test name
Test status
Simulation time 327869211766 ps
CPU time 703.87 seconds
Started Aug 15 06:20:46 PM PDT 24
Finished Aug 15 06:32:30 PM PDT 24
Peak memory 202108 kb
Host smart-f7fa65b3-4ad8-40c5-b3fe-2fb2008e0320
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086433909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.4086433909
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1618301486
Short name T242
Test name
Test status
Simulation time 358571559984 ps
CPU time 799.02 seconds
Started Aug 15 06:20:51 PM PDT 24
Finished Aug 15 06:34:10 PM PDT 24
Peak memory 202100 kb
Host smart-a1cd790b-bff6-4899-94ef-3bd0ce494b3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618301486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1618301486
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2710735657
Short name T555
Test name
Test status
Simulation time 194953965154 ps
CPU time 214.34 seconds
Started Aug 15 06:20:54 PM PDT 24
Finished Aug 15 06:24:28 PM PDT 24
Peak memory 202064 kb
Host smart-cc327718-eda0-4ef5-8ba9-44b10b14e37c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710735657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2710735657
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.826564543
Short name T552
Test name
Test status
Simulation time 89146078243 ps
CPU time 464.47 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:28:38 PM PDT 24
Peak memory 202456 kb
Host smart-229095b2-789b-4172-a730-2da83e5b33ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826564543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.826564543
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3256631876
Short name T471
Test name
Test status
Simulation time 31547650467 ps
CPU time 15.99 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:21:09 PM PDT 24
Peak memory 201936 kb
Host smart-6f2c8ff3-8d5f-46dc-b61a-94230099c00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256631876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3256631876
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1192491853
Short name T721
Test name
Test status
Simulation time 4967559385 ps
CPU time 3.33 seconds
Started Aug 15 06:20:52 PM PDT 24
Finished Aug 15 06:20:56 PM PDT 24
Peak memory 201976 kb
Host smart-1d7a6266-156d-493d-9d6c-d94c90870fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192491853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1192491853
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.797115132
Short name T505
Test name
Test status
Simulation time 5768400039 ps
CPU time 8.04 seconds
Started Aug 15 06:20:50 PM PDT 24
Finished Aug 15 06:20:59 PM PDT 24
Peak memory 201892 kb
Host smart-ac0f581e-fbb5-4184-bd8c-20067ea759c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797115132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.797115132
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2860040159
Short name T635
Test name
Test status
Simulation time 507167546657 ps
CPU time 247.88 seconds
Started Aug 15 06:20:54 PM PDT 24
Finished Aug 15 06:25:02 PM PDT 24
Peak memory 202188 kb
Host smart-aef4dce0-a12d-4151-9209-aad4ee9b26fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860040159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2860040159
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2848610117
Short name T626
Test name
Test status
Simulation time 462637431 ps
CPU time 1.7 seconds
Started Aug 15 06:21:19 PM PDT 24
Finished Aug 15 06:21:21 PM PDT 24
Peak memory 201972 kb
Host smart-47d8ae17-d0e1-41ca-8a88-6b8054d97206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848610117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2848610117
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1505500632
Short name T234
Test name
Test status
Simulation time 161490122408 ps
CPU time 45.85 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:20:47 PM PDT 24
Peak memory 202136 kb
Host smart-bc662f98-fbec-4cd1-886c-8c6927bb97c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505500632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1505500632
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.571238955
Short name T533
Test name
Test status
Simulation time 161840609461 ps
CPU time 94.46 seconds
Started Aug 15 06:20:06 PM PDT 24
Finished Aug 15 06:21:40 PM PDT 24
Peak memory 202124 kb
Host smart-5328e48d-427f-497c-b525-fb42a4bde33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571238955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.571238955
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.4096236557
Short name T736
Test name
Test status
Simulation time 325786522044 ps
CPU time 307.85 seconds
Started Aug 15 06:20:00 PM PDT 24
Finished Aug 15 06:25:08 PM PDT 24
Peak memory 202112 kb
Host smart-48b411fa-13d7-46e5-9d38-f5223b589820
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096236557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.4096236557
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2260955926
Short name T689
Test name
Test status
Simulation time 488055255340 ps
CPU time 395.32 seconds
Started Aug 15 06:19:55 PM PDT 24
Finished Aug 15 06:26:31 PM PDT 24
Peak memory 202000 kb
Host smart-de7b541e-8487-4e17-a392-f4afcbfd9a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260955926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2260955926
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.219325679
Short name T465
Test name
Test status
Simulation time 324723198484 ps
CPU time 744.03 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:32:27 PM PDT 24
Peak memory 202116 kb
Host smart-85d7e27d-1073-40f6-bbf4-60c727df652f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=219325679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.219325679
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1319352147
Short name T327
Test name
Test status
Simulation time 164309516562 ps
CPU time 198.64 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:23:21 PM PDT 24
Peak memory 202124 kb
Host smart-201b7984-cb6f-471a-9d0d-f17297ed2bcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319352147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1319352147
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.525914440
Short name T625
Test name
Test status
Simulation time 591898981685 ps
CPU time 1362.99 seconds
Started Aug 15 06:20:07 PM PDT 24
Finished Aug 15 06:42:50 PM PDT 24
Peak memory 202040 kb
Host smart-e8e4b744-12ae-4723-b5d3-3c1c57950fbe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525914440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.525914440
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2462095168
Short name T189
Test name
Test status
Simulation time 122175580003 ps
CPU time 421.23 seconds
Started Aug 15 06:20:05 PM PDT 24
Finished Aug 15 06:27:06 PM PDT 24
Peak memory 202328 kb
Host smart-337b21a2-9dfd-4ad8-a055-474f7bd695f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462095168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2462095168
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1254725658
Short name T792
Test name
Test status
Simulation time 38701900123 ps
CPU time 76.65 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:21:19 PM PDT 24
Peak memory 201940 kb
Host smart-f8cc4229-00a2-4644-9c30-7ce4eb7799a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254725658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1254725658
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.65478616
Short name T782
Test name
Test status
Simulation time 3548839901 ps
CPU time 1.38 seconds
Started Aug 15 06:20:04 PM PDT 24
Finished Aug 15 06:20:06 PM PDT 24
Peak memory 201976 kb
Host smart-079de66f-7f7c-41d8-ba47-4c19a774831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65478616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.65478616
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.279000404
Short name T66
Test name
Test status
Simulation time 4787697438 ps
CPU time 6.61 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:20:08 PM PDT 24
Peak memory 217496 kb
Host smart-efb4277b-416e-4aa1-b001-1c7be8825556
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279000404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.279000404
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3539077211
Short name T643
Test name
Test status
Simulation time 6008177147 ps
CPU time 14.22 seconds
Started Aug 15 06:19:58 PM PDT 24
Finished Aug 15 06:20:12 PM PDT 24
Peak memory 201896 kb
Host smart-c469ecd3-3b4d-40da-af59-4cc4f0173281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539077211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3539077211
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.693847396
Short name T212
Test name
Test status
Simulation time 284511354920 ps
CPU time 804.69 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 210604 kb
Host smart-7a745818-e247-451b-8c77-7f14ab2dd002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693847396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.693847396
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1823923404
Short name T248
Test name
Test status
Simulation time 15488330853 ps
CPU time 18 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:20:19 PM PDT 24
Peak memory 218892 kb
Host smart-2c83ef89-12bf-4f9b-bc46-d45f5efeb260
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823923404 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1823923404
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3010270515
Short name T98
Test name
Test status
Simulation time 421636527 ps
CPU time 0.89 seconds
Started Aug 15 06:20:54 PM PDT 24
Finished Aug 15 06:20:55 PM PDT 24
Peak memory 201900 kb
Host smart-8c81b278-d544-40f0-a5de-20e61299eb31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010270515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3010270515
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2646087087
Short name T97
Test name
Test status
Simulation time 345573648929 ps
CPU time 49.46 seconds
Started Aug 15 06:20:54 PM PDT 24
Finished Aug 15 06:21:43 PM PDT 24
Peak memory 202000 kb
Host smart-0b3d1859-22d4-4dcd-8933-e3a68d75282a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646087087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2646087087
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3261545779
Short name T480
Test name
Test status
Simulation time 489749103168 ps
CPU time 1146.32 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:40:00 PM PDT 24
Peak memory 202144 kb
Host smart-c45420fe-dbf6-4ba3-8cb8-0d57a27ddb7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261545779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3261545779
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3045936519
Short name T230
Test name
Test status
Simulation time 333937080257 ps
CPU time 777.21 seconds
Started Aug 15 06:20:55 PM PDT 24
Finished Aug 15 06:33:52 PM PDT 24
Peak memory 202052 kb
Host smart-133071ef-011d-4bcb-83c5-904ef0a80c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045936519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3045936519
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2337953606
Short name T608
Test name
Test status
Simulation time 325548677273 ps
CPU time 188.55 seconds
Started Aug 15 06:20:51 PM PDT 24
Finished Aug 15 06:23:59 PM PDT 24
Peak memory 202084 kb
Host smart-876384bb-8d97-49d3-901e-00fc589c8b42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337953606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2337953606
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.984674713
Short name T257
Test name
Test status
Simulation time 356124203458 ps
CPU time 401.79 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:27:34 PM PDT 24
Peak memory 202152 kb
Host smart-fb3b44c3-c4d2-4126-8beb-c377bb52737b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984674713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.984674713
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3639412433
Short name T549
Test name
Test status
Simulation time 582209563644 ps
CPU time 655.32 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:31:49 PM PDT 24
Peak memory 202108 kb
Host smart-fda88d07-4c57-47f8-aa9c-fbe5ccc4ffbd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639412433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3639412433
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2561082878
Short name T389
Test name
Test status
Simulation time 106755281599 ps
CPU time 340.86 seconds
Started Aug 15 06:20:54 PM PDT 24
Finished Aug 15 06:26:35 PM PDT 24
Peak memory 202352 kb
Host smart-2bda5217-906c-40e5-ad80-e72b490d7ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561082878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2561082878
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1117795996
Short name T470
Test name
Test status
Simulation time 30150052652 ps
CPU time 69.34 seconds
Started Aug 15 06:20:51 PM PDT 24
Finished Aug 15 06:22:01 PM PDT 24
Peak memory 201900 kb
Host smart-75cfb228-f523-4745-9cbd-293ba9de5266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117795996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1117795996
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3586519179
Short name T619
Test name
Test status
Simulation time 3478940972 ps
CPU time 4.76 seconds
Started Aug 15 06:20:52 PM PDT 24
Finished Aug 15 06:20:57 PM PDT 24
Peak memory 201924 kb
Host smart-b802fd33-1ab3-4fd0-8a67-f5b2d66c5870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586519179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3586519179
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1014044328
Short name T80
Test name
Test status
Simulation time 5927093277 ps
CPU time 4.41 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:20:58 PM PDT 24
Peak memory 201928 kb
Host smart-3c411f75-015f-447c-a338-5823c0f66ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014044328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1014044328
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3099817625
Short name T81
Test name
Test status
Simulation time 96717796091 ps
CPU time 451.09 seconds
Started Aug 15 06:20:55 PM PDT 24
Finished Aug 15 06:28:26 PM PDT 24
Peak memory 202248 kb
Host smart-aa926c2d-e2a1-4c4a-93b4-dd642eaad3c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099817625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3099817625
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3310995300
Short name T99
Test name
Test status
Simulation time 2929502921 ps
CPU time 4.09 seconds
Started Aug 15 06:20:53 PM PDT 24
Finished Aug 15 06:20:58 PM PDT 24
Peak memory 202188 kb
Host smart-24f8b288-d3ac-4f2b-81c0-7a3bf635c1e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310995300 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3310995300
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2877099452
Short name T540
Test name
Test status
Simulation time 307255218 ps
CPU time 0.72 seconds
Started Aug 15 06:21:01 PM PDT 24
Finished Aug 15 06:21:02 PM PDT 24
Peak memory 201944 kb
Host smart-add46c86-25ce-43eb-8a2f-296740f6a243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877099452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2877099452
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2152686847
Short name T177
Test name
Test status
Simulation time 351097764234 ps
CPU time 52.2 seconds
Started Aug 15 06:21:03 PM PDT 24
Finished Aug 15 06:21:55 PM PDT 24
Peak memory 202144 kb
Host smart-dbbae1c4-8d17-4347-bd9c-a21fab25dfac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152686847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2152686847
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1819506236
Short name T245
Test name
Test status
Simulation time 351713022822 ps
CPU time 183.87 seconds
Started Aug 15 06:21:04 PM PDT 24
Finished Aug 15 06:24:08 PM PDT 24
Peak memory 202212 kb
Host smart-7f537d12-3bda-49eb-8cdd-10f7f37ab6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819506236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1819506236
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3153692762
Short name T262
Test name
Test status
Simulation time 491382502315 ps
CPU time 297.54 seconds
Started Aug 15 06:21:02 PM PDT 24
Finished Aug 15 06:26:00 PM PDT 24
Peak memory 202148 kb
Host smart-ed7b8fce-335a-40b7-a12d-a17848e7ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153692762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3153692762
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3862346374
Short name T462
Test name
Test status
Simulation time 163005067971 ps
CPU time 147.15 seconds
Started Aug 15 06:21:02 PM PDT 24
Finished Aug 15 06:23:29 PM PDT 24
Peak memory 202124 kb
Host smart-0569575b-32a6-4cbe-963e-522063c0e3d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862346374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3862346374
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2532118265
Short name T175
Test name
Test status
Simulation time 506059566935 ps
CPU time 273.01 seconds
Started Aug 15 06:21:03 PM PDT 24
Finished Aug 15 06:25:36 PM PDT 24
Peak memory 202204 kb
Host smart-ae44892b-e420-4c6b-872a-0bc28333eda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532118265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2532118265
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1470917261
Short name T171
Test name
Test status
Simulation time 504112667565 ps
CPU time 635.43 seconds
Started Aug 15 06:21:04 PM PDT 24
Finished Aug 15 06:31:40 PM PDT 24
Peak memory 202064 kb
Host smart-df834470-9c2a-4180-b7bc-fa3a7aece8cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470917261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1470917261
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.955210763
Short name T599
Test name
Test status
Simulation time 176559504390 ps
CPU time 108.73 seconds
Started Aug 15 06:21:03 PM PDT 24
Finished Aug 15 06:22:52 PM PDT 24
Peak memory 202068 kb
Host smart-73423c55-497f-4efb-9e27-24ece463feb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955210763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.955210763
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1125977173
Short name T613
Test name
Test status
Simulation time 195563882684 ps
CPU time 107.92 seconds
Started Aug 15 06:21:02 PM PDT 24
Finished Aug 15 06:22:50 PM PDT 24
Peak memory 202116 kb
Host smart-4e36c701-f827-4130-872d-67c1cd9b7a81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125977173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1125977173
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2495129485
Short name T508
Test name
Test status
Simulation time 48755119224 ps
CPU time 114.07 seconds
Started Aug 15 06:21:00 PM PDT 24
Finished Aug 15 06:22:55 PM PDT 24
Peak memory 201936 kb
Host smart-cd7308e0-2d36-4014-9881-2c28883c0f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495129485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2495129485
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.292361030
Short name T356
Test name
Test status
Simulation time 4485732654 ps
CPU time 1.52 seconds
Started Aug 15 06:21:02 PM PDT 24
Finished Aug 15 06:21:04 PM PDT 24
Peak memory 201960 kb
Host smart-0dd2a402-3d35-4966-9506-858ca32101eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292361030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.292361030
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3976883989
Short name T68
Test name
Test status
Simulation time 5944936283 ps
CPU time 14.81 seconds
Started Aug 15 06:21:02 PM PDT 24
Finished Aug 15 06:21:16 PM PDT 24
Peak memory 201904 kb
Host smart-4d7aeee6-5eb6-4d7f-b0e4-75c18b3587bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976883989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3976883989
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3324826715
Short name T259
Test name
Test status
Simulation time 334723636794 ps
CPU time 355.25 seconds
Started Aug 15 06:21:02 PM PDT 24
Finished Aug 15 06:26:58 PM PDT 24
Peak memory 202124 kb
Host smart-56dd20c6-4cf6-4c51-ac01-4932713e0613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324826715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3324826715
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1031226179
Short name T31
Test name
Test status
Simulation time 42375714337 ps
CPU time 11.85 seconds
Started Aug 15 06:21:01 PM PDT 24
Finished Aug 15 06:21:13 PM PDT 24
Peak memory 214452 kb
Host smart-2261be2c-bfa3-4c64-9aae-a53767127e94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031226179 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1031226179
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.171313717
Short name T550
Test name
Test status
Simulation time 388620492 ps
CPU time 1.02 seconds
Started Aug 15 06:21:06 PM PDT 24
Finished Aug 15 06:21:07 PM PDT 24
Peak memory 201960 kb
Host smart-6f21f9b8-7486-4590-b4bf-76f95041b1db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171313717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.171313717
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2200041722
Short name T339
Test name
Test status
Simulation time 555640747587 ps
CPU time 535.83 seconds
Started Aug 15 06:21:07 PM PDT 24
Finished Aug 15 06:30:03 PM PDT 24
Peak memory 202164 kb
Host smart-92f2af43-61f8-4fc3-8689-8546f4a1be69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200041722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2200041722
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3374648838
Short name T670
Test name
Test status
Simulation time 163313455909 ps
CPU time 363.28 seconds
Started Aug 15 06:21:14 PM PDT 24
Finished Aug 15 06:27:18 PM PDT 24
Peak memory 202136 kb
Host smart-d64cb104-3693-4255-94aa-292c394a40a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374648838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3374648838
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.91315694
Short name T798
Test name
Test status
Simulation time 165337909965 ps
CPU time 99.68 seconds
Started Aug 15 06:21:03 PM PDT 24
Finished Aug 15 06:22:43 PM PDT 24
Peak memory 202136 kb
Host smart-ce2eddb3-8559-49e6-b554-ea43a4f9c555
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=91315694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt
_fixed.91315694
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2554964488
Short name T324
Test name
Test status
Simulation time 166977897673 ps
CPU time 167.31 seconds
Started Aug 15 06:21:03 PM PDT 24
Finished Aug 15 06:23:50 PM PDT 24
Peak memory 202096 kb
Host smart-0ab474a8-035f-4f47-8826-d01d9b4c0fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554964488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2554964488
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.744576160
Short name T797
Test name
Test status
Simulation time 325197400311 ps
CPU time 745.07 seconds
Started Aug 15 06:21:02 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 202116 kb
Host smart-a84c1386-2032-4d8c-aef7-0f91e26eeeda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=744576160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.744576160
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3800280427
Short name T239
Test name
Test status
Simulation time 541103675889 ps
CPU time 781.85 seconds
Started Aug 15 06:21:02 PM PDT 24
Finished Aug 15 06:34:05 PM PDT 24
Peak memory 202140 kb
Host smart-ce84bec4-ff34-4a21-8d26-b9daf310b52d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800280427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3800280427
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.128957440
Short name T514
Test name
Test status
Simulation time 192437883895 ps
CPU time 453.81 seconds
Started Aug 15 06:21:02 PM PDT 24
Finished Aug 15 06:28:37 PM PDT 24
Peak memory 202144 kb
Host smart-d700098f-8136-4b5c-bc97-a4d0643f19f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128957440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.128957440
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1684299943
Short name T567
Test name
Test status
Simulation time 46832471086 ps
CPU time 23.64 seconds
Started Aug 15 06:21:08 PM PDT 24
Finished Aug 15 06:21:32 PM PDT 24
Peak memory 201960 kb
Host smart-553bd87a-7044-4ac7-85be-2667bf7ae1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684299943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1684299943
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.695051918
Short name T85
Test name
Test status
Simulation time 3193424859 ps
CPU time 1.91 seconds
Started Aug 15 06:21:10 PM PDT 24
Finished Aug 15 06:21:12 PM PDT 24
Peak memory 201952 kb
Host smart-2c9e3b84-0730-4b47-88f5-eb4116c4957b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695051918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.695051918
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3831313829
Short name T753
Test name
Test status
Simulation time 5664288438 ps
CPU time 8.59 seconds
Started Aug 15 06:21:01 PM PDT 24
Finished Aug 15 06:21:10 PM PDT 24
Peak memory 201956 kb
Host smart-32e2774e-9200-4ea0-a2ba-8c72e68f660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831313829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3831313829
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3874513836
Short name T8
Test name
Test status
Simulation time 336751190817 ps
CPU time 373.17 seconds
Started Aug 15 06:21:06 PM PDT 24
Finished Aug 15 06:27:19 PM PDT 24
Peak memory 202096 kb
Host smart-31db19f8-c129-49db-84a0-548c094e94c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874513836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3874513836
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1431012900
Short name T636
Test name
Test status
Simulation time 556155640 ps
CPU time 0.73 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:21:16 PM PDT 24
Peak memory 201984 kb
Host smart-497ec87e-a7d3-4d78-9bc1-bc145273d990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431012900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1431012900
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.799422853
Short name T318
Test name
Test status
Simulation time 160040575218 ps
CPU time 355.73 seconds
Started Aug 15 06:21:09 PM PDT 24
Finished Aug 15 06:27:05 PM PDT 24
Peak memory 202088 kb
Host smart-3a3eb0db-2225-4591-9768-89a561638f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799422853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.799422853
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3701175835
Short name T663
Test name
Test status
Simulation time 166933719644 ps
CPU time 195.32 seconds
Started Aug 15 06:21:07 PM PDT 24
Finished Aug 15 06:24:22 PM PDT 24
Peak memory 202120 kb
Host smart-b82822fe-3c18-44a7-a4ef-6d5852b9d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701175835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3701175835
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2783094757
Short name T730
Test name
Test status
Simulation time 157201044099 ps
CPU time 182.63 seconds
Started Aug 15 06:21:15 PM PDT 24
Finished Aug 15 06:24:18 PM PDT 24
Peak memory 202176 kb
Host smart-e074d70c-d0b8-4d0f-a874-7fb3f768424f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783094757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2783094757
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3688235999
Short name T501
Test name
Test status
Simulation time 158717097202 ps
CPU time 351.74 seconds
Started Aug 15 06:21:08 PM PDT 24
Finished Aug 15 06:27:00 PM PDT 24
Peak memory 202128 kb
Host smart-1f1cbe63-71d2-4d4c-a0af-ec508a7234cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688235999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3688235999
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3620355163
Short name T390
Test name
Test status
Simulation time 324844101286 ps
CPU time 389.84 seconds
Started Aug 15 06:21:09 PM PDT 24
Finished Aug 15 06:27:39 PM PDT 24
Peak memory 202036 kb
Host smart-9483ae89-3016-4600-b169-10fffc13db1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620355163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3620355163
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3573124332
Short name T307
Test name
Test status
Simulation time 177260055422 ps
CPU time 182.96 seconds
Started Aug 15 06:21:09 PM PDT 24
Finished Aug 15 06:24:12 PM PDT 24
Peak memory 202164 kb
Host smart-2500ec88-6983-429b-b96e-e3a92173611a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573124332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3573124332
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1785015778
Short name T648
Test name
Test status
Simulation time 376294767797 ps
CPU time 137.16 seconds
Started Aug 15 06:21:08 PM PDT 24
Finished Aug 15 06:23:26 PM PDT 24
Peak memory 202168 kb
Host smart-bcc9b535-5b53-4458-82e6-08886325e22a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785015778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1785015778
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.611773538
Short name T545
Test name
Test status
Simulation time 59194368340 ps
CPU time 313.51 seconds
Started Aug 15 06:21:07 PM PDT 24
Finished Aug 15 06:26:21 PM PDT 24
Peak memory 202380 kb
Host smart-140ebda0-39e1-438a-a5f8-002c6a728df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611773538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.611773538
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1235904646
Short name T27
Test name
Test status
Simulation time 36270058387 ps
CPU time 83.93 seconds
Started Aug 15 06:21:09 PM PDT 24
Finished Aug 15 06:22:33 PM PDT 24
Peak memory 201876 kb
Host smart-767a2f9f-ff24-45ca-bad5-6df13801cfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235904646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1235904646
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2893138089
Short name T579
Test name
Test status
Simulation time 5648353447 ps
CPU time 11.33 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:21:27 PM PDT 24
Peak memory 201968 kb
Host smart-6c5670f2-9c48-4090-b3f2-edfb74c3cc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893138089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2893138089
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3343255811
Short name T642
Test name
Test status
Simulation time 5648763260 ps
CPU time 12.16 seconds
Started Aug 15 06:21:10 PM PDT 24
Finished Aug 15 06:21:22 PM PDT 24
Peak memory 201952 kb
Host smart-238dc57c-e183-4a8c-9e10-9059eb89bf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343255811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3343255811
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1356179295
Short name T147
Test name
Test status
Simulation time 192292131211 ps
CPU time 208.99 seconds
Started Aug 15 06:21:10 PM PDT 24
Finished Aug 15 06:24:39 PM PDT 24
Peak memory 202140 kb
Host smart-6dbae493-f714-4ca6-8ac4-12dd38d5df1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356179295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1356179295
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.86356659
Short name T701
Test name
Test status
Simulation time 6384358017 ps
CPU time 4.36 seconds
Started Aug 15 06:21:09 PM PDT 24
Finished Aug 15 06:21:14 PM PDT 24
Peak memory 202104 kb
Host smart-d8d843b1-feb9-4a5a-aef9-c182d7ef70d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86356659 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.86356659
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2821123672
Short name T780
Test name
Test status
Simulation time 541209761 ps
CPU time 0.94 seconds
Started Aug 15 06:21:18 PM PDT 24
Finished Aug 15 06:21:19 PM PDT 24
Peak memory 201976 kb
Host smart-e2423a00-a7c3-4409-840f-98116b1a0f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821123672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2821123672
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2721714685
Short name T240
Test name
Test status
Simulation time 517575791897 ps
CPU time 132.11 seconds
Started Aug 15 06:21:17 PM PDT 24
Finished Aug 15 06:23:29 PM PDT 24
Peak memory 202176 kb
Host smart-f64d87bf-7d29-4e26-9884-eaaa6c5de5ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721714685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2721714685
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.419162006
Short name T321
Test name
Test status
Simulation time 510974754137 ps
CPU time 1182.93 seconds
Started Aug 15 06:21:22 PM PDT 24
Finished Aug 15 06:41:05 PM PDT 24
Peak memory 202128 kb
Host smart-489a5da8-e4bf-4c44-979b-cbc20252dfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419162006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.419162006
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1206166
Short name T341
Test name
Test status
Simulation time 169324325203 ps
CPU time 193.96 seconds
Started Aug 15 06:21:15 PM PDT 24
Finished Aug 15 06:24:29 PM PDT 24
Peak memory 202064 kb
Host smart-3d5b0103-0723-4291-b5ef-6b0a3ea4d26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1206166
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2249756233
Short name T495
Test name
Test status
Simulation time 487095461240 ps
CPU time 1117.58 seconds
Started Aug 15 06:21:22 PM PDT 24
Finished Aug 15 06:40:00 PM PDT 24
Peak memory 202192 kb
Host smart-f6bef820-5db3-4bbd-bf05-f4bc10868355
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249756233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2249756233
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2116164430
Short name T453
Test name
Test status
Simulation time 492581856214 ps
CPU time 1160.84 seconds
Started Aug 15 06:21:17 PM PDT 24
Finished Aug 15 06:40:38 PM PDT 24
Peak memory 202192 kb
Host smart-194a02c1-de32-4e09-92f7-b17cb3236383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116164430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2116164430
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1492678856
Short name T544
Test name
Test status
Simulation time 486857205615 ps
CPU time 514.3 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:29:51 PM PDT 24
Peak memory 202108 kb
Host smart-b26b3588-fecc-4f6b-8868-78434662773e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492678856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1492678856
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1496960086
Short name T155
Test name
Test status
Simulation time 167930559264 ps
CPU time 362.62 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:27:19 PM PDT 24
Peak memory 202116 kb
Host smart-a0118a46-5cfa-4cdc-9259-64ea03054d35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496960086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1496960086
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1587446092
Short name T419
Test name
Test status
Simulation time 192609256335 ps
CPU time 212.74 seconds
Started Aug 15 06:21:17 PM PDT 24
Finished Aug 15 06:24:50 PM PDT 24
Peak memory 202116 kb
Host smart-1db04cf8-147f-43e1-a90b-08621c4e4c6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587446092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1587446092
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1165072305
Short name T355
Test name
Test status
Simulation time 131590229133 ps
CPU time 683.81 seconds
Started Aug 15 06:21:17 PM PDT 24
Finished Aug 15 06:32:40 PM PDT 24
Peak memory 202360 kb
Host smart-36ce5cf5-b3cd-4a1c-8cb9-c046a0d8be23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165072305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1165072305
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2512929129
Short name T435
Test name
Test status
Simulation time 33687382032 ps
CPU time 73.91 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:22:30 PM PDT 24
Peak memory 201956 kb
Host smart-ff49a90f-e8a3-44ec-a7ba-328c23bffb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512929129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2512929129
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.524999743
Short name T395
Test name
Test status
Simulation time 3579370441 ps
CPU time 9.08 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:21:25 PM PDT 24
Peak memory 201904 kb
Host smart-34ac3084-8ea0-4d58-9efb-85cc7a178b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524999743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.524999743
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1738735804
Short name T775
Test name
Test status
Simulation time 5976653004 ps
CPU time 10.38 seconds
Started Aug 15 06:21:07 PM PDT 24
Finished Aug 15 06:21:17 PM PDT 24
Peak memory 201904 kb
Host smart-71a6230d-ebe7-47cf-bce3-6e1c06776c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738735804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1738735804
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.763780069
Short name T751
Test name
Test status
Simulation time 165084758156 ps
CPU time 32.36 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:21:48 PM PDT 24
Peak memory 202052 kb
Host smart-ea31780f-be8c-4f86-a802-2f36e0173e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763780069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
763780069
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2785377675
Short name T13
Test name
Test status
Simulation time 235415119591 ps
CPU time 24.81 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:21:40 PM PDT 24
Peak memory 210492 kb
Host smart-d9bb54a2-0992-41dd-9210-dfc213994aa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785377675 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2785377675
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.928821761
Short name T365
Test name
Test status
Simulation time 483022355 ps
CPU time 0.89 seconds
Started Aug 15 06:21:24 PM PDT 24
Finished Aug 15 06:21:25 PM PDT 24
Peak memory 201968 kb
Host smart-cc9cf0e3-05e2-4389-b5fd-27d30ccac905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928821761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.928821761
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3585545472
Short name T615
Test name
Test status
Simulation time 159972939260 ps
CPU time 23.63 seconds
Started Aug 15 06:21:24 PM PDT 24
Finished Aug 15 06:21:48 PM PDT 24
Peak memory 202188 kb
Host smart-8b654a36-eddd-417b-af91-eed3a26cd2df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585545472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3585545472
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.808245434
Short name T581
Test name
Test status
Simulation time 548946705093 ps
CPU time 1276.95 seconds
Started Aug 15 06:21:27 PM PDT 24
Finished Aug 15 06:42:44 PM PDT 24
Peak memory 201388 kb
Host smart-ca49f86c-9a73-47e7-85af-dd4d7b23c7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808245434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.808245434
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1998941924
Short name T646
Test name
Test status
Simulation time 334619276287 ps
CPU time 213.45 seconds
Started Aug 15 06:21:23 PM PDT 24
Finished Aug 15 06:24:57 PM PDT 24
Peak memory 202112 kb
Host smart-d31a4cf9-7611-4650-b256-b522e145bbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998941924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1998941924
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4195821971
Short name T439
Test name
Test status
Simulation time 163002958415 ps
CPU time 362.17 seconds
Started Aug 15 06:21:21 PM PDT 24
Finished Aug 15 06:27:24 PM PDT 24
Peak memory 202120 kb
Host smart-1db444a6-70cd-4a1a-ab42-fa8276cc28d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195821971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.4195821971
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3835309256
Short name T651
Test name
Test status
Simulation time 329716390995 ps
CPU time 186.64 seconds
Started Aug 15 06:21:15 PM PDT 24
Finished Aug 15 06:24:22 PM PDT 24
Peak memory 202188 kb
Host smart-ab76f59e-7a96-4fa2-8de2-b5e24bfb0907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835309256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3835309256
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3686048205
Short name T436
Test name
Test status
Simulation time 161234469582 ps
CPU time 191.11 seconds
Started Aug 15 06:21:18 PM PDT 24
Finished Aug 15 06:24:29 PM PDT 24
Peak memory 202104 kb
Host smart-f02334df-60b7-4097-954d-b968014a4bc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686048205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3686048205
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.420419085
Short name T725
Test name
Test status
Simulation time 191394676521 ps
CPU time 119.32 seconds
Started Aug 15 06:21:24 PM PDT 24
Finished Aug 15 06:23:24 PM PDT 24
Peak memory 202072 kb
Host smart-653b747a-4b90-4202-a2ee-124d0750b009
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420419085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.420419085
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3164632346
Short name T561
Test name
Test status
Simulation time 603538026163 ps
CPU time 258.05 seconds
Started Aug 15 06:21:23 PM PDT 24
Finished Aug 15 06:25:41 PM PDT 24
Peak memory 202120 kb
Host smart-afa5d405-929d-4248-8ac7-5a60d2c13194
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164632346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3164632346
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4188635509
Short name T404
Test name
Test status
Simulation time 124097220753 ps
CPU time 602.44 seconds
Started Aug 15 06:21:27 PM PDT 24
Finished Aug 15 06:31:30 PM PDT 24
Peak memory 201460 kb
Host smart-9e82b1d5-0c29-4501-9162-69a1eb81d885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188635509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4188635509
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3751766497
Short name T494
Test name
Test status
Simulation time 36864488356 ps
CPU time 20.56 seconds
Started Aug 15 06:21:26 PM PDT 24
Finished Aug 15 06:21:46 PM PDT 24
Peak memory 201932 kb
Host smart-b54ba0d1-ccd1-4ed8-b322-f7e1695eaa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751766497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3751766497
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2462174047
Short name T788
Test name
Test status
Simulation time 4128015231 ps
CPU time 7.61 seconds
Started Aug 15 06:21:25 PM PDT 24
Finished Aug 15 06:21:33 PM PDT 24
Peak memory 201956 kb
Host smart-97f279c7-89b6-407e-bcb8-bd540948e7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462174047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2462174047
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1798978398
Short name T385
Test name
Test status
Simulation time 5730506876 ps
CPU time 14.56 seconds
Started Aug 15 06:21:16 PM PDT 24
Finished Aug 15 06:21:30 PM PDT 24
Peak memory 201880 kb
Host smart-b3e64661-45a5-4983-b78f-b78982d550c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798978398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1798978398
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3141515293
Short name T332
Test name
Test status
Simulation time 374458886820 ps
CPU time 172.46 seconds
Started Aug 15 06:21:23 PM PDT 24
Finished Aug 15 06:24:16 PM PDT 24
Peak memory 202104 kb
Host smart-41d14a16-017f-4ef7-9832-c8d544933aae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141515293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3141515293
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2925166142
Short name T627
Test name
Test status
Simulation time 1309028488 ps
CPU time 4.1 seconds
Started Aug 15 06:21:24 PM PDT 24
Finished Aug 15 06:21:28 PM PDT 24
Peak memory 202000 kb
Host smart-fa01c4ba-49b9-4e61-ad40-935ab2c7471e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925166142 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2925166142
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.978334252
Short name T376
Test name
Test status
Simulation time 460457542 ps
CPU time 1.13 seconds
Started Aug 15 06:21:32 PM PDT 24
Finished Aug 15 06:21:34 PM PDT 24
Peak memory 201936 kb
Host smart-14a87f5c-3d96-4ee9-83c4-e286960176c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978334252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.978334252
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3009664004
Short name T73
Test name
Test status
Simulation time 165869929294 ps
CPU time 190.52 seconds
Started Aug 15 06:21:30 PM PDT 24
Finished Aug 15 06:24:40 PM PDT 24
Peak memory 202088 kb
Host smart-f3993574-4398-49d2-9938-ee2ff33f7520
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009664004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3009664004
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3119645536
Short name T182
Test name
Test status
Simulation time 330561780325 ps
CPU time 205.09 seconds
Started Aug 15 06:21:23 PM PDT 24
Finished Aug 15 06:24:48 PM PDT 24
Peak memory 202104 kb
Host smart-8cd64e01-a4e6-4daa-965c-d9d26e87ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119645536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3119645536
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.808572224
Short name T744
Test name
Test status
Simulation time 498185726160 ps
CPU time 260.69 seconds
Started Aug 15 06:21:32 PM PDT 24
Finished Aug 15 06:25:53 PM PDT 24
Peak memory 202076 kb
Host smart-39509be6-2bbe-4269-850a-3538f2e3b642
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=808572224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.808572224
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3093704944
Short name T140
Test name
Test status
Simulation time 499773318102 ps
CPU time 183.53 seconds
Started Aug 15 06:21:24 PM PDT 24
Finished Aug 15 06:24:27 PM PDT 24
Peak memory 202148 kb
Host smart-15ec834f-64c9-4890-b42d-2f33d6d25254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093704944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3093704944
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1198839839
Short name T410
Test name
Test status
Simulation time 329397917663 ps
CPU time 182.76 seconds
Started Aug 15 06:21:24 PM PDT 24
Finished Aug 15 06:24:26 PM PDT 24
Peak memory 202040 kb
Host smart-f359bca0-9dc6-4e47-84e4-60b682939493
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198839839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1198839839
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3389788359
Short name T703
Test name
Test status
Simulation time 275486167909 ps
CPU time 154.38 seconds
Started Aug 15 06:21:30 PM PDT 24
Finished Aug 15 06:24:04 PM PDT 24
Peak memory 202100 kb
Host smart-41bd8913-f704-40c8-842a-f92b21d14436
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389788359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3389788359
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1433111444
Short name T173
Test name
Test status
Simulation time 416062375086 ps
CPU time 238.67 seconds
Started Aug 15 06:21:31 PM PDT 24
Finished Aug 15 06:25:29 PM PDT 24
Peak memory 202140 kb
Host smart-c2ce8b3a-5738-492d-897e-b14af09f9903
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433111444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1433111444
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3658002780
Short name T203
Test name
Test status
Simulation time 95570153578 ps
CPU time 366.59 seconds
Started Aug 15 06:21:33 PM PDT 24
Finished Aug 15 06:27:39 PM PDT 24
Peak memory 202316 kb
Host smart-9f9ec42e-b3dd-4de6-8593-5d124a99582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658002780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3658002780
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3682346887
Short name T662
Test name
Test status
Simulation time 31040776323 ps
CPU time 70.32 seconds
Started Aug 15 06:21:31 PM PDT 24
Finished Aug 15 06:22:41 PM PDT 24
Peak memory 201976 kb
Host smart-3cfbb891-c121-4599-85f2-b4520e8ffd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682346887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3682346887
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.188879969
Short name T92
Test name
Test status
Simulation time 4920872609 ps
CPU time 3.52 seconds
Started Aug 15 06:21:29 PM PDT 24
Finished Aug 15 06:21:33 PM PDT 24
Peak memory 201912 kb
Host smart-037f94fe-ec71-4dee-880a-f525a47167e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188879969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.188879969
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3270414416
Short name T589
Test name
Test status
Simulation time 6100400727 ps
CPU time 4.37 seconds
Started Aug 15 06:21:25 PM PDT 24
Finished Aug 15 06:21:29 PM PDT 24
Peak memory 201976 kb
Host smart-7ccadeb0-2785-46ab-af3a-98bfd38fcae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270414416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3270414416
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.661778933
Short name T19
Test name
Test status
Simulation time 3383168854 ps
CPU time 16.58 seconds
Started Aug 15 06:21:33 PM PDT 24
Finished Aug 15 06:21:50 PM PDT 24
Peak memory 210700 kb
Host smart-5adc4a68-6ea2-48dd-a7ff-219b755fd71a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661778933 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.661778933
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.83259480
Short name T553
Test name
Test status
Simulation time 423761077 ps
CPU time 0.89 seconds
Started Aug 15 06:21:44 PM PDT 24
Finished Aug 15 06:21:45 PM PDT 24
Peak memory 201940 kb
Host smart-25265b81-1d8b-46ad-83bd-9b9a7ea83153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83259480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.83259480
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1650317751
Short name T29
Test name
Test status
Simulation time 328637133274 ps
CPU time 69.87 seconds
Started Aug 15 06:21:38 PM PDT 24
Finished Aug 15 06:22:48 PM PDT 24
Peak memory 202156 kb
Host smart-c0376a92-789e-4dc8-b972-c7771592e77f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650317751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1650317751
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.659458465
Short name T141
Test name
Test status
Simulation time 331191956454 ps
CPU time 814.08 seconds
Started Aug 15 06:21:37 PM PDT 24
Finished Aug 15 06:35:11 PM PDT 24
Peak memory 202144 kb
Host smart-98af98a4-d2f6-4307-bc63-9632e1436303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659458465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.659458465
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2605091288
Short name T226
Test name
Test status
Simulation time 161873733405 ps
CPU time 197.5 seconds
Started Aug 15 06:21:39 PM PDT 24
Finished Aug 15 06:24:57 PM PDT 24
Peak memory 202116 kb
Host smart-cf277c35-ceb8-437f-8726-fdbe31316c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605091288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2605091288
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1752657526
Short name T364
Test name
Test status
Simulation time 167015090735 ps
CPU time 368.72 seconds
Started Aug 15 06:21:37 PM PDT 24
Finished Aug 15 06:27:46 PM PDT 24
Peak memory 202140 kb
Host smart-51b317b8-0a4e-4823-b9d3-036cb8ee2279
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752657526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1752657526
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1598847294
Short name T634
Test name
Test status
Simulation time 491704222888 ps
CPU time 336.42 seconds
Started Aug 15 06:21:37 PM PDT 24
Finished Aug 15 06:27:14 PM PDT 24
Peak memory 202136 kb
Host smart-e73ff09a-1ef4-4957-b571-a1864bf8fd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598847294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1598847294
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4127070530
Short name T457
Test name
Test status
Simulation time 330244482054 ps
CPU time 409.23 seconds
Started Aug 15 06:21:37 PM PDT 24
Finished Aug 15 06:28:26 PM PDT 24
Peak memory 202076 kb
Host smart-678ceedc-9bb0-45f7-bf26-69dd25f49c3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127070530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4127070530
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.403322595
Short name T523
Test name
Test status
Simulation time 191449560538 ps
CPU time 320.28 seconds
Started Aug 15 06:21:37 PM PDT 24
Finished Aug 15 06:26:58 PM PDT 24
Peak memory 202072 kb
Host smart-8b1b94d2-ff56-4443-91c0-ac03f2a2889d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403322595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.403322595
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3385157789
Short name T591
Test name
Test status
Simulation time 414423043800 ps
CPU time 239.54 seconds
Started Aug 15 06:21:37 PM PDT 24
Finished Aug 15 06:25:36 PM PDT 24
Peak memory 202144 kb
Host smart-1de72b47-2aeb-4767-b20d-a326f0a26c1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385157789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3385157789
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3091063106
Short name T755
Test name
Test status
Simulation time 119204262954 ps
CPU time 647.51 seconds
Started Aug 15 06:21:43 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 202372 kb
Host smart-be07d2fa-624d-446a-bfda-06a613066d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091063106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3091063106
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.768158994
Short name T783
Test name
Test status
Simulation time 45672138430 ps
CPU time 55.87 seconds
Started Aug 15 06:21:46 PM PDT 24
Finished Aug 15 06:22:42 PM PDT 24
Peak memory 201960 kb
Host smart-86bc1bad-e988-4c4a-8784-2657c22c3927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768158994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.768158994
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1483837084
Short name T443
Test name
Test status
Simulation time 3309467508 ps
CPU time 4.89 seconds
Started Aug 15 06:21:38 PM PDT 24
Finished Aug 15 06:21:43 PM PDT 24
Peak memory 201948 kb
Host smart-85a2e753-a0eb-4dcb-88d2-6ecc8202e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483837084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1483837084
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1224485277
Short name T735
Test name
Test status
Simulation time 5939177811 ps
CPU time 2.92 seconds
Started Aug 15 06:21:37 PM PDT 24
Finished Aug 15 06:21:40 PM PDT 24
Peak memory 201908 kb
Host smart-6f1d0e62-5759-4e23-8806-8a0e8118a1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224485277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1224485277
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1171029598
Short name T325
Test name
Test status
Simulation time 478506151548 ps
CPU time 650.1 seconds
Started Aug 15 06:21:44 PM PDT 24
Finished Aug 15 06:32:34 PM PDT 24
Peak memory 202360 kb
Host smart-f21b048e-3160-4244-93c0-2533f226607f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171029598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1171029598
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1031915219
Short name T570
Test name
Test status
Simulation time 61316223694 ps
CPU time 27.98 seconds
Started Aug 15 06:21:49 PM PDT 24
Finished Aug 15 06:22:17 PM PDT 24
Peak memory 210468 kb
Host smart-cb3bb110-af64-4c77-843e-738bc8522baf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031915219 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1031915219
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2998395930
Short name T726
Test name
Test status
Simulation time 340878604 ps
CPU time 1.03 seconds
Started Aug 15 06:21:56 PM PDT 24
Finished Aug 15 06:21:57 PM PDT 24
Peak memory 201980 kb
Host smart-48c9fe82-47d1-4091-9851-c62ba68e6a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998395930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2998395930
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.887547443
Short name T277
Test name
Test status
Simulation time 180328391873 ps
CPU time 412.5 seconds
Started Aug 15 06:21:52 PM PDT 24
Finished Aug 15 06:28:45 PM PDT 24
Peak memory 202124 kb
Host smart-8a6e6326-b990-4ae4-a4af-4425eef849fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887547443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.887547443
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.632122549
Short name T145
Test name
Test status
Simulation time 185242739197 ps
CPU time 41.25 seconds
Started Aug 15 06:21:52 PM PDT 24
Finished Aug 15 06:22:33 PM PDT 24
Peak memory 202144 kb
Host smart-de7996ff-d47b-43fe-8e71-bfaff8beab28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632122549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.632122549
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3625476228
Short name T760
Test name
Test status
Simulation time 492422880857 ps
CPU time 261.49 seconds
Started Aug 15 06:21:43 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 202120 kb
Host smart-72bcb438-15fc-47d2-8459-4c793c1b5f43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625476228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3625476228
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.174417760
Short name T704
Test name
Test status
Simulation time 494983465185 ps
CPU time 211.4 seconds
Started Aug 15 06:21:44 PM PDT 24
Finished Aug 15 06:25:16 PM PDT 24
Peak memory 202116 kb
Host smart-0ef9e052-893a-48b5-8865-e0a1dcbaed10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=174417760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.174417760
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3495990583
Short name T232
Test name
Test status
Simulation time 194512380174 ps
CPU time 119.62 seconds
Started Aug 15 06:21:49 PM PDT 24
Finished Aug 15 06:23:49 PM PDT 24
Peak memory 202148 kb
Host smart-c19d14b0-80e0-4616-96fa-fdf60b3f6112
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495990583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3495990583
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3719406829
Short name T790
Test name
Test status
Simulation time 386358399122 ps
CPU time 240.99 seconds
Started Aug 15 06:21:49 PM PDT 24
Finished Aug 15 06:25:50 PM PDT 24
Peak memory 202132 kb
Host smart-3f799007-9685-46e1-80e8-477bebc307d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719406829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3719406829
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.4015519800
Short name T202
Test name
Test status
Simulation time 96752563534 ps
CPU time 538.72 seconds
Started Aug 15 06:21:53 PM PDT 24
Finished Aug 15 06:30:51 PM PDT 24
Peak memory 202432 kb
Host smart-02088f15-0d11-4e30-af98-9ad20a7033c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015519800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.4015519800
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.404956495
Short name T491
Test name
Test status
Simulation time 41432676243 ps
CPU time 85.64 seconds
Started Aug 15 06:21:53 PM PDT 24
Finished Aug 15 06:23:19 PM PDT 24
Peak memory 201904 kb
Host smart-f78acc19-66c7-4747-a1e8-8ae03b473159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404956495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.404956495
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2339011008
Short name T617
Test name
Test status
Simulation time 3480713046 ps
CPU time 8.69 seconds
Started Aug 15 06:21:53 PM PDT 24
Finished Aug 15 06:22:01 PM PDT 24
Peak memory 201920 kb
Host smart-fe8f0218-8a22-49e7-ae72-97371363f04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339011008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2339011008
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1489159561
Short name T660
Test name
Test status
Simulation time 5488109858 ps
CPU time 3.88 seconds
Started Aug 15 06:21:47 PM PDT 24
Finished Aug 15 06:21:52 PM PDT 24
Peak memory 201940 kb
Host smart-e4a5ae00-93dc-49db-b5fa-86569d3a74a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489159561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1489159561
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3215624771
Short name T60
Test name
Test status
Simulation time 651092396 ps
CPU time 0.75 seconds
Started Aug 15 06:22:01 PM PDT 24
Finished Aug 15 06:22:02 PM PDT 24
Peak memory 201992 kb
Host smart-d4ce5146-43b4-4b66-81b8-67fa0b29cc92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215624771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3215624771
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1721523484
Short name T183
Test name
Test status
Simulation time 333271382817 ps
CPU time 406.76 seconds
Started Aug 15 06:22:01 PM PDT 24
Finished Aug 15 06:28:48 PM PDT 24
Peak memory 202144 kb
Host smart-d912fe8f-8931-4691-9c42-9bc23e581e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721523484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1721523484
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1983916631
Short name T130
Test name
Test status
Simulation time 327492226854 ps
CPU time 196.22 seconds
Started Aug 15 06:21:56 PM PDT 24
Finished Aug 15 06:25:12 PM PDT 24
Peak memory 202124 kb
Host smart-09a474f5-cfbc-4306-ab11-f7fdf9ec5644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983916631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1983916631
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1047545768
Short name T369
Test name
Test status
Simulation time 503081527273 ps
CPU time 881.84 seconds
Started Aug 15 06:21:52 PM PDT 24
Finished Aug 15 06:36:34 PM PDT 24
Peak memory 202120 kb
Host smart-73246eb0-b72a-4041-a050-3501badfd7ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047545768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1047545768
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1630539414
Short name T731
Test name
Test status
Simulation time 167398043351 ps
CPU time 104.85 seconds
Started Aug 15 06:21:53 PM PDT 24
Finished Aug 15 06:23:38 PM PDT 24
Peak memory 202188 kb
Host smart-5eb3b01b-23ea-4604-8392-4421212a3da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630539414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1630539414
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2012978637
Short name T683
Test name
Test status
Simulation time 166188154256 ps
CPU time 381.71 seconds
Started Aug 15 06:21:52 PM PDT 24
Finished Aug 15 06:28:14 PM PDT 24
Peak memory 202084 kb
Host smart-042881de-1b8b-4feb-8b32-c084cd60ab96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012978637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2012978637
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2733566959
Short name T343
Test name
Test status
Simulation time 178360923461 ps
CPU time 98.7 seconds
Started Aug 15 06:21:52 PM PDT 24
Finished Aug 15 06:23:31 PM PDT 24
Peak memory 202072 kb
Host smart-1f8585dc-78fd-4a6c-b19b-147a1af85759
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733566959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2733566959
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2837425349
Short name T24
Test name
Test status
Simulation time 403048238602 ps
CPU time 213.63 seconds
Started Aug 15 06:21:51 PM PDT 24
Finished Aug 15 06:25:25 PM PDT 24
Peak memory 202124 kb
Host smart-ec8c8218-7818-4ba3-a4a2-81b3ceb88845
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837425349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2837425349
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3757944535
Short name T535
Test name
Test status
Simulation time 92338971054 ps
CPU time 444.71 seconds
Started Aug 15 06:22:00 PM PDT 24
Finished Aug 15 06:29:25 PM PDT 24
Peak memory 202448 kb
Host smart-33dfdd79-6089-468a-b64d-20cc48a4d060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757944535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3757944535
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2987514847
Short name T587
Test name
Test status
Simulation time 22283882875 ps
CPU time 49.05 seconds
Started Aug 15 06:22:00 PM PDT 24
Finished Aug 15 06:22:49 PM PDT 24
Peak memory 201920 kb
Host smart-c4fe6b88-8c3d-4064-92f1-46faaec81c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987514847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2987514847
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3105002210
Short name T517
Test name
Test status
Simulation time 4444739479 ps
CPU time 3.51 seconds
Started Aug 15 06:22:01 PM PDT 24
Finished Aug 15 06:22:04 PM PDT 24
Peak memory 201968 kb
Host smart-92521074-e6c5-4fab-a010-db4c575f1079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105002210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3105002210
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2738182302
Short name T503
Test name
Test status
Simulation time 5715221463 ps
CPU time 12.99 seconds
Started Aug 15 06:21:52 PM PDT 24
Finished Aug 15 06:22:05 PM PDT 24
Peak memory 201976 kb
Host smart-7254a4b3-f34b-4a64-90db-200bb1e762d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738182302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2738182302
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2617445321
Short name T138
Test name
Test status
Simulation time 487626799582 ps
CPU time 990.15 seconds
Started Aug 15 06:22:00 PM PDT 24
Finished Aug 15 06:38:31 PM PDT 24
Peak memory 202092 kb
Host smart-87932ef3-48cd-4f66-b8a9-a7b4edebb7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617445321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2617445321
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2673158769
Short name T16
Test name
Test status
Simulation time 1318407604759 ps
CPU time 63.54 seconds
Started Aug 15 06:21:59 PM PDT 24
Finished Aug 15 06:23:03 PM PDT 24
Peak memory 210740 kb
Host smart-c92e7fc5-45a4-4f4e-bd3d-398d2d378701
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673158769 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2673158769
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3990730142
Short name T59
Test name
Test status
Simulation time 349766315 ps
CPU time 0.75 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:20:04 PM PDT 24
Peak memory 201980 kb
Host smart-59145779-41b8-47ea-b5b8-5e2bff8329da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990730142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3990730142
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.946956867
Short name T279
Test name
Test status
Simulation time 174088160945 ps
CPU time 265.7 seconds
Started Aug 15 06:20:07 PM PDT 24
Finished Aug 15 06:24:33 PM PDT 24
Peak memory 202072 kb
Host smart-3151df89-2d3f-42da-b266-c9adbe8f70c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946956867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.946956867
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2238847692
Short name T176
Test name
Test status
Simulation time 356103887161 ps
CPU time 98.15 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:21:40 PM PDT 24
Peak memory 202128 kb
Host smart-234cefe2-aa37-46fc-8619-c935d32d78eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238847692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2238847692
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2626996294
Short name T268
Test name
Test status
Simulation time 165633764393 ps
CPU time 115.93 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:21:59 PM PDT 24
Peak memory 202136 kb
Host smart-7543f1c5-effe-4762-bd8a-1f86e2423c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626996294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2626996294
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.105496034
Short name T100
Test name
Test status
Simulation time 165651042950 ps
CPU time 96.49 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:21:38 PM PDT 24
Peak memory 202132 kb
Host smart-4d60dc7a-ed35-4c56-b4a3-d057122924eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=105496034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.105496034
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3043501763
Short name T169
Test name
Test status
Simulation time 496848444088 ps
CPU time 278.42 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:24:39 PM PDT 24
Peak memory 202080 kb
Host smart-ceec17da-fb29-4a5c-98d8-f62e33adf087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043501763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3043501763
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3875039107
Short name T468
Test name
Test status
Simulation time 491186908118 ps
CPU time 1095.74 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:38:17 PM PDT 24
Peak memory 202080 kb
Host smart-7939de32-f758-4412-864a-36ef8d4bf7e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875039107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3875039107
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3257853941
Short name T243
Test name
Test status
Simulation time 520112738654 ps
CPU time 629.77 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:30:33 PM PDT 24
Peak memory 202312 kb
Host smart-888f6a82-77b9-4cd7-801b-266b91399ad5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257853941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3257853941
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1795974928
Short name T624
Test name
Test status
Simulation time 208423530292 ps
CPU time 479.96 seconds
Started Aug 15 06:20:05 PM PDT 24
Finished Aug 15 06:28:05 PM PDT 24
Peak memory 202120 kb
Host smart-1d6b861b-486b-4369-ac3c-b60d0ef3afb3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795974928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1795974928
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2762006931
Short name T562
Test name
Test status
Simulation time 91003424058 ps
CPU time 449.01 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:27:31 PM PDT 24
Peak memory 202376 kb
Host smart-5d8839e6-0d17-4024-8eb0-5420534daca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762006931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2762006931
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2517039298
Short name T431
Test name
Test status
Simulation time 34860536753 ps
CPU time 83.67 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:21:27 PM PDT 24
Peak memory 201896 kb
Host smart-dc171167-b77b-4c2a-9add-1b32cd843147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517039298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2517039298
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.75143932
Short name T398
Test name
Test status
Simulation time 5137455551 ps
CPU time 6.39 seconds
Started Aug 15 06:20:07 PM PDT 24
Finished Aug 15 06:20:13 PM PDT 24
Peak memory 201880 kb
Host smart-684c24f8-ca39-4138-b174-69d71c4dee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75143932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.75143932
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3949969119
Short name T54
Test name
Test status
Simulation time 4438976474 ps
CPU time 4.77 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:20:06 PM PDT 24
Peak memory 217452 kb
Host smart-ff1daf91-e995-4003-95ce-d192f2d2ed7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949969119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3949969119
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1083552528
Short name T740
Test name
Test status
Simulation time 5730115428 ps
CPU time 3.96 seconds
Started Aug 15 06:20:06 PM PDT 24
Finished Aug 15 06:20:10 PM PDT 24
Peak memory 201876 kb
Host smart-97babe88-c060-4f19-9754-34e023c21aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083552528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1083552528
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2802337706
Short name T235
Test name
Test status
Simulation time 360203759318 ps
CPU time 72.71 seconds
Started Aug 15 06:19:59 PM PDT 24
Finished Aug 15 06:21:12 PM PDT 24
Peak memory 202140 kb
Host smart-532ac646-3bf6-42f7-8ef5-8bf37263ff0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802337706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2802337706
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.436494471
Short name T575
Test name
Test status
Simulation time 2601013026 ps
CPU time 7.74 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:20:11 PM PDT 24
Peak memory 210692 kb
Host smart-96aa59d4-45f0-40d4-94c8-22e8d75afe9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436494471 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.436494471
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.4191454509
Short name T601
Test name
Test status
Simulation time 311489402 ps
CPU time 0.95 seconds
Started Aug 15 06:22:11 PM PDT 24
Finished Aug 15 06:22:12 PM PDT 24
Peak memory 201960 kb
Host smart-60a5304b-eefe-44d0-9bac-efc4deb7988c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191454509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.4191454509
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3657011279
Short name T565
Test name
Test status
Simulation time 194344756798 ps
CPU time 95.8 seconds
Started Aug 15 06:22:01 PM PDT 24
Finished Aug 15 06:23:37 PM PDT 24
Peak memory 202096 kb
Host smart-9f1233fe-7fa1-4abe-b86c-ed26428ec9f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657011279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3657011279
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4007381613
Short name T84
Test name
Test status
Simulation time 346433267405 ps
CPU time 207.49 seconds
Started Aug 15 06:22:02 PM PDT 24
Finished Aug 15 06:25:29 PM PDT 24
Peak memory 202120 kb
Host smart-384a2d97-19ef-4c5d-8158-73bc7f7a9571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007381613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4007381613
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.4264403109
Short name T225
Test name
Test status
Simulation time 501513435528 ps
CPU time 257.65 seconds
Started Aug 15 06:21:58 PM PDT 24
Finished Aug 15 06:26:16 PM PDT 24
Peak memory 202152 kb
Host smart-094b3b5b-ccf3-48cc-ae61-8e402e6e8722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264403109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.4264403109
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4203700895
Short name T379
Test name
Test status
Simulation time 496351995688 ps
CPU time 1208.66 seconds
Started Aug 15 06:21:59 PM PDT 24
Finished Aug 15 06:42:08 PM PDT 24
Peak memory 202104 kb
Host smart-1d40f9f9-6111-43d0-9e2e-25f5cf6b385c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203700895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.4203700895
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3078204639
Short name T330
Test name
Test status
Simulation time 491382636526 ps
CPU time 131.81 seconds
Started Aug 15 06:22:01 PM PDT 24
Finished Aug 15 06:24:13 PM PDT 24
Peak memory 202168 kb
Host smart-60d65a05-07f9-4d05-81bf-25c08fbcf868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078204639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3078204639
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3963251311
Short name T489
Test name
Test status
Simulation time 329471572847 ps
CPU time 728.66 seconds
Started Aug 15 06:22:00 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 202088 kb
Host smart-9d246c61-880c-4b82-8448-d26192bd1b98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963251311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3963251311
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.613252421
Short name T368
Test name
Test status
Simulation time 202010823801 ps
CPU time 232.17 seconds
Started Aug 15 06:22:04 PM PDT 24
Finished Aug 15 06:25:56 PM PDT 24
Peak memory 202136 kb
Host smart-3b34ae71-94e9-44f4-80f3-6de582f74b45
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613252421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.613252421
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2505885676
Short name T752
Test name
Test status
Simulation time 77975569486 ps
CPU time 247.34 seconds
Started Aug 15 06:22:10 PM PDT 24
Finished Aug 15 06:26:17 PM PDT 24
Peak memory 202356 kb
Host smart-b51cc75e-8ea0-4db3-9233-60ce663b6fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505885676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2505885676
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2234524493
Short name T759
Test name
Test status
Simulation time 39194648199 ps
CPU time 97.14 seconds
Started Aug 15 06:22:09 PM PDT 24
Finished Aug 15 06:23:46 PM PDT 24
Peak memory 201904 kb
Host smart-46387eb7-4294-49c3-8d33-9dd0a0a9ebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234524493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2234524493
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.250411113
Short name T746
Test name
Test status
Simulation time 3166027601 ps
CPU time 4.82 seconds
Started Aug 15 06:21:59 PM PDT 24
Finished Aug 15 06:22:04 PM PDT 24
Peak memory 201956 kb
Host smart-456155c9-b121-4513-acbd-eda82ac2a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250411113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.250411113
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2845258960
Short name T426
Test name
Test status
Simulation time 5831605649 ps
CPU time 3.54 seconds
Started Aug 15 06:22:01 PM PDT 24
Finished Aug 15 06:22:04 PM PDT 24
Peak memory 201948 kb
Host smart-d086a6d9-e8b7-4b1c-b322-de1360fad277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845258960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2845258960
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1612936715
Short name T645
Test name
Test status
Simulation time 203700102171 ps
CPU time 116.69 seconds
Started Aug 15 06:22:11 PM PDT 24
Finished Aug 15 06:24:07 PM PDT 24
Peak memory 202144 kb
Host smart-5f06e77d-1e3e-46e4-9399-a35baec2fb7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612936715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1612936715
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1817182721
Short name T650
Test name
Test status
Simulation time 2814747301 ps
CPU time 12.21 seconds
Started Aug 15 06:22:10 PM PDT 24
Finished Aug 15 06:22:23 PM PDT 24
Peak memory 202256 kb
Host smart-2e7565a3-277c-4bc9-b597-c63d5a4a3986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817182721 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1817182721
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1756114312
Short name T519
Test name
Test status
Simulation time 473908380 ps
CPU time 1.2 seconds
Started Aug 15 06:22:16 PM PDT 24
Finished Aug 15 06:22:17 PM PDT 24
Peak memory 201956 kb
Host smart-1350e80f-9e0d-43b2-a61d-1fe026cd4ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756114312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1756114312
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.4178094325
Short name T338
Test name
Test status
Simulation time 190151577023 ps
CPU time 108.1 seconds
Started Aug 15 06:22:14 PM PDT 24
Finished Aug 15 06:24:02 PM PDT 24
Peak memory 202144 kb
Host smart-48c859ef-cbd8-4de4-ad91-a6ce47936aa8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178094325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.4178094325
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3666613386
Short name T331
Test name
Test status
Simulation time 552162874784 ps
CPU time 1203.3 seconds
Started Aug 15 06:22:15 PM PDT 24
Finished Aug 15 06:42:19 PM PDT 24
Peak memory 202128 kb
Host smart-cbe37e07-43c4-4a1b-8a04-c3cad64a1f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666613386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3666613386
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.564422637
Short name T428
Test name
Test status
Simulation time 328260924568 ps
CPU time 631.11 seconds
Started Aug 15 06:22:11 PM PDT 24
Finished Aug 15 06:32:42 PM PDT 24
Peak memory 202124 kb
Host smart-2abd9970-c523-42ad-b5d1-b2e5415c70e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=564422637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.564422637
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3629249403
Short name T786
Test name
Test status
Simulation time 486858551256 ps
CPU time 271.64 seconds
Started Aug 15 06:22:10 PM PDT 24
Finished Aug 15 06:26:42 PM PDT 24
Peak memory 202088 kb
Host smart-fa7be8bc-d75c-4c79-8da9-2855a30e6c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629249403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3629249403
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1118905922
Short name T612
Test name
Test status
Simulation time 162278932862 ps
CPU time 386.33 seconds
Started Aug 15 06:22:10 PM PDT 24
Finished Aug 15 06:28:37 PM PDT 24
Peak memory 202128 kb
Host smart-00733691-b29c-4515-96f9-bac04141bc27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118905922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1118905922
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4278158034
Short name T255
Test name
Test status
Simulation time 548692062173 ps
CPU time 673.54 seconds
Started Aug 15 06:22:10 PM PDT 24
Finished Aug 15 06:33:24 PM PDT 24
Peak memory 202192 kb
Host smart-14c40297-85cf-41ce-b551-5b390a23d331
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278158034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4278158034
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.4234801564
Short name T386
Test name
Test status
Simulation time 610102014060 ps
CPU time 1375.86 seconds
Started Aug 15 06:22:15 PM PDT 24
Finished Aug 15 06:45:11 PM PDT 24
Peak memory 202144 kb
Host smart-3f3c9c79-f04b-43fa-a0e7-d346fe6213cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234801564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.4234801564
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1497075622
Short name T481
Test name
Test status
Simulation time 74344725943 ps
CPU time 436.69 seconds
Started Aug 15 06:22:15 PM PDT 24
Finished Aug 15 06:29:31 PM PDT 24
Peak memory 202380 kb
Host smart-b9800696-3d97-4db6-ac9c-587d25a55c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497075622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1497075622
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1707799901
Short name T26
Test name
Test status
Simulation time 29055361307 ps
CPU time 14.41 seconds
Started Aug 15 06:22:16 PM PDT 24
Finished Aug 15 06:22:31 PM PDT 24
Peak memory 201928 kb
Host smart-3e30a296-cd33-427b-a386-b8809c7c1c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707799901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1707799901
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.233327081
Short name T185
Test name
Test status
Simulation time 5176128053 ps
CPU time 6.59 seconds
Started Aug 15 06:22:18 PM PDT 24
Finished Aug 15 06:22:25 PM PDT 24
Peak memory 201900 kb
Host smart-ef0c0f2d-1d67-4c02-9ac1-de4c2d54cc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233327081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.233327081
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1702057633
Short name T417
Test name
Test status
Simulation time 5806975476 ps
CPU time 4.07 seconds
Started Aug 15 06:22:11 PM PDT 24
Finished Aug 15 06:22:15 PM PDT 24
Peak memory 201948 kb
Host smart-9f23ec21-0648-47d6-a494-b715addd0be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702057633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1702057633
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.780743700
Short name T14
Test name
Test status
Simulation time 5145057905 ps
CPU time 18.11 seconds
Started Aug 15 06:22:18 PM PDT 24
Finished Aug 15 06:22:36 PM PDT 24
Peak memory 210520 kb
Host smart-7bf8452c-eb4c-4cf4-9814-b1e69b47fbc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780743700 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.780743700
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1708593501
Short name T712
Test name
Test status
Simulation time 375189483 ps
CPU time 0.82 seconds
Started Aug 15 06:22:20 PM PDT 24
Finished Aug 15 06:22:21 PM PDT 24
Peak memory 201944 kb
Host smart-84d49071-9afb-45b7-b02e-bb748de4c25d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708593501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1708593501
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2034006347
Short name T266
Test name
Test status
Simulation time 326339281054 ps
CPU time 712.87 seconds
Started Aug 15 06:22:14 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 202148 kb
Host smart-0bd5e40a-36e9-4612-a1cd-68c2f9b74719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034006347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2034006347
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3516858865
Short name T669
Test name
Test status
Simulation time 483639938837 ps
CPU time 1141.58 seconds
Started Aug 15 06:22:23 PM PDT 24
Finished Aug 15 06:41:24 PM PDT 24
Peak memory 202160 kb
Host smart-36ca0d96-2226-46dd-83e1-8b199a60dc9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516858865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3516858865
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.134917790
Short name T168
Test name
Test status
Simulation time 327196137863 ps
CPU time 188.1 seconds
Started Aug 15 06:22:13 PM PDT 24
Finished Aug 15 06:25:22 PM PDT 24
Peak memory 202152 kb
Host smart-4e48bc62-ef16-4929-ab1f-4feeefd8158e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134917790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.134917790
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2121842068
Short name T478
Test name
Test status
Simulation time 491826756104 ps
CPU time 229.54 seconds
Started Aug 15 06:22:15 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 202036 kb
Host smart-bbb1a798-1724-432a-92b5-1f5ca9700b7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121842068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2121842068
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2186752896
Short name T196
Test name
Test status
Simulation time 188714126762 ps
CPU time 109.06 seconds
Started Aug 15 06:22:22 PM PDT 24
Finished Aug 15 06:24:11 PM PDT 24
Peak memory 202132 kb
Host smart-82f30f76-9a7a-4835-ae9d-acbc6a6a228d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186752896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2186752896
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2430274348
Short name T693
Test name
Test status
Simulation time 601727354335 ps
CPU time 363.79 seconds
Started Aug 15 06:22:24 PM PDT 24
Finished Aug 15 06:28:28 PM PDT 24
Peak memory 202116 kb
Host smart-8a38fdb2-7c3b-4b01-81ed-7bcee5e8a160
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430274348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2430274348
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.383521818
Short name T609
Test name
Test status
Simulation time 30587195965 ps
CPU time 35.7 seconds
Started Aug 15 06:22:22 PM PDT 24
Finished Aug 15 06:22:58 PM PDT 24
Peak memory 201940 kb
Host smart-d348fc23-6f90-41c6-a5ee-c0effee25d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383521818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.383521818
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3150112850
Short name T460
Test name
Test status
Simulation time 5163654227 ps
CPU time 2.37 seconds
Started Aug 15 06:22:21 PM PDT 24
Finished Aug 15 06:22:24 PM PDT 24
Peak memory 201812 kb
Host smart-368222d8-5f5a-4e2c-ae4d-e70d0eedf1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150112850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3150112850
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1374379529
Short name T408
Test name
Test status
Simulation time 5834272224 ps
CPU time 13.82 seconds
Started Aug 15 06:22:14 PM PDT 24
Finished Aug 15 06:22:28 PM PDT 24
Peak memory 201900 kb
Host smart-be60c1cd-03cd-4055-be16-9520603aba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374379529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1374379529
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3127287702
Short name T227
Test name
Test status
Simulation time 189760448305 ps
CPU time 121.36 seconds
Started Aug 15 06:22:22 PM PDT 24
Finished Aug 15 06:24:23 PM PDT 24
Peak memory 202088 kb
Host smart-dfa6c59c-2678-4d94-927e-86835269fe15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127287702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3127287702
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4030442953
Short name T653
Test name
Test status
Simulation time 35091861607 ps
CPU time 24.71 seconds
Started Aug 15 06:22:24 PM PDT 24
Finished Aug 15 06:22:49 PM PDT 24
Peak memory 210496 kb
Host smart-67d0fc2f-c687-49ff-bec1-6fe86ca87be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030442953 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4030442953
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2855856814
Short name T498
Test name
Test status
Simulation time 388576630 ps
CPU time 0.83 seconds
Started Aug 15 06:22:29 PM PDT 24
Finished Aug 15 06:22:30 PM PDT 24
Peak memory 201968 kb
Host smart-82b3c909-30c4-4db7-84d8-4cf3579ea23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855856814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2855856814
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4167143835
Short name T774
Test name
Test status
Simulation time 325263969268 ps
CPU time 106.71 seconds
Started Aug 15 06:22:31 PM PDT 24
Finished Aug 15 06:24:18 PM PDT 24
Peak memory 202172 kb
Host smart-f11ce824-82b0-4a95-828a-1f3d4f33ee02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167143835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4167143835
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.983557580
Short name T294
Test name
Test status
Simulation time 160238613442 ps
CPU time 89.63 seconds
Started Aug 15 06:22:29 PM PDT 24
Finished Aug 15 06:23:59 PM PDT 24
Peak memory 202120 kb
Host smart-be6cb1f7-02e3-46fe-871d-ea546e81ba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983557580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.983557580
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3533481911
Short name T605
Test name
Test status
Simulation time 169108435480 ps
CPU time 394.77 seconds
Started Aug 15 06:22:30 PM PDT 24
Finished Aug 15 06:29:04 PM PDT 24
Peak memory 202148 kb
Host smart-cb8ef173-2e7f-490a-8b24-65a9ead908e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533481911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3533481911
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4214388132
Short name T577
Test name
Test status
Simulation time 332260534470 ps
CPU time 68.03 seconds
Started Aug 15 06:22:32 PM PDT 24
Finished Aug 15 06:23:40 PM PDT 24
Peak memory 202096 kb
Host smart-d9f68177-e794-4d6b-af33-22ff6e398241
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214388132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.4214388132
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1806208507
Short name T621
Test name
Test status
Simulation time 326040818680 ps
CPU time 63.96 seconds
Started Aug 15 06:22:30 PM PDT 24
Finished Aug 15 06:23:34 PM PDT 24
Peak memory 202136 kb
Host smart-79b0827d-df63-4dd9-a141-57edc548572f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806208507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1806208507
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3701632973
Short name T781
Test name
Test status
Simulation time 332322073355 ps
CPU time 764.21 seconds
Started Aug 15 06:22:30 PM PDT 24
Finished Aug 15 06:35:15 PM PDT 24
Peak memory 202108 kb
Host smart-1441dfb5-b8d3-4224-8db6-c66327fd9d76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701632973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3701632973
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3028734105
Short name T336
Test name
Test status
Simulation time 524130174463 ps
CPU time 302.27 seconds
Started Aug 15 06:22:34 PM PDT 24
Finished Aug 15 06:27:36 PM PDT 24
Peak memory 202204 kb
Host smart-b2553cb2-3e83-4264-82f7-1b70f917b74f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028734105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3028734105
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2474918591
Short name T727
Test name
Test status
Simulation time 396889180613 ps
CPU time 975.6 seconds
Started Aug 15 06:22:28 PM PDT 24
Finished Aug 15 06:38:44 PM PDT 24
Peak memory 202116 kb
Host smart-4268dabe-de01-4961-9111-d52cd49b83cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474918591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2474918591
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3083324289
Short name T67
Test name
Test status
Simulation time 126221128449 ps
CPU time 459.72 seconds
Started Aug 15 06:22:32 PM PDT 24
Finished Aug 15 06:30:12 PM PDT 24
Peak memory 202376 kb
Host smart-73c840da-208c-49f6-8331-2843c4a29586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083324289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3083324289
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.294509600
Short name T95
Test name
Test status
Simulation time 22628329636 ps
CPU time 13.76 seconds
Started Aug 15 06:22:30 PM PDT 24
Finished Aug 15 06:22:44 PM PDT 24
Peak memory 201924 kb
Host smart-a1c8d033-bd0d-45d4-b8fc-ca0df1715f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294509600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.294509600
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1862961120
Short name T502
Test name
Test status
Simulation time 3923674323 ps
CPU time 4.88 seconds
Started Aug 15 06:22:32 PM PDT 24
Finished Aug 15 06:22:37 PM PDT 24
Peak memory 201956 kb
Host smart-5c2c139d-9e12-4ffa-a092-4118d6152c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862961120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1862961120
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1754764454
Short name T459
Test name
Test status
Simulation time 5504708783 ps
CPU time 2.59 seconds
Started Aug 15 06:22:21 PM PDT 24
Finished Aug 15 06:22:24 PM PDT 24
Peak memory 201932 kb
Host smart-1956e164-d970-411d-b6a3-c9730aff05c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754764454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1754764454
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3577569342
Short name T360
Test name
Test status
Simulation time 287733032 ps
CPU time 1.12 seconds
Started Aug 15 06:22:37 PM PDT 24
Finished Aug 15 06:22:39 PM PDT 24
Peak memory 201956 kb
Host smart-2abdeb8a-c246-48ed-a296-38e2a780ce50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577569342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3577569342
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1953912306
Short name T680
Test name
Test status
Simulation time 161630067383 ps
CPU time 103.04 seconds
Started Aug 15 06:22:37 PM PDT 24
Finished Aug 15 06:24:21 PM PDT 24
Peak memory 202100 kb
Host smart-7a328ef6-59ac-43c6-adff-2a74a482e3b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953912306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1953912306
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.220989247
Short name T310
Test name
Test status
Simulation time 342718239287 ps
CPU time 824.41 seconds
Started Aug 15 06:22:37 PM PDT 24
Finished Aug 15 06:36:22 PM PDT 24
Peak memory 202148 kb
Host smart-26a9431f-1ec2-4b2f-92cd-38a5101741ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220989247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.220989247
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.4192915655
Short name T237
Test name
Test status
Simulation time 165181258126 ps
CPU time 100.36 seconds
Started Aug 15 06:22:30 PM PDT 24
Finished Aug 15 06:24:11 PM PDT 24
Peak memory 202080 kb
Host smart-2ba23131-582e-4b85-bd18-871361aea7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192915655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.4192915655
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2271573056
Short name T172
Test name
Test status
Simulation time 491212012702 ps
CPU time 319.24 seconds
Started Aug 15 06:22:32 PM PDT 24
Finished Aug 15 06:27:51 PM PDT 24
Peak memory 202088 kb
Host smart-c977d801-93d6-4ce8-bd32-690fa6154cd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271573056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2271573056
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.814965866
Short name T164
Test name
Test status
Simulation time 160920039545 ps
CPU time 358.27 seconds
Started Aug 15 06:22:35 PM PDT 24
Finished Aug 15 06:28:33 PM PDT 24
Peak memory 202112 kb
Host smart-49070b10-352c-4e86-bee5-e62757457665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814965866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.814965866
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2588093762
Short name T638
Test name
Test status
Simulation time 495350799630 ps
CPU time 1167.43 seconds
Started Aug 15 06:22:32 PM PDT 24
Finished Aug 15 06:42:00 PM PDT 24
Peak memory 202072 kb
Host smart-15027d83-9e69-4af0-9637-57627e1d8f71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588093762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2588093762
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.664091178
Short name T779
Test name
Test status
Simulation time 527487466882 ps
CPU time 1193.18 seconds
Started Aug 15 06:22:32 PM PDT 24
Finished Aug 15 06:42:26 PM PDT 24
Peak memory 202052 kb
Host smart-42006d02-4f3b-472b-aa6a-36b85bdc92e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664091178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.664091178
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1642650613
Short name T246
Test name
Test status
Simulation time 598767959954 ps
CPU time 379.51 seconds
Started Aug 15 06:22:39 PM PDT 24
Finished Aug 15 06:28:59 PM PDT 24
Peak memory 202112 kb
Host smart-3d92f660-3be3-46dd-9620-6df62feb02ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642650613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1642650613
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1159442405
Short name T702
Test name
Test status
Simulation time 97759582080 ps
CPU time 499.78 seconds
Started Aug 15 06:22:38 PM PDT 24
Finished Aug 15 06:30:58 PM PDT 24
Peak memory 202344 kb
Host smart-d68eadf9-93c8-4b4b-a21b-af3af6d95168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159442405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1159442405
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2699479407
Short name T656
Test name
Test status
Simulation time 23176387207 ps
CPU time 7.29 seconds
Started Aug 15 06:22:38 PM PDT 24
Finished Aug 15 06:22:45 PM PDT 24
Peak memory 201968 kb
Host smart-06c4531c-8fae-4ceb-aa44-40b99a361dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699479407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2699479407
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1853655654
Short name T688
Test name
Test status
Simulation time 4462338988 ps
CPU time 6.13 seconds
Started Aug 15 06:22:38 PM PDT 24
Finished Aug 15 06:22:44 PM PDT 24
Peak memory 201960 kb
Host smart-97a19831-5c4e-4b04-8b2a-1be85036a094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853655654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1853655654
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2321665362
Short name T604
Test name
Test status
Simulation time 5773597731 ps
CPU time 3.64 seconds
Started Aug 15 06:22:35 PM PDT 24
Finished Aug 15 06:22:39 PM PDT 24
Peak memory 201936 kb
Host smart-53bf5860-3736-403c-b3ab-7a9b8d350731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321665362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2321665362
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2795802043
Short name T420
Test name
Test status
Simulation time 34296659727 ps
CPU time 20.88 seconds
Started Aug 15 06:22:38 PM PDT 24
Finished Aug 15 06:22:59 PM PDT 24
Peak memory 202000 kb
Host smart-9a2ffcf2-b4ed-4299-9af4-810a64c464ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795802043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2795802043
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1756549090
Short name T482
Test name
Test status
Simulation time 12428783599 ps
CPU time 10.98 seconds
Started Aug 15 06:22:37 PM PDT 24
Finished Aug 15 06:22:49 PM PDT 24
Peak memory 210504 kb
Host smart-799a1444-feac-478a-bae8-ccd3e01fbe8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756549090 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1756549090
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1704309103
Short name T374
Test name
Test status
Simulation time 483377450 ps
CPU time 1.24 seconds
Started Aug 15 06:22:46 PM PDT 24
Finished Aug 15 06:22:48 PM PDT 24
Peak memory 201964 kb
Host smart-6bda8057-29f3-4af5-ad64-35fae49fdadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704309103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1704309103
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.952719059
Short name T74
Test name
Test status
Simulation time 165449635598 ps
CPU time 339.94 seconds
Started Aug 15 06:22:44 PM PDT 24
Finished Aug 15 06:28:24 PM PDT 24
Peak memory 202132 kb
Host smart-fd68d65e-dbcd-4f05-85d2-28ae3ba06b73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952719059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.952719059
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.429754232
Short name T657
Test name
Test status
Simulation time 181128564161 ps
CPU time 108.81 seconds
Started Aug 15 06:22:52 PM PDT 24
Finished Aug 15 06:24:41 PM PDT 24
Peak memory 202128 kb
Host smart-597d6b11-b569-4c51-855f-dab1299552f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429754232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.429754232
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1891566845
Short name T221
Test name
Test status
Simulation time 491648196124 ps
CPU time 278.95 seconds
Started Aug 15 06:22:40 PM PDT 24
Finished Aug 15 06:27:19 PM PDT 24
Peak memory 202060 kb
Host smart-cad0e9b3-22ea-49ae-b844-556485f9ee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891566845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1891566845
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3998137628
Short name T366
Test name
Test status
Simulation time 162917074569 ps
CPU time 68.55 seconds
Started Aug 15 06:22:39 PM PDT 24
Finished Aug 15 06:23:48 PM PDT 24
Peak memory 202124 kb
Host smart-30e0ce13-a9c4-4708-ba94-35bcd280f34c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998137628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3998137628
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.959745906
Short name T258
Test name
Test status
Simulation time 493046450230 ps
CPU time 550.02 seconds
Started Aug 15 06:22:38 PM PDT 24
Finished Aug 15 06:31:48 PM PDT 24
Peak memory 202132 kb
Host smart-50079653-3e16-4c27-ac6b-8e604295a769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959745906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.959745906
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.811218876
Short name T682
Test name
Test status
Simulation time 166467906012 ps
CPU time 95.04 seconds
Started Aug 15 06:22:38 PM PDT 24
Finished Aug 15 06:24:13 PM PDT 24
Peak memory 202068 kb
Host smart-07df7962-e7df-4057-9d5a-76f2a07eb48d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=811218876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.811218876
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2600260073
Short name T295
Test name
Test status
Simulation time 338150687163 ps
CPU time 743.81 seconds
Started Aug 15 06:22:46 PM PDT 24
Finished Aug 15 06:35:10 PM PDT 24
Peak memory 202128 kb
Host smart-f9febedf-4f55-466a-b9d1-95f1954888f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600260073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2600260073
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.12317824
Short name T526
Test name
Test status
Simulation time 197168015066 ps
CPU time 116.84 seconds
Started Aug 15 06:22:50 PM PDT 24
Finished Aug 15 06:24:47 PM PDT 24
Peak memory 202124 kb
Host smart-fcc8fffe-d0a4-4d48-b4cd-7a2a4add26f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12317824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.a
dc_ctrl_filters_wakeup_fixed.12317824
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.415667203
Short name T351
Test name
Test status
Simulation time 70361283962 ps
CPU time 298.28 seconds
Started Aug 15 06:22:49 PM PDT 24
Finished Aug 15 06:27:47 PM PDT 24
Peak memory 202368 kb
Host smart-46d8b0aa-31d5-4d13-b750-a752e4b46ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415667203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.415667203
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.79374306
Short name T88
Test name
Test status
Simulation time 34668092994 ps
CPU time 18.77 seconds
Started Aug 15 06:22:48 PM PDT 24
Finished Aug 15 06:23:07 PM PDT 24
Peak memory 201948 kb
Host smart-0b386761-50d9-4465-a493-fef06d3ca8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79374306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.79374306
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2730013637
Short name T576
Test name
Test status
Simulation time 5585240368 ps
CPU time 1.71 seconds
Started Aug 15 06:22:46 PM PDT 24
Finished Aug 15 06:22:48 PM PDT 24
Peak memory 201948 kb
Host smart-dc70b40f-2574-41ac-932c-4cd59ffa0936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730013637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2730013637
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.527543756
Short name T445
Test name
Test status
Simulation time 5883822853 ps
CPU time 14.76 seconds
Started Aug 15 06:22:39 PM PDT 24
Finished Aug 15 06:22:53 PM PDT 24
Peak memory 202140 kb
Host smart-97330f26-6de9-4c26-9b5c-a238bd928de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527543756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.527543756
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1687929096
Short name T209
Test name
Test status
Simulation time 469545563749 ps
CPU time 634.04 seconds
Started Aug 15 06:22:45 PM PDT 24
Finished Aug 15 06:33:19 PM PDT 24
Peak memory 210576 kb
Host smart-89659790-5a0f-4f83-9522-d8fddf6aba22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687929096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1687929096
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.156769828
Short name T438
Test name
Test status
Simulation time 2666498866 ps
CPU time 5.44 seconds
Started Aug 15 06:22:45 PM PDT 24
Finished Aug 15 06:22:51 PM PDT 24
Peak memory 202112 kb
Host smart-02fb8c87-3e31-4e08-bf91-17a517e3e4a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156769828 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.156769828
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4078420177
Short name T659
Test name
Test status
Simulation time 502559273 ps
CPU time 0.82 seconds
Started Aug 15 06:22:52 PM PDT 24
Finished Aug 15 06:22:53 PM PDT 24
Peak memory 201956 kb
Host smart-54dc4769-45e7-49a6-a1d8-64e6841cebce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078420177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4078420177
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3942238360
Short name T616
Test name
Test status
Simulation time 176961914678 ps
CPU time 176.36 seconds
Started Aug 15 06:22:52 PM PDT 24
Finished Aug 15 06:25:49 PM PDT 24
Peak memory 202124 kb
Host smart-4f1570d7-fbe2-4fa2-adba-facc2f79dc19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942238360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3942238360
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.4284917302
Short name T252
Test name
Test status
Simulation time 333866797118 ps
CPU time 820.19 seconds
Started Aug 15 06:22:53 PM PDT 24
Finished Aug 15 06:36:33 PM PDT 24
Peak memory 202132 kb
Host smart-67663454-16f0-44eb-b890-deae6f521854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284917302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4284917302
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.692787128
Short name T586
Test name
Test status
Simulation time 341396974550 ps
CPU time 733.09 seconds
Started Aug 15 06:22:45 PM PDT 24
Finished Aug 15 06:34:58 PM PDT 24
Peak memory 202132 kb
Host smart-f8b2804e-2c6b-41d2-b7df-506428f73a2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=692787128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.692787128
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3943088622
Short name T687
Test name
Test status
Simulation time 339515209824 ps
CPU time 749.11 seconds
Started Aug 15 06:22:50 PM PDT 24
Finished Aug 15 06:35:19 PM PDT 24
Peak memory 202128 kb
Host smart-1f37905a-7ab6-4a58-92da-640b1b1a0289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943088622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3943088622
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3734378409
Short name T675
Test name
Test status
Simulation time 482774717506 ps
CPU time 1047.22 seconds
Started Aug 15 06:22:45 PM PDT 24
Finished Aug 15 06:40:12 PM PDT 24
Peak memory 202124 kb
Host smart-0ecd1a19-9894-4b3e-8c11-fc58f135e6e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734378409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3734378409
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3600009022
Short name T35
Test name
Test status
Simulation time 502020807613 ps
CPU time 145.7 seconds
Started Aug 15 06:22:48 PM PDT 24
Finished Aug 15 06:25:13 PM PDT 24
Peak memory 202204 kb
Host smart-b95110e9-cf0d-41bc-922a-3f3532776367
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600009022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3600009022
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1912498683
Short name T442
Test name
Test status
Simulation time 206105959124 ps
CPU time 70.27 seconds
Started Aug 15 06:22:54 PM PDT 24
Finished Aug 15 06:24:04 PM PDT 24
Peak memory 202120 kb
Host smart-6ed0c054-eac3-4d95-aee8-fed0aae26139
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912498683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1912498683
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.330082987
Short name T451
Test name
Test status
Simulation time 43647164970 ps
CPU time 97.01 seconds
Started Aug 15 06:22:54 PM PDT 24
Finished Aug 15 06:24:31 PM PDT 24
Peak memory 201984 kb
Host smart-76916d5f-4a5d-42a6-85a3-f36a1131df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330082987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.330082987
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1518836384
Short name T709
Test name
Test status
Simulation time 4696893808 ps
CPU time 6.28 seconds
Started Aug 15 06:22:52 PM PDT 24
Finished Aug 15 06:22:59 PM PDT 24
Peak memory 201952 kb
Host smart-2143f62a-90ad-4627-abec-04e2f57b24d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518836384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1518836384
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2076709533
Short name T499
Test name
Test status
Simulation time 6023688443 ps
CPU time 7.75 seconds
Started Aug 15 06:22:47 PM PDT 24
Finished Aug 15 06:22:55 PM PDT 24
Peak memory 201972 kb
Host smart-ce0fbc36-3a4e-4e09-8788-b4cb6e517d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076709533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2076709533
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3168508498
Short name T286
Test name
Test status
Simulation time 531312972526 ps
CPU time 136.94 seconds
Started Aug 15 06:22:52 PM PDT 24
Finished Aug 15 06:25:10 PM PDT 24
Peak memory 202108 kb
Host smart-04822256-0621-4bd2-8a32-664f3a93c2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168508498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3168508498
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2330129075
Short name T20
Test name
Test status
Simulation time 3224645802 ps
CPU time 10.16 seconds
Started Aug 15 06:22:53 PM PDT 24
Finished Aug 15 06:23:03 PM PDT 24
Peak memory 210520 kb
Host smart-522f9350-beab-4777-9917-3e0a5d935e5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330129075 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2330129075
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2755926662
Short name T479
Test name
Test status
Simulation time 441329901 ps
CPU time 1.14 seconds
Started Aug 15 06:22:59 PM PDT 24
Finished Aug 15 06:23:00 PM PDT 24
Peak memory 201928 kb
Host smart-5f6e9f52-e4d4-4356-96b8-20d3acf38417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755926662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2755926662
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2239581000
Short name T124
Test name
Test status
Simulation time 531595302143 ps
CPU time 187.84 seconds
Started Aug 15 06:22:59 PM PDT 24
Finished Aug 15 06:26:07 PM PDT 24
Peak memory 202092 kb
Host smart-e8a13fb3-c4bf-496d-9024-bba517440ac5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239581000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2239581000
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2283349989
Short name T222
Test name
Test status
Simulation time 343739778200 ps
CPU time 71.76 seconds
Started Aug 15 06:23:00 PM PDT 24
Finished Aug 15 06:24:12 PM PDT 24
Peak memory 202132 kb
Host smart-b71626ff-ea4f-4cc1-a98b-9d26f64155af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283349989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2283349989
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2916971525
Short name T516
Test name
Test status
Simulation time 482653827195 ps
CPU time 1148.37 seconds
Started Aug 15 06:22:58 PM PDT 24
Finished Aug 15 06:42:06 PM PDT 24
Peak memory 202132 kb
Host smart-41ef59c8-cff4-476e-8151-90ce67ced0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916971525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2916971525
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.109434376
Short name T722
Test name
Test status
Simulation time 491727191478 ps
CPU time 643.96 seconds
Started Aug 15 06:23:02 PM PDT 24
Finished Aug 15 06:33:46 PM PDT 24
Peak memory 202104 kb
Host smart-ffbba192-8311-4901-b3fe-7be5f1589f8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=109434376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.109434376
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2695227775
Short name T765
Test name
Test status
Simulation time 500023537077 ps
CPU time 255.3 seconds
Started Aug 15 06:22:54 PM PDT 24
Finished Aug 15 06:27:09 PM PDT 24
Peak memory 202128 kb
Host smart-7365072e-0071-4bad-aa1f-2285c12d86a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695227775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2695227775
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2020033544
Short name T694
Test name
Test status
Simulation time 329773049544 ps
CPU time 697 seconds
Started Aug 15 06:22:59 PM PDT 24
Finished Aug 15 06:34:36 PM PDT 24
Peak memory 202160 kb
Host smart-beee1ba5-ee89-44c5-9685-a0177d598e1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020033544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2020033544
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2527123475
Short name T241
Test name
Test status
Simulation time 544504619747 ps
CPU time 294.66 seconds
Started Aug 15 06:23:01 PM PDT 24
Finished Aug 15 06:27:55 PM PDT 24
Peak memory 202116 kb
Host smart-f5954abe-616c-454d-b186-a4d5648f508e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527123475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2527123475
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.333198898
Short name T87
Test name
Test status
Simulation time 597335633471 ps
CPU time 101.71 seconds
Started Aug 15 06:23:00 PM PDT 24
Finished Aug 15 06:24:42 PM PDT 24
Peak memory 202128 kb
Host smart-67d225fd-873c-4d5e-898c-544a46aca3a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333198898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.333198898
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2285698148
Short name T641
Test name
Test status
Simulation time 81135808774 ps
CPU time 255.51 seconds
Started Aug 15 06:22:59 PM PDT 24
Finished Aug 15 06:27:15 PM PDT 24
Peak memory 202380 kb
Host smart-2ea2f6fa-f10a-4539-adee-655c9654f473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285698148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2285698148
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2309049065
Short name T441
Test name
Test status
Simulation time 30873207530 ps
CPU time 19.87 seconds
Started Aug 15 06:23:00 PM PDT 24
Finished Aug 15 06:23:20 PM PDT 24
Peak memory 201984 kb
Host smart-ac12abfc-4f0e-497b-8a5f-84b7ea6c4488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309049065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2309049065
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2877477576
Short name T767
Test name
Test status
Simulation time 3976664586 ps
CPU time 10.28 seconds
Started Aug 15 06:22:58 PM PDT 24
Finished Aug 15 06:23:08 PM PDT 24
Peak memory 201812 kb
Host smart-23cf89ac-f9eb-4df1-8ca3-21496a6e3a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877477576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2877477576
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1917672544
Short name T715
Test name
Test status
Simulation time 6011300091 ps
CPU time 3.77 seconds
Started Aug 15 06:22:51 PM PDT 24
Finished Aug 15 06:22:55 PM PDT 24
Peak memory 201952 kb
Host smart-39a4f2da-9c8d-4494-a3df-c6547046cb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917672544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1917672544
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.652744975
Short name T208
Test name
Test status
Simulation time 334597396278 ps
CPU time 715.81 seconds
Started Aug 15 06:23:02 PM PDT 24
Finished Aug 15 06:34:58 PM PDT 24
Peak memory 202356 kb
Host smart-0ca426c2-ab7a-484b-ab9f-dc529c07f7f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652744975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
652744975
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.698216079
Short name T76
Test name
Test status
Simulation time 19669536825 ps
CPU time 25.03 seconds
Started Aug 15 06:23:01 PM PDT 24
Finished Aug 15 06:23:26 PM PDT 24
Peak memory 210664 kb
Host smart-f4831e3b-af78-4375-a32c-19ffbcd9fc27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698216079 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.698216079
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1789297559
Short name T407
Test name
Test status
Simulation time 328733340 ps
CPU time 1 seconds
Started Aug 15 06:23:18 PM PDT 24
Finished Aug 15 06:23:19 PM PDT 24
Peak memory 201964 kb
Host smart-30118a02-d545-4067-9cc7-b82ae7178d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789297559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1789297559
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2721944177
Short name T637
Test name
Test status
Simulation time 166914399580 ps
CPU time 28.58 seconds
Started Aug 15 06:23:08 PM PDT 24
Finished Aug 15 06:23:38 PM PDT 24
Peak memory 202144 kb
Host smart-86900134-830a-4e1f-8efd-dab0934c9736
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721944177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2721944177
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.145397007
Short name T293
Test name
Test status
Simulation time 356637168386 ps
CPU time 892.33 seconds
Started Aug 15 06:23:08 PM PDT 24
Finished Aug 15 06:38:01 PM PDT 24
Peak memory 202176 kb
Host smart-7c509bac-bc0d-4841-94fc-db720c3bff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145397007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.145397007
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.988177936
Short name T253
Test name
Test status
Simulation time 164552796642 ps
CPU time 160.34 seconds
Started Aug 15 06:23:07 PM PDT 24
Finished Aug 15 06:25:47 PM PDT 24
Peak memory 202140 kb
Host smart-c8ccc72e-3c12-41c0-b561-65ee71123caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988177936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.988177936
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3915186558
Short name T380
Test name
Test status
Simulation time 320336324563 ps
CPU time 688.26 seconds
Started Aug 15 06:23:08 PM PDT 24
Finished Aug 15 06:34:37 PM PDT 24
Peak memory 202152 kb
Host smart-bb58a33e-fd49-4230-9264-0eaa796bef02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915186558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3915186558
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.385582580
Short name T229
Test name
Test status
Simulation time 162734688168 ps
CPU time 182.68 seconds
Started Aug 15 06:23:02 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 202076 kb
Host smart-feed1a5d-80f2-482d-b3a7-0c989fb1b253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385582580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.385582580
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1662754635
Short name T639
Test name
Test status
Simulation time 324557466057 ps
CPU time 699.91 seconds
Started Aug 15 06:23:08 PM PDT 24
Finished Aug 15 06:34:48 PM PDT 24
Peak memory 202124 kb
Host smart-89c9f1e7-c677-4709-b8c6-539b2863247c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662754635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1662754635
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1558290146
Short name T284
Test name
Test status
Simulation time 393589260000 ps
CPU time 193.11 seconds
Started Aug 15 06:23:09 PM PDT 24
Finished Aug 15 06:26:22 PM PDT 24
Peak memory 202124 kb
Host smart-b1d5fc39-c946-4809-bc5e-355f800e5319
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558290146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1558290146
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3678393745
Short name T506
Test name
Test status
Simulation time 616496538450 ps
CPU time 1278.16 seconds
Started Aug 15 06:23:09 PM PDT 24
Finished Aug 15 06:44:28 PM PDT 24
Peak memory 202144 kb
Host smart-a9393263-4a03-4694-a9d7-ffdd2041733d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678393745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3678393745
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2299005673
Short name T477
Test name
Test status
Simulation time 96609048951 ps
CPU time 347.8 seconds
Started Aug 15 06:23:15 PM PDT 24
Finished Aug 15 06:29:03 PM PDT 24
Peak memory 202368 kb
Host smart-90027716-d52d-4e5b-bca8-49fa6c5de8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299005673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2299005673
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3164566729
Short name T162
Test name
Test status
Simulation time 40110451648 ps
CPU time 22.75 seconds
Started Aug 15 06:23:19 PM PDT 24
Finished Aug 15 06:23:42 PM PDT 24
Peak memory 201964 kb
Host smart-44feb904-f88e-4b7f-bc5f-b1e867191ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164566729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3164566729
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3058832793
Short name T432
Test name
Test status
Simulation time 4600745726 ps
CPU time 10.98 seconds
Started Aug 15 06:23:06 PM PDT 24
Finished Aug 15 06:23:17 PM PDT 24
Peak memory 201972 kb
Host smart-9612bf31-6019-4a80-b19c-958e40bd57a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058832793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3058832793
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3519200139
Short name T528
Test name
Test status
Simulation time 5986514614 ps
CPU time 4.52 seconds
Started Aug 15 06:23:02 PM PDT 24
Finished Aug 15 06:23:06 PM PDT 24
Peak memory 201940 kb
Host smart-2b4e03a3-290c-467d-8780-38cf050a29da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519200139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3519200139
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.155486605
Short name T588
Test name
Test status
Simulation time 8658064333 ps
CPU time 5.86 seconds
Started Aug 15 06:23:14 PM PDT 24
Finished Aug 15 06:23:20 PM PDT 24
Peak memory 202328 kb
Host smart-434a01e8-519c-4d46-b1a0-af4e341b07d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155486605 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.155486605
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.876232261
Short name T474
Test name
Test status
Simulation time 518704646 ps
CPU time 1.85 seconds
Started Aug 15 06:23:24 PM PDT 24
Finished Aug 15 06:23:26 PM PDT 24
Peak memory 201992 kb
Host smart-c3483451-b321-4b93-a7ce-932585f8cf4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876232261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.876232261
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1050111288
Short name T86
Test name
Test status
Simulation time 164909603530 ps
CPU time 362.22 seconds
Started Aug 15 06:23:14 PM PDT 24
Finished Aug 15 06:29:17 PM PDT 24
Peak memory 202080 kb
Host smart-b4b70d4a-1433-498e-96ff-5558521606ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050111288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1050111288
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.177004014
Short name T787
Test name
Test status
Simulation time 163196426303 ps
CPU time 80.15 seconds
Started Aug 15 06:23:13 PM PDT 24
Finished Aug 15 06:24:34 PM PDT 24
Peak memory 202144 kb
Host smart-f206b8f7-72b6-4523-9c64-79dd9565d639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177004014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.177004014
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1270174586
Short name T585
Test name
Test status
Simulation time 489557528336 ps
CPU time 172.17 seconds
Started Aug 15 06:23:14 PM PDT 24
Finished Aug 15 06:26:06 PM PDT 24
Peak memory 202168 kb
Host smart-7b6b70ec-e295-4e26-b519-823f47b4dca1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270174586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1270174586
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.4243740906
Short name T512
Test name
Test status
Simulation time 335850030937 ps
CPU time 205.31 seconds
Started Aug 15 06:23:16 PM PDT 24
Finished Aug 15 06:26:42 PM PDT 24
Peak memory 202312 kb
Host smart-f044fbd9-0b78-4e52-820b-1aca68679b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243740906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.4243740906
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2647777157
Short name T580
Test name
Test status
Simulation time 490006111319 ps
CPU time 196.1 seconds
Started Aug 15 06:23:15 PM PDT 24
Finished Aug 15 06:26:31 PM PDT 24
Peak memory 202120 kb
Host smart-04902009-ea7b-4dd9-afa9-226e4d818ed1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647777157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2647777157
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3132250354
Short name T793
Test name
Test status
Simulation time 374075724597 ps
CPU time 221.1 seconds
Started Aug 15 06:23:14 PM PDT 24
Finished Aug 15 06:26:55 PM PDT 24
Peak memory 202116 kb
Host smart-03601a62-79d3-4062-bb0a-4dada673b62d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132250354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3132250354
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.935358652
Short name T661
Test name
Test status
Simulation time 403130071201 ps
CPU time 238.73 seconds
Started Aug 15 06:23:16 PM PDT 24
Finished Aug 15 06:27:15 PM PDT 24
Peak memory 202128 kb
Host smart-d9ecbf3d-f6ee-459a-b39f-0cda5aa352d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935358652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.935358652
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.811507802
Short name T205
Test name
Test status
Simulation time 108490700559 ps
CPU time 381.49 seconds
Started Aug 15 06:23:23 PM PDT 24
Finished Aug 15 06:29:45 PM PDT 24
Peak memory 202384 kb
Host smart-37cbc528-8f6e-4b65-a4fe-203ba254339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811507802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.811507802
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2552503350
Short name T713
Test name
Test status
Simulation time 25228526384 ps
CPU time 48.05 seconds
Started Aug 15 06:23:23 PM PDT 24
Finished Aug 15 06:24:12 PM PDT 24
Peak memory 201952 kb
Host smart-6f2c7fbb-6da6-4915-9991-327f91c7cb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552503350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2552503350
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3308136989
Short name T566
Test name
Test status
Simulation time 5799746146 ps
CPU time 3.72 seconds
Started Aug 15 06:23:35 PM PDT 24
Finished Aug 15 06:23:39 PM PDT 24
Peak memory 201964 kb
Host smart-2e49dbe2-3b64-4c38-9dec-61784c600fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308136989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3308136989
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1476799645
Short name T383
Test name
Test status
Simulation time 5895379448 ps
CPU time 16.06 seconds
Started Aug 15 06:23:19 PM PDT 24
Finished Aug 15 06:23:35 PM PDT 24
Peak memory 201964 kb
Host smart-91d57748-00a6-4308-8b72-d5a25518de45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476799645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1476799645
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2933033989
Short name T647
Test name
Test status
Simulation time 5711708998 ps
CPU time 6.4 seconds
Started Aug 15 06:23:21 PM PDT 24
Finished Aug 15 06:23:28 PM PDT 24
Peak memory 202256 kb
Host smart-6ab3f585-98cd-4625-9082-c22d528464f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933033989 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2933033989
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2078108717
Short name T403
Test name
Test status
Simulation time 499012650 ps
CPU time 0.8 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:20:02 PM PDT 24
Peak memory 201980 kb
Host smart-865ae83c-fc2b-4484-9166-aec55e5a67ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078108717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2078108717
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1029789377
Short name T750
Test name
Test status
Simulation time 165678055103 ps
CPU time 96.32 seconds
Started Aug 15 06:21:17 PM PDT 24
Finished Aug 15 06:22:53 PM PDT 24
Peak memory 202160 kb
Host smart-2ffdf805-130a-4f30-a87f-81527d1af4fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029789377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1029789377
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.409494093
Short name T10
Test name
Test status
Simulation time 162202311357 ps
CPU time 91.84 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:21:34 PM PDT 24
Peak memory 202108 kb
Host smart-b169ed7b-fea0-4ed9-bbc2-f83a72230b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409494093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.409494093
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1804683674
Short name T574
Test name
Test status
Simulation time 163412680786 ps
CPU time 94.76 seconds
Started Aug 15 06:20:06 PM PDT 24
Finished Aug 15 06:21:41 PM PDT 24
Peak memory 202148 kb
Host smart-00c6e191-d1e6-467b-891d-b309aa5e4bfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804683674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1804683674
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1046809555
Short name T556
Test name
Test status
Simulation time 330952170922 ps
CPU time 692.87 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:31:35 PM PDT 24
Peak memory 202116 kb
Host smart-8aa34a70-32ac-4b31-affc-a0598fd826e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046809555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1046809555
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3056599491
Short name T463
Test name
Test status
Simulation time 337847872972 ps
CPU time 416.46 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:27:00 PM PDT 24
Peak memory 202012 kb
Host smart-512dcbfa-ef15-4d18-87c9-c2d376a2a0b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056599491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3056599491
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.4056082574
Short name T518
Test name
Test status
Simulation time 366827802625 ps
CPU time 138.32 seconds
Started Aug 15 06:20:05 PM PDT 24
Finished Aug 15 06:22:23 PM PDT 24
Peak memory 202064 kb
Host smart-4be67c05-0e56-4da0-ac6e-1e64fbde09a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056082574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.4056082574
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1296679691
Short name T707
Test name
Test status
Simulation time 390401620888 ps
CPU time 806.79 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 202092 kb
Host smart-d39bc349-6137-405a-8ab9-bfcaa460e809
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296679691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1296679691
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1066259523
Short name T603
Test name
Test status
Simulation time 71637929204 ps
CPU time 276.09 seconds
Started Aug 15 06:20:00 PM PDT 24
Finished Aug 15 06:24:36 PM PDT 24
Peak memory 202420 kb
Host smart-6ab7cd8a-1c2f-4e95-8e49-d7e9f3eead1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066259523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1066259523
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.310088644
Short name T524
Test name
Test status
Simulation time 43547585636 ps
CPU time 25.56 seconds
Started Aug 15 06:20:04 PM PDT 24
Finished Aug 15 06:20:30 PM PDT 24
Peak memory 201944 kb
Host smart-d33b0dc7-3dca-46e2-89d2-d619f4b38852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310088644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.310088644
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.674742391
Short name T469
Test name
Test status
Simulation time 4023445999 ps
CPU time 6.16 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:20:08 PM PDT 24
Peak memory 201928 kb
Host smart-60663947-874b-4443-99af-040ff0543ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674742391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.674742391
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1488193626
Short name T53
Test name
Test status
Simulation time 7600726957 ps
CPU time 18.34 seconds
Started Aug 15 06:20:04 PM PDT 24
Finished Aug 15 06:20:23 PM PDT 24
Peak memory 218548 kb
Host smart-1289dafc-e578-456c-bb61-642ea3c789bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488193626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1488193626
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.595292781
Short name T560
Test name
Test status
Simulation time 6131783151 ps
CPU time 15.47 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:20:16 PM PDT 24
Peak memory 202000 kb
Host smart-7848ae32-feff-4d48-b6df-2b6ae78a1870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595292781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.595292781
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.16748696
Short name T538
Test name
Test status
Simulation time 257793880804 ps
CPU time 316.46 seconds
Started Aug 15 06:20:05 PM PDT 24
Finished Aug 15 06:25:21 PM PDT 24
Peak memory 218668 kb
Host smart-da91c49d-d0b7-4f2d-8855-0ff60f0c9d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16748696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.16748696
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2876532083
Short name T251
Test name
Test status
Simulation time 5046890338 ps
CPU time 14.61 seconds
Started Aug 15 06:21:17 PM PDT 24
Finished Aug 15 06:21:31 PM PDT 24
Peak memory 210720 kb
Host smart-9f4767d7-a0c8-4941-9d56-0a61e2f36f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876532083 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2876532083
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.216561731
Short name T373
Test name
Test status
Simulation time 340885429 ps
CPU time 0.82 seconds
Started Aug 15 06:23:31 PM PDT 24
Finished Aug 15 06:23:32 PM PDT 24
Peak memory 201980 kb
Host smart-80adad5a-a1ec-436c-a80e-75b4027ab42e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216561731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.216561731
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.375942973
Short name T732
Test name
Test status
Simulation time 482722462767 ps
CPU time 306.07 seconds
Started Aug 15 06:23:30 PM PDT 24
Finished Aug 15 06:28:37 PM PDT 24
Peak memory 202112 kb
Host smart-eb55af41-86ef-4faf-87e2-3ede9bbdc12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375942973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.375942973
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3235226433
Short name T288
Test name
Test status
Simulation time 167764246476 ps
CPU time 393.86 seconds
Started Aug 15 06:23:24 PM PDT 24
Finished Aug 15 06:29:58 PM PDT 24
Peak memory 202144 kb
Host smart-1433daf9-fd3a-4b73-b724-e390ae55d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235226433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3235226433
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.111411387
Short name T161
Test name
Test status
Simulation time 328555982365 ps
CPU time 185.99 seconds
Started Aug 15 06:23:23 PM PDT 24
Finished Aug 15 06:26:30 PM PDT 24
Peak memory 202188 kb
Host smart-22fe5c9d-3567-41f2-8668-2d4a6d79d9e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=111411387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.111411387
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3830931928
Short name T157
Test name
Test status
Simulation time 329577065273 ps
CPU time 753.45 seconds
Started Aug 15 06:23:23 PM PDT 24
Finished Aug 15 06:35:57 PM PDT 24
Peak memory 202144 kb
Host smart-91e3cf43-c68b-407d-94a8-9b7c30b278ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830931928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3830931928
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2514924200
Short name T25
Test name
Test status
Simulation time 167821407028 ps
CPU time 104.64 seconds
Started Aug 15 06:23:23 PM PDT 24
Finished Aug 15 06:25:07 PM PDT 24
Peak memory 202100 kb
Host smart-a9b7240e-4a66-4374-a014-4e19d27ac6c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514924200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2514924200
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4248069229
Short name T654
Test name
Test status
Simulation time 213573365966 ps
CPU time 491.04 seconds
Started Aug 15 06:23:31 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 202104 kb
Host smart-c5e5f4d2-6356-4c91-b7fc-53de1da40aac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248069229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4248069229
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2634323363
Short name T543
Test name
Test status
Simulation time 111827275508 ps
CPU time 359.31 seconds
Started Aug 15 06:23:31 PM PDT 24
Finished Aug 15 06:29:30 PM PDT 24
Peak memory 202380 kb
Host smart-c0602a49-4c53-4dcf-bc7e-1d21b2970872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634323363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2634323363
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1457705343
Short name T754
Test name
Test status
Simulation time 41393692559 ps
CPU time 25.59 seconds
Started Aug 15 06:23:31 PM PDT 24
Finished Aug 15 06:23:57 PM PDT 24
Peak memory 201972 kb
Host smart-9ef454d0-b906-4d23-b03c-10c15e5c8b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457705343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1457705343
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3106170962
Short name T708
Test name
Test status
Simulation time 3779308251 ps
CPU time 2.78 seconds
Started Aug 15 06:23:37 PM PDT 24
Finished Aug 15 06:23:40 PM PDT 24
Peak memory 201960 kb
Host smart-f2b161fa-66f0-4a0b-934d-2081d83cd582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106170962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3106170962
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3015593871
Short name T618
Test name
Test status
Simulation time 5918279554 ps
CPU time 15.8 seconds
Started Aug 15 06:23:35 PM PDT 24
Finished Aug 15 06:23:51 PM PDT 24
Peak memory 201964 kb
Host smart-d4d2b3ff-e235-4752-9fce-f2f575a6ddf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015593871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3015593871
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.754350610
Short name T132
Test name
Test status
Simulation time 349861514350 ps
CPU time 102.33 seconds
Started Aug 15 06:23:37 PM PDT 24
Finished Aug 15 06:25:19 PM PDT 24
Peak memory 202192 kb
Host smart-46bf48d9-db40-442a-8094-cf8ba05e01ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754350610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
754350610
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2196090149
Short name T473
Test name
Test status
Simulation time 6258985856 ps
CPU time 18.92 seconds
Started Aug 15 06:23:30 PM PDT 24
Finished Aug 15 06:23:49 PM PDT 24
Peak memory 217076 kb
Host smart-a22a5e57-7a00-471b-8a64-c2a9506d2dab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196090149 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2196090149
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2598200857
Short name T592
Test name
Test status
Simulation time 314803275 ps
CPU time 1.04 seconds
Started Aug 15 06:23:36 PM PDT 24
Finished Aug 15 06:23:38 PM PDT 24
Peak memory 201968 kb
Host smart-c962b3e3-990a-4edf-95ba-93a54bc43c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598200857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2598200857
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1381297272
Short name T228
Test name
Test status
Simulation time 495897268398 ps
CPU time 1132.39 seconds
Started Aug 15 06:23:37 PM PDT 24
Finished Aug 15 06:42:30 PM PDT 24
Peak memory 202180 kb
Host smart-db4fee5e-a62f-4a4d-831e-c5c9ecf9cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381297272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1381297272
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1904103333
Short name T260
Test name
Test status
Simulation time 162076364123 ps
CPU time 342.45 seconds
Started Aug 15 06:23:32 PM PDT 24
Finished Aug 15 06:29:14 PM PDT 24
Peak memory 202168 kb
Host smart-0fdfe3c2-c176-4d37-b0b8-6465cb19efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904103333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1904103333
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4046099221
Short name T723
Test name
Test status
Simulation time 323678635465 ps
CPU time 202.42 seconds
Started Aug 15 06:23:31 PM PDT 24
Finished Aug 15 06:26:54 PM PDT 24
Peak memory 202368 kb
Host smart-d377717f-22b2-46b5-8f53-4847a5fe3f43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046099221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.4046099221
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.4085213855
Short name T215
Test name
Test status
Simulation time 325123463784 ps
CPU time 177.66 seconds
Started Aug 15 06:23:30 PM PDT 24
Finished Aug 15 06:26:27 PM PDT 24
Peak memory 202124 kb
Host smart-3e6859fb-eee9-42cb-959b-a2733c0c8d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085213855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.4085213855
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.242689322
Short name T559
Test name
Test status
Simulation time 482957673060 ps
CPU time 186.09 seconds
Started Aug 15 06:23:28 PM PDT 24
Finished Aug 15 06:26:35 PM PDT 24
Peak memory 202112 kb
Host smart-0dbc4def-339b-4711-8252-0f42e7167ffc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=242689322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.242689322
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1156691908
Short name T238
Test name
Test status
Simulation time 170067206551 ps
CPU time 97.32 seconds
Started Aug 15 06:23:31 PM PDT 24
Finished Aug 15 06:25:09 PM PDT 24
Peak memory 202100 kb
Host smart-a0298274-553e-4252-b7a9-f15abf1dbbc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156691908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1156691908
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3193487584
Short name T569
Test name
Test status
Simulation time 585169434306 ps
CPU time 329.8 seconds
Started Aug 15 06:23:29 PM PDT 24
Finished Aug 15 06:28:59 PM PDT 24
Peak memory 202056 kb
Host smart-a2a4b081-3145-4cc5-9d97-55cb113ed848
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193487584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3193487584
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1426934846
Short name T595
Test name
Test status
Simulation time 130256551253 ps
CPU time 443.02 seconds
Started Aug 15 06:23:37 PM PDT 24
Finished Aug 15 06:31:00 PM PDT 24
Peak memory 202416 kb
Host smart-a0bf9c18-4ae5-4e7d-b992-387bbda7f29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426934846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1426934846
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2673930895
Short name T418
Test name
Test status
Simulation time 37150767772 ps
CPU time 22.53 seconds
Started Aug 15 06:23:38 PM PDT 24
Finished Aug 15 06:24:01 PM PDT 24
Peak memory 201936 kb
Host smart-2e95c1ba-dfca-452d-9540-91ead02c932c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673930895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2673930895
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.502335540
Short name T446
Test name
Test status
Simulation time 2842872193 ps
CPU time 7.07 seconds
Started Aug 15 06:23:38 PM PDT 24
Finished Aug 15 06:23:45 PM PDT 24
Peak memory 201948 kb
Host smart-76e3a8dc-8512-4661-8ff7-736a19e3491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502335540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.502335540
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.421352884
Short name T684
Test name
Test status
Simulation time 5852006763 ps
CPU time 4.27 seconds
Started Aug 15 06:23:29 PM PDT 24
Finished Aug 15 06:23:33 PM PDT 24
Peak memory 201916 kb
Host smart-c4519c7a-605b-4c13-90af-e4ec1dcd9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421352884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.421352884
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2864270870
Short name T547
Test name
Test status
Simulation time 45672482164 ps
CPU time 49.99 seconds
Started Aug 15 06:23:37 PM PDT 24
Finished Aug 15 06:24:27 PM PDT 24
Peak memory 201908 kb
Host smart-652eec14-0417-4625-86de-bed78e58621c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864270870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2864270870
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1389408687
Short name T600
Test name
Test status
Simulation time 5188776245 ps
CPU time 7.16 seconds
Started Aug 15 06:23:38 PM PDT 24
Finished Aug 15 06:23:45 PM PDT 24
Peak memory 202224 kb
Host smart-9c723ec9-4381-474c-b729-33156f367631
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389408687 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1389408687
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.658500510
Short name T466
Test name
Test status
Simulation time 315597391 ps
CPU time 1.33 seconds
Started Aug 15 06:23:45 PM PDT 24
Finished Aug 15 06:23:46 PM PDT 24
Peak memory 201928 kb
Host smart-f743ec66-7bd5-4a8b-98f4-21a208765e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658500510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.658500510
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2366092387
Short name T231
Test name
Test status
Simulation time 325590792914 ps
CPU time 675.16 seconds
Started Aug 15 06:23:46 PM PDT 24
Finished Aug 15 06:35:01 PM PDT 24
Peak memory 202140 kb
Host smart-fc051f26-d599-45de-a52b-c4e1c390954a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366092387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2366092387
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1612759290
Short name T789
Test name
Test status
Simulation time 332977808248 ps
CPU time 398.22 seconds
Started Aug 15 06:23:38 PM PDT 24
Finished Aug 15 06:30:17 PM PDT 24
Peak memory 202100 kb
Host smart-5bb9d441-465a-4a43-ac4f-17816fa8dbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612759290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1612759290
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.953768426
Short name T28
Test name
Test status
Simulation time 165219859717 ps
CPU time 100.95 seconds
Started Aug 15 06:23:37 PM PDT 24
Finished Aug 15 06:25:18 PM PDT 24
Peak memory 202116 kb
Host smart-dab1517d-d304-4366-9bb7-f4bed049f861
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=953768426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.953768426
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.519821383
Short name T93
Test name
Test status
Simulation time 328897009334 ps
CPU time 370.08 seconds
Started Aug 15 06:23:38 PM PDT 24
Finished Aug 15 06:29:49 PM PDT 24
Peak memory 202096 kb
Host smart-f58d7fb4-b80f-4920-b6b0-f6481c25c17b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=519821383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.519821383
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1331142961
Short name T748
Test name
Test status
Simulation time 209916890845 ps
CPU time 120.08 seconds
Started Aug 15 06:23:47 PM PDT 24
Finished Aug 15 06:25:47 PM PDT 24
Peak memory 202088 kb
Host smart-fa3d8bb0-7e1e-416d-b4b5-d861578af87e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331142961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1331142961
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1825699231
Short name T548
Test name
Test status
Simulation time 89627792059 ps
CPU time 316.53 seconds
Started Aug 15 06:23:52 PM PDT 24
Finished Aug 15 06:29:09 PM PDT 24
Peak memory 202376 kb
Host smart-fd7e62ae-27b7-463b-bf1a-beaf14687ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825699231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1825699231
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2178605235
Short name T449
Test name
Test status
Simulation time 39157480752 ps
CPU time 95.22 seconds
Started Aug 15 06:23:52 PM PDT 24
Finished Aug 15 06:25:28 PM PDT 24
Peak memory 201968 kb
Host smart-b749282a-7f2e-44ae-a663-af13cff1c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178605235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2178605235
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2194240276
Short name T546
Test name
Test status
Simulation time 5382155913 ps
CPU time 13.46 seconds
Started Aug 15 06:23:45 PM PDT 24
Finished Aug 15 06:23:58 PM PDT 24
Peak memory 201956 kb
Host smart-a5a8e86f-c321-4782-a111-4dca3c93dcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194240276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2194240276
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3275097462
Short name T488
Test name
Test status
Simulation time 5744593216 ps
CPU time 4.17 seconds
Started Aug 15 06:23:36 PM PDT 24
Finished Aug 15 06:23:40 PM PDT 24
Peak memory 201948 kb
Host smart-a5cdb3a0-7e30-44b0-aa99-141e4c7873a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275097462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3275097462
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1755742744
Short name T496
Test name
Test status
Simulation time 334232286040 ps
CPU time 201.63 seconds
Started Aug 15 06:23:45 PM PDT 24
Finished Aug 15 06:27:06 PM PDT 24
Peak memory 202000 kb
Host smart-8433541f-5018-4918-aa79-34fff1493413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755742744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1755742744
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2665039391
Short name T632
Test name
Test status
Simulation time 288138024 ps
CPU time 0.95 seconds
Started Aug 15 06:24:00 PM PDT 24
Finished Aug 15 06:24:01 PM PDT 24
Peak memory 201964 kb
Host smart-15ad2505-cbb8-4b48-81a8-919f014eeae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665039391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2665039391
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.640054699
Short name T582
Test name
Test status
Simulation time 170934878804 ps
CPU time 91 seconds
Started Aug 15 06:23:52 PM PDT 24
Finished Aug 15 06:25:23 PM PDT 24
Peak memory 202104 kb
Host smart-aa80b0cb-69f1-43dc-bf20-d6f201355b76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640054699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.640054699
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1859994368
Short name T158
Test name
Test status
Simulation time 504738551214 ps
CPU time 161.76 seconds
Started Aug 15 06:23:53 PM PDT 24
Finished Aug 15 06:26:35 PM PDT 24
Peak memory 202136 kb
Host smart-c064501a-0e0c-403f-814d-458682fdc1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859994368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1859994368
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1231002321
Short name T633
Test name
Test status
Simulation time 322709576885 ps
CPU time 510.68 seconds
Started Aug 15 06:23:44 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 202140 kb
Host smart-603207ac-9d36-4731-a1d1-9a6017b41347
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231002321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1231002321
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.288109722
Short name T745
Test name
Test status
Simulation time 323615716314 ps
CPU time 87.54 seconds
Started Aug 15 06:23:46 PM PDT 24
Finished Aug 15 06:25:13 PM PDT 24
Peak memory 202124 kb
Host smart-06b9a52a-a799-4e69-a5be-2e1b73fc2eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288109722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.288109722
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2089731234
Short name T497
Test name
Test status
Simulation time 164869122964 ps
CPU time 405.64 seconds
Started Aug 15 06:23:43 PM PDT 24
Finished Aug 15 06:30:29 PM PDT 24
Peak memory 202124 kb
Host smart-b8aff86c-091b-4d81-94fd-8cb413e239dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089731234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2089731234
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2787406890
Short name T344
Test name
Test status
Simulation time 342635182375 ps
CPU time 818 seconds
Started Aug 15 06:23:51 PM PDT 24
Finished Aug 15 06:37:30 PM PDT 24
Peak memory 202072 kb
Host smart-2b3d7a2a-1315-4343-9cc3-05affd929a20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787406890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2787406890
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.993661876
Short name T409
Test name
Test status
Simulation time 191745079633 ps
CPU time 107.45 seconds
Started Aug 15 06:23:49 PM PDT 24
Finished Aug 15 06:25:37 PM PDT 24
Peak memory 202144 kb
Host smart-73e5b87d-9cec-4d7d-b2ad-2ce84db1addc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993661876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.993661876
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1986162256
Short name T794
Test name
Test status
Simulation time 72836868631 ps
CPU time 286.25 seconds
Started Aug 15 06:23:57 PM PDT 24
Finished Aug 15 06:28:44 PM PDT 24
Peak memory 202440 kb
Host smart-173cbbeb-1453-4fff-8d0b-48d0cde035f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986162256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1986162256
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.816736913
Short name T771
Test name
Test status
Simulation time 43865180650 ps
CPU time 26.81 seconds
Started Aug 15 06:23:51 PM PDT 24
Finished Aug 15 06:24:18 PM PDT 24
Peak memory 201904 kb
Host smart-706b5490-0299-4a76-b2f1-dbd117b05765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816736913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.816736913
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3347627933
Short name T392
Test name
Test status
Simulation time 5200722046 ps
CPU time 3.41 seconds
Started Aug 15 06:23:52 PM PDT 24
Finished Aug 15 06:23:55 PM PDT 24
Peak memory 201944 kb
Host smart-88836cee-8ab6-4325-924b-2ce5278c5151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347627933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3347627933
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.386007277
Short name T572
Test name
Test status
Simulation time 6062180999 ps
CPU time 2.07 seconds
Started Aug 15 06:23:43 PM PDT 24
Finished Aug 15 06:23:46 PM PDT 24
Peak memory 201900 kb
Host smart-5fe108c0-4f83-43e2-b0cc-73973015a8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386007277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.386007277
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2138896003
Short name T30
Test name
Test status
Simulation time 331342328988 ps
CPU time 431.17 seconds
Started Aug 15 06:24:00 PM PDT 24
Finished Aug 15 06:31:11 PM PDT 24
Peak memory 202132 kb
Host smart-06cfca3b-17d2-4ee0-8302-e96d44af0878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138896003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2138896003
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1470065733
Short name T264
Test name
Test status
Simulation time 6174300925 ps
CPU time 9.65 seconds
Started Aug 15 06:23:57 PM PDT 24
Finished Aug 15 06:24:07 PM PDT 24
Peak memory 210524 kb
Host smart-088e5403-8ff2-43a1-80ed-687365298677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470065733 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1470065733
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3424589162
Short name T461
Test name
Test status
Simulation time 341362223 ps
CPU time 1.02 seconds
Started Aug 15 06:24:08 PM PDT 24
Finished Aug 15 06:24:09 PM PDT 24
Peak memory 201960 kb
Host smart-856804d5-3a04-430a-a9dc-044f55804734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424589162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3424589162
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2951855448
Short name T762
Test name
Test status
Simulation time 167282941599 ps
CPU time 99.04 seconds
Started Aug 15 06:23:59 PM PDT 24
Finished Aug 15 06:25:38 PM PDT 24
Peak memory 202164 kb
Host smart-fcc42bcf-84a2-4d0e-87f6-e1cbc0c6c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951855448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2951855448
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3568625473
Short name T387
Test name
Test status
Simulation time 489920256303 ps
CPU time 132.34 seconds
Started Aug 15 06:23:57 PM PDT 24
Finished Aug 15 06:26:09 PM PDT 24
Peak memory 202120 kb
Host smart-7519031c-af0d-4090-b024-d049907a5818
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568625473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3568625473
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2331639118
Short name T136
Test name
Test status
Simulation time 486989245608 ps
CPU time 289.48 seconds
Started Aug 15 06:23:57 PM PDT 24
Finished Aug 15 06:28:47 PM PDT 24
Peak memory 202136 kb
Host smart-6a5679e7-a5b3-4682-abf4-037737a444a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331639118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2331639118
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.846993335
Short name T458
Test name
Test status
Simulation time 326610388466 ps
CPU time 722.39 seconds
Started Aug 15 06:23:57 PM PDT 24
Finished Aug 15 06:36:00 PM PDT 24
Peak memory 201976 kb
Host smart-7dd12905-092a-48d0-b7f8-7a342ae9bfee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=846993335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.846993335
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3266717430
Short name T370
Test name
Test status
Simulation time 201815226673 ps
CPU time 133.89 seconds
Started Aug 15 06:23:58 PM PDT 24
Finished Aug 15 06:26:12 PM PDT 24
Peak memory 202084 kb
Host smart-bb8c3242-bef8-4896-a924-0a7b210075de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266717430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3266717430
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1384361440
Short name T42
Test name
Test status
Simulation time 129498513682 ps
CPU time 517.03 seconds
Started Aug 15 06:24:08 PM PDT 24
Finished Aug 15 06:32:46 PM PDT 24
Peak memory 202384 kb
Host smart-b19ffaf9-2eee-4f1c-89bd-50b4dbd67d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384361440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1384361440
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2988882015
Short name T485
Test name
Test status
Simulation time 37246999345 ps
CPU time 86.3 seconds
Started Aug 15 06:24:06 PM PDT 24
Finished Aug 15 06:25:33 PM PDT 24
Peak memory 201952 kb
Host smart-783fb6cd-fce2-4b52-8093-2d57df6fb9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988882015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2988882015
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.646491605
Short name T492
Test name
Test status
Simulation time 3996788947 ps
CPU time 10.08 seconds
Started Aug 15 06:23:56 PM PDT 24
Finished Aug 15 06:24:06 PM PDT 24
Peak memory 201972 kb
Host smart-16808b1c-45d1-49af-a4a8-980cb9e0be37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646491605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.646491605
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2882234561
Short name T733
Test name
Test status
Simulation time 6021186205 ps
CPU time 8.27 seconds
Started Aug 15 06:23:57 PM PDT 24
Finished Aug 15 06:24:06 PM PDT 24
Peak memory 201904 kb
Host smart-fdaa8cec-ae46-425e-a09a-151f42b25dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882234561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2882234561
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2110955790
Short name T521
Test name
Test status
Simulation time 328656673009 ps
CPU time 549.2 seconds
Started Aug 15 06:24:05 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 202124 kb
Host smart-7a2daca5-9883-4eb6-bf2e-44f7bb47bee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110955790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2110955790
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1833052272
Short name T678
Test name
Test status
Simulation time 1035038233 ps
CPU time 4.16 seconds
Started Aug 15 06:24:05 PM PDT 24
Finished Aug 15 06:24:09 PM PDT 24
Peak memory 202004 kb
Host smart-fc329124-449b-48ca-bac6-a7fc1835fc9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833052272 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1833052272
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2552414689
Short name T490
Test name
Test status
Simulation time 348578847 ps
CPU time 1.29 seconds
Started Aug 15 06:24:12 PM PDT 24
Finished Aug 15 06:24:13 PM PDT 24
Peak memory 201956 kb
Host smart-c30a1c9c-98fe-4cc6-aa19-e42701ba1f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552414689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2552414689
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1682281116
Short name T329
Test name
Test status
Simulation time 360671938407 ps
CPU time 486.5 seconds
Started Aug 15 06:24:16 PM PDT 24
Finished Aug 15 06:32:22 PM PDT 24
Peak memory 202124 kb
Host smart-1b594acb-cc1c-4cb2-bb40-f45dafdc0b3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682281116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1682281116
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2434323626
Short name T685
Test name
Test status
Simulation time 352542773819 ps
CPU time 743.94 seconds
Started Aug 15 06:24:17 PM PDT 24
Finished Aug 15 06:36:41 PM PDT 24
Peak memory 202132 kb
Host smart-636c6997-4d30-489e-b4e0-9cd5aa4a54e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434323626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2434323626
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1212761682
Short name T129
Test name
Test status
Simulation time 489195229368 ps
CPU time 310.51 seconds
Started Aug 15 06:24:06 PM PDT 24
Finished Aug 15 06:29:17 PM PDT 24
Peak memory 202036 kb
Host smart-c8e294ab-78b2-49f0-ae04-fb88e32c5455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212761682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1212761682
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3316783255
Short name T768
Test name
Test status
Simulation time 325998283842 ps
CPU time 58.05 seconds
Started Aug 15 06:24:04 PM PDT 24
Finished Aug 15 06:25:02 PM PDT 24
Peak memory 202156 kb
Host smart-60fbac3e-2b38-4d1b-ab03-c92caea49eba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316783255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3316783255
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.790324649
Short name T690
Test name
Test status
Simulation time 321658308319 ps
CPU time 754.72 seconds
Started Aug 15 06:24:06 PM PDT 24
Finished Aug 15 06:36:41 PM PDT 24
Peak memory 202180 kb
Host smart-eed15f80-41fa-4251-a44d-93283f62dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790324649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.790324649
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1980431619
Short name T179
Test name
Test status
Simulation time 168485510713 ps
CPU time 392.58 seconds
Started Aug 15 06:24:07 PM PDT 24
Finished Aug 15 06:30:40 PM PDT 24
Peak memory 202092 kb
Host smart-023e53b1-ff9b-49f0-b5b1-6214228f2b9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980431619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1980431619
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.420459173
Short name T342
Test name
Test status
Simulation time 180186250300 ps
CPU time 99.83 seconds
Started Aug 15 06:24:06 PM PDT 24
Finished Aug 15 06:25:46 PM PDT 24
Peak memory 202136 kb
Host smart-6a09c13b-322c-4f2c-bf4a-884b571e541d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420459173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.420459173
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1411298975
Short name T378
Test name
Test status
Simulation time 399827688949 ps
CPU time 147.4 seconds
Started Aug 15 06:24:04 PM PDT 24
Finished Aug 15 06:26:32 PM PDT 24
Peak memory 202096 kb
Host smart-883f99e3-188d-48e4-b21b-8549a74306f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411298975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1411298975
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.833028554
Short name T37
Test name
Test status
Simulation time 102081406564 ps
CPU time 554.8 seconds
Started Aug 15 06:24:11 PM PDT 24
Finished Aug 15 06:33:26 PM PDT 24
Peak memory 202328 kb
Host smart-c8478730-36d4-4f4b-9396-39d52abd911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833028554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.833028554
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3342491260
Short name T375
Test name
Test status
Simulation time 25819325600 ps
CPU time 8.02 seconds
Started Aug 15 06:24:12 PM PDT 24
Finished Aug 15 06:24:21 PM PDT 24
Peak memory 201964 kb
Host smart-547324b9-a4b3-446d-95f9-98c4460bf124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342491260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3342491260
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3432432901
Short name T655
Test name
Test status
Simulation time 4522109319 ps
CPU time 2.56 seconds
Started Aug 15 06:24:13 PM PDT 24
Finished Aug 15 06:24:15 PM PDT 24
Peak memory 201916 kb
Host smart-0a79ab54-bf33-4f45-ad29-dc737be4219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432432901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3432432901
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.363833170
Short name T716
Test name
Test status
Simulation time 5915932516 ps
CPU time 4.42 seconds
Started Aug 15 06:24:05 PM PDT 24
Finished Aug 15 06:24:10 PM PDT 24
Peak memory 201896 kb
Host smart-0a53976b-343e-41e6-9560-5d425da9a121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363833170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.363833170
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1083412678
Short name T606
Test name
Test status
Simulation time 168930964956 ps
CPU time 188.01 seconds
Started Aug 15 06:24:11 PM PDT 24
Finished Aug 15 06:27:19 PM PDT 24
Peak memory 202124 kb
Host smart-9b6290bd-c603-4c5b-9a5f-ed365a72f11d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083412678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1083412678
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.555394024
Short name T640
Test name
Test status
Simulation time 4501374984 ps
CPU time 6.01 seconds
Started Aug 15 06:24:12 PM PDT 24
Finished Aug 15 06:24:18 PM PDT 24
Peak memory 202116 kb
Host smart-91930e25-1df4-4f2c-9650-6db343fed36a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555394024 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.555394024
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2675682266
Short name T564
Test name
Test status
Simulation time 464854766 ps
CPU time 0.82 seconds
Started Aug 15 06:24:23 PM PDT 24
Finished Aug 15 06:24:24 PM PDT 24
Peak memory 201964 kb
Host smart-0af84475-5e77-4214-92a2-c0d04e27563b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675682266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2675682266
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2028808209
Short name T300
Test name
Test status
Simulation time 500796933358 ps
CPU time 402.17 seconds
Started Aug 15 06:24:21 PM PDT 24
Finished Aug 15 06:31:03 PM PDT 24
Peak memory 202124 kb
Host smart-bbd3c916-2416-469c-9306-d7f99c8d1890
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028808209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2028808209
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1580874355
Short name T236
Test name
Test status
Simulation time 339631404447 ps
CPU time 703.29 seconds
Started Aug 15 06:24:23 PM PDT 24
Finished Aug 15 06:36:07 PM PDT 24
Peak memory 202140 kb
Host smart-1f39f1e9-6b71-446a-93fc-749b624621e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580874355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1580874355
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3309005500
Short name T424
Test name
Test status
Simulation time 326878386260 ps
CPU time 381.36 seconds
Started Aug 15 06:24:13 PM PDT 24
Finished Aug 15 06:30:35 PM PDT 24
Peak memory 202120 kb
Host smart-6ca6447e-808e-447c-ba06-b51ed06fe96d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309005500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3309005500
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.874321056
Short name T137
Test name
Test status
Simulation time 489743815224 ps
CPU time 1150.7 seconds
Started Aug 15 06:24:12 PM PDT 24
Finished Aug 15 06:43:23 PM PDT 24
Peak memory 202164 kb
Host smart-2c3b6b33-8b3c-4180-a019-9f9941409f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874321056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.874321056
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1415317787
Short name T422
Test name
Test status
Simulation time 167158373391 ps
CPU time 384.26 seconds
Started Aug 15 06:24:17 PM PDT 24
Finished Aug 15 06:30:42 PM PDT 24
Peak memory 202100 kb
Host smart-8ddebeeb-0e19-460c-afca-356ea6bfc9d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415317787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1415317787
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2548668890
Short name T433
Test name
Test status
Simulation time 197053537242 ps
CPU time 121.2 seconds
Started Aug 15 06:24:21 PM PDT 24
Finished Aug 15 06:26:22 PM PDT 24
Peak memory 202136 kb
Host smart-c7e152d3-51f0-4782-a2c4-4b49759e2235
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548668890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2548668890
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1341735850
Short name T734
Test name
Test status
Simulation time 35842108089 ps
CPU time 10.02 seconds
Started Aug 15 06:24:21 PM PDT 24
Finished Aug 15 06:24:31 PM PDT 24
Peak memory 201972 kb
Host smart-ca98d31f-a96d-4011-8775-dca5d0f08385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341735850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1341735850
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.531987004
Short name T412
Test name
Test status
Simulation time 3029910518 ps
CPU time 4.13 seconds
Started Aug 15 06:24:23 PM PDT 24
Finished Aug 15 06:24:28 PM PDT 24
Peak memory 201956 kb
Host smart-ddf39a3e-6260-4384-87fa-d6f0eb86991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531987004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.531987004
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1306363848
Short name T705
Test name
Test status
Simulation time 5991994140 ps
CPU time 15.12 seconds
Started Aug 15 06:24:16 PM PDT 24
Finished Aug 15 06:24:31 PM PDT 24
Peak memory 201952 kb
Host smart-e0890fdc-3f3c-477d-8d61-b676fd9dc1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306363848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1306363848
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2093869484
Short name T282
Test name
Test status
Simulation time 330819694815 ps
CPU time 723.73 seconds
Started Aug 15 06:24:22 PM PDT 24
Finished Aug 15 06:36:26 PM PDT 24
Peak memory 202124 kb
Host smart-e44ac26b-872d-48f9-a909-5b5e34bbf07e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093869484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2093869484
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1417250772
Short name T17
Test name
Test status
Simulation time 2214270089 ps
CPU time 8.06 seconds
Started Aug 15 06:24:25 PM PDT 24
Finished Aug 15 06:24:34 PM PDT 24
Peak memory 210568 kb
Host smart-24034000-9770-4768-b47f-58bd778c8d1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417250772 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1417250772
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3215123175
Short name T358
Test name
Test status
Simulation time 476178937 ps
CPU time 0.85 seconds
Started Aug 15 06:24:25 PM PDT 24
Finished Aug 15 06:24:26 PM PDT 24
Peak memory 201944 kb
Host smart-0e668f14-e935-4331-b6fc-1fb3c7e7f1c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215123175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3215123175
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2052574300
Short name T320
Test name
Test status
Simulation time 168167940334 ps
CPU time 404.34 seconds
Started Aug 15 06:24:23 PM PDT 24
Finished Aug 15 06:31:07 PM PDT 24
Peak memory 202156 kb
Host smart-355cb802-1a15-467d-b0ae-f2525e3a26d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052574300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2052574300
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.9025326
Short name T72
Test name
Test status
Simulation time 326049855773 ps
CPU time 701.74 seconds
Started Aug 15 06:24:26 PM PDT 24
Finished Aug 15 06:36:08 PM PDT 24
Peak memory 202120 kb
Host smart-88a32208-09c3-42f9-8f44-dc59190ff215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9025326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.9025326
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1943534886
Short name T454
Test name
Test status
Simulation time 502080442046 ps
CPU time 1155.42 seconds
Started Aug 15 06:24:22 PM PDT 24
Finished Aug 15 06:43:38 PM PDT 24
Peak memory 202124 kb
Host smart-a866825b-0e16-4430-8ffd-697430f30854
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943534886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1943534886
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1168836593
Short name T213
Test name
Test status
Simulation time 491990605272 ps
CPU time 301.13 seconds
Started Aug 15 06:24:26 PM PDT 24
Finished Aug 15 06:29:27 PM PDT 24
Peak memory 202076 kb
Host smart-a2334774-9fb6-4292-a996-9ccd7c328f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168836593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1168836593
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2695150172
Short name T486
Test name
Test status
Simulation time 167974763846 ps
CPU time 192.12 seconds
Started Aug 15 06:24:26 PM PDT 24
Finished Aug 15 06:27:38 PM PDT 24
Peak memory 202060 kb
Host smart-f2088732-fa92-4518-8153-09240e6a669b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695150172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2695150172
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1097215134
Short name T597
Test name
Test status
Simulation time 551921200363 ps
CPU time 320.22 seconds
Started Aug 15 06:24:23 PM PDT 24
Finished Aug 15 06:29:44 PM PDT 24
Peak memory 202068 kb
Host smart-a6ed4c36-facc-4ccf-bfca-443d6920b57b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097215134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1097215134
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1244618988
Short name T696
Test name
Test status
Simulation time 392742101149 ps
CPU time 249.23 seconds
Started Aug 15 06:24:21 PM PDT 24
Finished Aug 15 06:28:31 PM PDT 24
Peak memory 202140 kb
Host smart-d3bce0e7-7108-4c98-aff0-cdbc0e3ba421
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244618988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1244618988
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.388129957
Short name T352
Test name
Test status
Simulation time 86165267865 ps
CPU time 312.92 seconds
Started Aug 15 06:24:25 PM PDT 24
Finished Aug 15 06:29:38 PM PDT 24
Peak memory 202380 kb
Host smart-d2887f0f-a68b-4a04-ac06-d428d7072c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388129957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.388129957
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2930694582
Short name T444
Test name
Test status
Simulation time 47414040201 ps
CPU time 13.14 seconds
Started Aug 15 06:24:26 PM PDT 24
Finished Aug 15 06:24:39 PM PDT 24
Peak memory 201904 kb
Host smart-cd232cbf-56d0-4e50-b52b-5ab997ec8c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930694582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2930694582
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2928039187
Short name T188
Test name
Test status
Simulation time 3076997446 ps
CPU time 7.85 seconds
Started Aug 15 06:24:23 PM PDT 24
Finished Aug 15 06:24:31 PM PDT 24
Peak memory 201900 kb
Host smart-047ef22c-850e-484b-b20d-8337d065d4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928039187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2928039187
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3325115009
Short name T539
Test name
Test status
Simulation time 5597012940 ps
CPU time 2.58 seconds
Started Aug 15 06:24:20 PM PDT 24
Finished Aug 15 06:24:23 PM PDT 24
Peak memory 201896 kb
Host smart-a8ade7ec-44e5-4a46-a5ad-737554b93c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325115009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3325115009
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3680088960
Short name T153
Test name
Test status
Simulation time 340548421702 ps
CPU time 787.89 seconds
Started Aug 15 06:24:28 PM PDT 24
Finished Aug 15 06:37:36 PM PDT 24
Peak memory 202084 kb
Host smart-5ebefb8e-e946-4a7c-967f-6eb9ee23e59f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680088960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3680088960
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2268284017
Short name T34
Test name
Test status
Simulation time 10632440575 ps
CPU time 7.13 seconds
Started Aug 15 06:24:28 PM PDT 24
Finished Aug 15 06:24:36 PM PDT 24
Peak memory 202304 kb
Host smart-6b802865-dad8-48a3-a456-f72a29b79429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268284017 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2268284017
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4017789966
Short name T493
Test name
Test status
Simulation time 430532423 ps
CPU time 1.07 seconds
Started Aug 15 06:24:34 PM PDT 24
Finished Aug 15 06:24:35 PM PDT 24
Peak memory 201972 kb
Host smart-166cc74d-bafa-441b-af4c-6811a514f0f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017789966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4017789966
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.735296459
Short name T764
Test name
Test status
Simulation time 164965593699 ps
CPU time 183.09 seconds
Started Aug 15 06:24:28 PM PDT 24
Finished Aug 15 06:27:32 PM PDT 24
Peak memory 202196 kb
Host smart-fdea01bc-6d34-41c6-aea0-37d32952cae5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735296459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.735296459
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2411430132
Short name T165
Test name
Test status
Simulation time 327464803494 ps
CPU time 141.11 seconds
Started Aug 15 06:24:29 PM PDT 24
Finished Aug 15 06:26:50 PM PDT 24
Peak memory 202136 kb
Host smart-90e8338c-c7ea-4100-90be-f7c421adbef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411430132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2411430132
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.933354954
Short name T649
Test name
Test status
Simulation time 490979273196 ps
CPU time 229.27 seconds
Started Aug 15 06:24:28 PM PDT 24
Finished Aug 15 06:28:18 PM PDT 24
Peak memory 202160 kb
Host smart-6c4f7001-e2e5-4627-8057-98d7eb906605
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=933354954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.933354954
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2077584887
Short name T791
Test name
Test status
Simulation time 500879421482 ps
CPU time 571.49 seconds
Started Aug 15 06:24:26 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 202132 kb
Host smart-9f8025f1-7e23-4bc8-8c1c-1a37b52ab8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077584887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2077584887
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3800384431
Short name T69
Test name
Test status
Simulation time 166800841520 ps
CPU time 97.31 seconds
Started Aug 15 06:24:28 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 202140 kb
Host smart-75ae42a6-2047-4a30-8b82-dc93e4e1fbb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800384431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3800384431
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.379845454
Short name T777
Test name
Test status
Simulation time 418268110624 ps
CPU time 642.76 seconds
Started Aug 15 06:24:28 PM PDT 24
Finished Aug 15 06:35:11 PM PDT 24
Peak memory 202144 kb
Host smart-61c15e57-e18c-4da3-829a-d0df77a7478f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379845454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.379845454
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1198449206
Short name T472
Test name
Test status
Simulation time 97847462674 ps
CPU time 395.73 seconds
Started Aug 15 06:24:33 PM PDT 24
Finished Aug 15 06:31:09 PM PDT 24
Peak memory 202396 kb
Host smart-82989f45-b1e0-4257-97d9-a718d45b0046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198449206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1198449206
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4131767526
Short name T718
Test name
Test status
Simulation time 43782735541 ps
CPU time 102.21 seconds
Started Aug 15 06:24:34 PM PDT 24
Finished Aug 15 06:26:16 PM PDT 24
Peak memory 201952 kb
Host smart-aecf1495-c92d-4d6e-9454-8e425acbc87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131767526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.4131767526
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.74069182
Short name T9
Test name
Test status
Simulation time 5069612044 ps
CPU time 2.13 seconds
Started Aug 15 06:24:36 PM PDT 24
Finished Aug 15 06:24:39 PM PDT 24
Peak memory 201952 kb
Host smart-28e4b061-2ea1-4049-8bc4-4031927343c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74069182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.74069182
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.564621366
Short name T593
Test name
Test status
Simulation time 5751051063 ps
CPU time 4.13 seconds
Started Aug 15 06:24:27 PM PDT 24
Finished Aug 15 06:24:31 PM PDT 24
Peak memory 201928 kb
Host smart-96ea5ed1-acff-4f24-88fe-4289a6a83cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564621366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.564621366
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2936771956
Short name T571
Test name
Test status
Simulation time 143879583526 ps
CPU time 458.03 seconds
Started Aug 15 06:24:36 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 211788 kb
Host smart-16b41f74-b614-4bb4-ace9-1bbe539610fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936771956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2936771956
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2954265467
Short name T673
Test name
Test status
Simulation time 74135371845 ps
CPU time 23.89 seconds
Started Aug 15 06:24:34 PM PDT 24
Finished Aug 15 06:24:58 PM PDT 24
Peak memory 210756 kb
Host smart-858bd2aa-5184-4d55-95fd-3eb2b907c4f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954265467 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2954265467
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.63053717
Short name T784
Test name
Test status
Simulation time 344115827 ps
CPU time 0.81 seconds
Started Aug 15 06:24:41 PM PDT 24
Finished Aug 15 06:24:42 PM PDT 24
Peak memory 201952 kb
Host smart-cb0e9ba8-c92d-425b-ac28-f353f3d622b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63053717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.63053717
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2040241734
Short name T178
Test name
Test status
Simulation time 571725623958 ps
CPU time 75.79 seconds
Started Aug 15 06:24:43 PM PDT 24
Finished Aug 15 06:25:59 PM PDT 24
Peak memory 202132 kb
Host smart-c92c73a6-42ae-40ab-9c18-3891f547bc2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040241734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2040241734
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1537626166
Short name T337
Test name
Test status
Simulation time 488096811926 ps
CPU time 1057.9 seconds
Started Aug 15 06:24:37 PM PDT 24
Finished Aug 15 06:42:15 PM PDT 24
Peak memory 202172 kb
Host smart-e926f193-6aec-4bb7-8823-dce5818eab3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537626166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1537626166
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3295930207
Short name T456
Test name
Test status
Simulation time 166133179501 ps
CPU time 405.42 seconds
Started Aug 15 06:24:41 PM PDT 24
Finished Aug 15 06:31:27 PM PDT 24
Peak memory 202124 kb
Host smart-3f4c6ad5-90cf-440d-a90a-00777be2c2ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295930207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3295930207
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2924176249
Short name T281
Test name
Test status
Simulation time 491240676271 ps
CPU time 985.38 seconds
Started Aug 15 06:24:35 PM PDT 24
Finished Aug 15 06:41:00 PM PDT 24
Peak memory 202208 kb
Host smart-e943a869-5fb7-417b-950d-1b2042afd977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924176249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2924176249
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3325932478
Short name T558
Test name
Test status
Simulation time 333813459925 ps
CPU time 377.13 seconds
Started Aug 15 06:24:34 PM PDT 24
Finished Aug 15 06:30:52 PM PDT 24
Peak memory 202096 kb
Host smart-e9955319-d44b-4ef8-883b-246c1deeea8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325932478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3325932478
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2380382474
Short name T2
Test name
Test status
Simulation time 537307123931 ps
CPU time 609.43 seconds
Started Aug 15 06:24:40 PM PDT 24
Finished Aug 15 06:34:50 PM PDT 24
Peak memory 202064 kb
Host smart-b707eb31-c3b2-4257-92cd-cae94b8f55e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380382474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2380382474
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2833983752
Short name T484
Test name
Test status
Simulation time 395085671492 ps
CPU time 254.29 seconds
Started Aug 15 06:24:43 PM PDT 24
Finished Aug 15 06:28:58 PM PDT 24
Peak memory 202104 kb
Host smart-a9b79389-656e-42c8-8aef-529b50e01393
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833983752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2833983752
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2407353595
Short name T39
Test name
Test status
Simulation time 90567730141 ps
CPU time 477.1 seconds
Started Aug 15 06:24:40 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 202228 kb
Host smart-8932622f-92c2-424b-a616-54cf7a2a2089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407353595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2407353595
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3867745153
Short name T769
Test name
Test status
Simulation time 26976191137 ps
CPU time 16.67 seconds
Started Aug 15 06:24:43 PM PDT 24
Finished Aug 15 06:25:00 PM PDT 24
Peak memory 201952 kb
Host smart-96dd4d1a-d59d-4c57-a0f0-c05611422b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867745153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3867745153
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.654402460
Short name T515
Test name
Test status
Simulation time 5185241922 ps
CPU time 6.14 seconds
Started Aug 15 06:24:41 PM PDT 24
Finished Aug 15 06:24:48 PM PDT 24
Peak memory 201960 kb
Host smart-a2eadbe9-3cf2-4cd1-a7db-c716adc85cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654402460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.654402460
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.287330317
Short name T522
Test name
Test status
Simulation time 6030427769 ps
CPU time 8.07 seconds
Started Aug 15 06:24:36 PM PDT 24
Finished Aug 15 06:24:44 PM PDT 24
Peak memory 201980 kb
Host smart-7aec5630-89ac-46c7-a927-6bf2a94dca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287330317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.287330317
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4058504955
Short name T334
Test name
Test status
Simulation time 465815578330 ps
CPU time 1488.49 seconds
Started Aug 15 06:24:41 PM PDT 24
Finished Aug 15 06:49:30 PM PDT 24
Peak memory 210584 kb
Host smart-f3983c29-3d6a-4d37-b985-e921eb7a8ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058504955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4058504955
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2650880523
Short name T197
Test name
Test status
Simulation time 7272516453 ps
CPU time 15.24 seconds
Started Aug 15 06:24:39 PM PDT 24
Finished Aug 15 06:24:55 PM PDT 24
Peak memory 210664 kb
Host smart-e1644c84-d845-4218-b017-e4f7a9adf99b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650880523 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2650880523
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3016370269
Short name T520
Test name
Test status
Simulation time 422749883 ps
CPU time 0.89 seconds
Started Aug 15 06:20:04 PM PDT 24
Finished Aug 15 06:20:05 PM PDT 24
Peak memory 201980 kb
Host smart-3b530289-558f-4ec9-96f0-e303f58c7455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016370269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3016370269
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.132834537
Short name T756
Test name
Test status
Simulation time 336717326601 ps
CPU time 699.92 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:31:43 PM PDT 24
Peak memory 202148 kb
Host smart-8a80393f-3501-43f9-8500-f0aded1a4208
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132834537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.132834537
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.733814970
Short name T671
Test name
Test status
Simulation time 157892349168 ps
CPU time 45.84 seconds
Started Aug 15 06:20:05 PM PDT 24
Finished Aug 15 06:20:51 PM PDT 24
Peak memory 202128 kb
Host smart-5a14776e-9ff4-4307-a45a-41d79a75ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733814970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.733814970
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3237923409
Short name T289
Test name
Test status
Simulation time 164792164774 ps
CPU time 121.81 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:22:05 PM PDT 24
Peak memory 202072 kb
Host smart-c435b948-78e2-4019-8f49-97f602f11354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237923409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3237923409
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4086787941
Short name T536
Test name
Test status
Simulation time 166391115602 ps
CPU time 104.3 seconds
Started Aug 15 06:20:06 PM PDT 24
Finished Aug 15 06:21:50 PM PDT 24
Peak memory 202124 kb
Host smart-054c30f7-c5f7-413c-8f92-0642244facc3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086787941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4086787941
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3337532396
Short name T148
Test name
Test status
Simulation time 495368881205 ps
CPU time 1037.01 seconds
Started Aug 15 06:20:04 PM PDT 24
Finished Aug 15 06:37:22 PM PDT 24
Peak memory 202072 kb
Host smart-860806e9-30f1-4416-a02e-06a92b5272fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337532396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3337532396
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1561140240
Short name T607
Test name
Test status
Simulation time 325993784005 ps
CPU time 227.2 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:23:50 PM PDT 24
Peak memory 202116 kb
Host smart-a4de10d2-80a0-422f-829e-277e3eb99575
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561140240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1561140240
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1517943399
Short name T692
Test name
Test status
Simulation time 180998550562 ps
CPU time 149.26 seconds
Started Aug 15 06:20:03 PM PDT 24
Finished Aug 15 06:22:33 PM PDT 24
Peak memory 202116 kb
Host smart-6d33d746-daa2-4cef-afbe-71caa9a79547
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517943399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1517943399
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2192512408
Short name T450
Test name
Test status
Simulation time 407019815033 ps
CPU time 475.58 seconds
Started Aug 15 06:20:04 PM PDT 24
Finished Aug 15 06:28:00 PM PDT 24
Peak memory 202092 kb
Host smart-9e5dde5f-d257-4573-913e-a04d2525e8db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192512408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2192512408
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1744504697
Short name T70
Test name
Test status
Simulation time 96489446621 ps
CPU time 321.86 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:25:24 PM PDT 24
Peak memory 202356 kb
Host smart-16f8920a-75db-41bb-93e7-054b2854457d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744504697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1744504697
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2662935777
Short name T487
Test name
Test status
Simulation time 31277210515 ps
CPU time 73.47 seconds
Started Aug 15 06:20:04 PM PDT 24
Finished Aug 15 06:21:17 PM PDT 24
Peak memory 201976 kb
Host smart-57f7f31d-0aea-46cf-b572-964a4746f25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662935777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2662935777
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3761995168
Short name T739
Test name
Test status
Simulation time 3851288141 ps
CPU time 2.93 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:20:04 PM PDT 24
Peak memory 201916 kb
Host smart-7b354c56-0bfb-414d-912b-e7718999efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761995168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3761995168
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2707715764
Short name T464
Test name
Test status
Simulation time 5680137384 ps
CPU time 2.05 seconds
Started Aug 15 06:20:07 PM PDT 24
Finished Aug 15 06:20:09 PM PDT 24
Peak memory 201876 kb
Host smart-a10b1279-7ff9-4b96-92ac-8b6476c653ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707715764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2707715764
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3035208101
Short name T628
Test name
Test status
Simulation time 1826681460754 ps
CPU time 973.74 seconds
Started Aug 15 06:20:04 PM PDT 24
Finished Aug 15 06:36:18 PM PDT 24
Peak memory 210596 kb
Host smart-c63f9850-8e23-48cf-98cb-5b12c62f10fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035208101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3035208101
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.888646434
Short name T1
Test name
Test status
Simulation time 7719461687 ps
CPU time 6.11 seconds
Started Aug 15 06:20:07 PM PDT 24
Finished Aug 15 06:20:13 PM PDT 24
Peak memory 202176 kb
Host smart-c092c3be-bd40-47d8-8d1b-8e3b044a4634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888646434 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.888646434
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3941727152
Short name T58
Test name
Test status
Simulation time 473282551 ps
CPU time 1.75 seconds
Started Aug 15 06:20:12 PM PDT 24
Finished Aug 15 06:20:14 PM PDT 24
Peak memory 201928 kb
Host smart-d5c8dd48-91f2-42ef-a491-3edc5f032f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941727152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3941727152
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3304174745
Short name T303
Test name
Test status
Simulation time 188574975620 ps
CPU time 100.83 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:21:51 PM PDT 24
Peak memory 202124 kb
Host smart-64a498f5-2a34-47d2-ae02-f009b5f8d5ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304174745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3304174745
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.111742211
Short name T180
Test name
Test status
Simulation time 498187608233 ps
CPU time 1197.93 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:40:08 PM PDT 24
Peak memory 202136 kb
Host smart-51d303d1-f6ff-4794-b04f-a5fb6ff5092e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=111742211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.111742211
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3707516641
Short name T166
Test name
Test status
Simulation time 485017000657 ps
CPU time 1193.1 seconds
Started Aug 15 06:20:01 PM PDT 24
Finished Aug 15 06:39:54 PM PDT 24
Peak memory 202124 kb
Host smart-8bf09b36-93fe-49f3-8e07-825dc521d57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707516641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3707516641
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3501366122
Short name T530
Test name
Test status
Simulation time 328891713600 ps
CPU time 194.49 seconds
Started Aug 15 06:20:00 PM PDT 24
Finished Aug 15 06:23:15 PM PDT 24
Peak memory 202104 kb
Host smart-a268f1ce-54af-492c-a274-c0c0c0a2141e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501366122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3501366122
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2090757361
Short name T629
Test name
Test status
Simulation time 360001701020 ps
CPU time 422.66 seconds
Started Aug 15 06:20:11 PM PDT 24
Finished Aug 15 06:27:13 PM PDT 24
Peak memory 202112 kb
Host smart-302a8369-fb99-489d-bfc2-28c387c80c13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090757361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2090757361
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3748951201
Short name T75
Test name
Test status
Simulation time 401076050555 ps
CPU time 836.11 seconds
Started Aug 15 06:20:13 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 202148 kb
Host smart-84253224-5296-434b-ad92-2f9039cfeef5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748951201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3748951201
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3822407467
Short name T509
Test name
Test status
Simulation time 74007646903 ps
CPU time 222.47 seconds
Started Aug 15 06:20:12 PM PDT 24
Finished Aug 15 06:23:55 PM PDT 24
Peak memory 202396 kb
Host smart-9f40246f-bf69-484e-8082-c459a93a2adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822407467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3822407467
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2348049291
Short name T423
Test name
Test status
Simulation time 41252810021 ps
CPU time 47.38 seconds
Started Aug 15 06:20:08 PM PDT 24
Finished Aug 15 06:20:55 PM PDT 24
Peak memory 201900 kb
Host smart-87fbaf98-f04d-4917-9be0-335e9f046750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348049291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2348049291
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.205835502
Short name T666
Test name
Test status
Simulation time 3706245191 ps
CPU time 4.85 seconds
Started Aug 15 06:20:12 PM PDT 24
Finished Aug 15 06:20:17 PM PDT 24
Peak memory 201952 kb
Host smart-01eacbb7-f53c-49a4-8cab-8c93b42e659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205835502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.205835502
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.920248346
Short name T371
Test name
Test status
Simulation time 5632562134 ps
CPU time 13.13 seconds
Started Aug 15 06:20:02 PM PDT 24
Finished Aug 15 06:20:16 PM PDT 24
Peak memory 201960 kb
Host smart-a92786bf-8d6f-4e26-99fe-c7a5d340f6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920248346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.920248346
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1658058198
Short name T204
Test name
Test status
Simulation time 103876882299 ps
CPU time 342.61 seconds
Started Aug 15 06:20:09 PM PDT 24
Finished Aug 15 06:25:51 PM PDT 24
Peak memory 210564 kb
Host smart-d51928ce-4120-4c8b-8d5c-9ef87c0932b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658058198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1658058198
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2657268825
Short name T267
Test name
Test status
Simulation time 11881628784 ps
CPU time 7.81 seconds
Started Aug 15 06:20:11 PM PDT 24
Finished Aug 15 06:20:19 PM PDT 24
Peak memory 202276 kb
Host smart-97f722b8-ca4b-4493-8e9f-60dad4077e3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657268825 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2657268825
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.938921125
Short name T766
Test name
Test status
Simulation time 420360765 ps
CPU time 0.69 seconds
Started Aug 15 06:20:14 PM PDT 24
Finished Aug 15 06:20:15 PM PDT 24
Peak memory 201976 kb
Host smart-088dc4e8-5da7-477c-88fb-ef17e8f77a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938921125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.938921125
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.807796890
Short name T315
Test name
Test status
Simulation time 375599229611 ps
CPU time 114.25 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:22:05 PM PDT 24
Peak memory 202132 kb
Host smart-c6f4ef8b-2640-40c1-834e-0fdcd0d5aad1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807796890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.807796890
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3709065789
Short name T598
Test name
Test status
Simulation time 161819317982 ps
CPU time 391.49 seconds
Started Aug 15 06:20:09 PM PDT 24
Finished Aug 15 06:26:41 PM PDT 24
Peak memory 202092 kb
Host smart-c00441f2-278d-4805-a2fa-1ebef10e389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709065789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3709065789
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.48225793
Short name T425
Test name
Test status
Simulation time 169281399835 ps
CPU time 102.34 seconds
Started Aug 15 06:20:12 PM PDT 24
Finished Aug 15 06:21:54 PM PDT 24
Peak memory 202084 kb
Host smart-5ac2ca1e-3aba-4e8f-8ee5-10c8298e5d05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=48225793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_
fixed.48225793
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3795251707
Short name T149
Test name
Test status
Simulation time 498343280665 ps
CPU time 204.94 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:23:35 PM PDT 24
Peak memory 202136 kb
Host smart-004f4aa9-9d98-45b0-9443-b7255fa554df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795251707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3795251707
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1592637908
Short name T405
Test name
Test status
Simulation time 401059302517 ps
CPU time 438.81 seconds
Started Aug 15 06:20:07 PM PDT 24
Finished Aug 15 06:27:26 PM PDT 24
Peak memory 202080 kb
Host smart-a1fb8734-3d31-4685-88bc-479b93c6f78f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592637908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1592637908
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1697367025
Short name T353
Test name
Test status
Simulation time 65099086017 ps
CPU time 190.92 seconds
Started Aug 15 06:20:11 PM PDT 24
Finished Aug 15 06:23:22 PM PDT 24
Peak memory 202284 kb
Host smart-3c774c7e-5bae-4dff-a913-50c193c91a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697367025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1697367025
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.866190132
Short name T697
Test name
Test status
Simulation time 25376743819 ps
CPU time 15.57 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:20:26 PM PDT 24
Peak memory 201960 kb
Host smart-7b0b5ad4-c90b-4c03-a338-a160e07f9cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866190132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.866190132
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1946535970
Short name T126
Test name
Test status
Simulation time 5102400154 ps
CPU time 10.65 seconds
Started Aug 15 06:20:12 PM PDT 24
Finished Aug 15 06:20:23 PM PDT 24
Peak memory 201912 kb
Host smart-7eda251b-fa15-4743-905a-235d5a3ccfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946535970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1946535970
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3651294966
Short name T388
Test name
Test status
Simulation time 6122218993 ps
CPU time 7.77 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:20:18 PM PDT 24
Peak memory 201948 kb
Host smart-a246b5c6-ee6f-44d6-853f-b3b4ff20d984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651294966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3651294966
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.685999853
Short name T186
Test name
Test status
Simulation time 84138197304 ps
CPU time 425.99 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:27:16 PM PDT 24
Peak memory 210568 kb
Host smart-2c4ceadd-cb0d-49af-88f4-ce725e620ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685999853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.685999853
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.470038360
Short name T90
Test name
Test status
Simulation time 7371265289 ps
CPU time 5.59 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:20:16 PM PDT 24
Peak memory 210292 kb
Host smart-221b1c11-7c7a-4a98-a6b8-e6702e9cce89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470038360 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.470038360
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3484167462
Short name T534
Test name
Test status
Simulation time 609917910 ps
CPU time 0.73 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:20:11 PM PDT 24
Peak memory 201940 kb
Host smart-23728b3b-2b9a-4d39-ac9d-7bde2da73203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484167462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3484167462
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.300731575
Short name T306
Test name
Test status
Simulation time 561739193155 ps
CPU time 1218.72 seconds
Started Aug 15 06:20:13 PM PDT 24
Finished Aug 15 06:40:32 PM PDT 24
Peak memory 202120 kb
Host smart-0a72a4a3-e09e-49e3-ac93-1c11708766b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300731575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.300731575
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.223035501
Short name T737
Test name
Test status
Simulation time 500808303140 ps
CPU time 328.25 seconds
Started Aug 15 06:20:14 PM PDT 24
Finished Aug 15 06:25:42 PM PDT 24
Peak memory 202168 kb
Host smart-fba290fc-f051-4625-aa80-45cdadced395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223035501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.223035501
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.4141152323
Short name T467
Test name
Test status
Simulation time 488702454837 ps
CPU time 296.01 seconds
Started Aug 15 06:20:13 PM PDT 24
Finished Aug 15 06:25:09 PM PDT 24
Peak memory 202116 kb
Host smart-b5a0d054-3fe0-447e-ad83-bb825adcfc7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141152323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.4141152323
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.4158603713
Short name T761
Test name
Test status
Simulation time 337113816679 ps
CPU time 391.38 seconds
Started Aug 15 06:20:07 PM PDT 24
Finished Aug 15 06:26:39 PM PDT 24
Peak memory 202088 kb
Host smart-b4ad60b0-85b5-4202-9f9f-d8e48d7d6d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158603713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.4158603713
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3822202739
Short name T184
Test name
Test status
Simulation time 488215282351 ps
CPU time 281.18 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:24:51 PM PDT 24
Peak memory 202032 kb
Host smart-d12f62bf-344d-464b-b08c-0dac67a157ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822202739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3822202739
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3519978049
Short name T415
Test name
Test status
Simulation time 198905810020 ps
CPU time 257.28 seconds
Started Aug 15 06:20:09 PM PDT 24
Finished Aug 15 06:24:27 PM PDT 24
Peak memory 201960 kb
Host smart-30d75d25-df9e-4260-a6db-7389035082bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519978049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3519978049
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.4132072059
Short name T568
Test name
Test status
Simulation time 98905548671 ps
CPU time 405.04 seconds
Started Aug 15 06:20:12 PM PDT 24
Finished Aug 15 06:26:57 PM PDT 24
Peak memory 202444 kb
Host smart-a3faa146-b5b6-44d6-ba9e-a60fb468b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132072059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.4132072059
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2802136685
Short name T500
Test name
Test status
Simulation time 23729025673 ps
CPU time 23.66 seconds
Started Aug 15 06:20:09 PM PDT 24
Finished Aug 15 06:20:33 PM PDT 24
Peak memory 201876 kb
Host smart-edec852d-3068-448e-af6e-857f4f1ab0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802136685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2802136685
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2161558546
Short name T430
Test name
Test status
Simulation time 3282954333 ps
CPU time 4.62 seconds
Started Aug 15 06:20:08 PM PDT 24
Finished Aug 15 06:20:13 PM PDT 24
Peak memory 201904 kb
Host smart-a34a66e7-eb6f-4d0c-b1f5-9d955f6e7fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161558546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2161558546
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3747139431
Short name T724
Test name
Test status
Simulation time 5853181662 ps
CPU time 1.42 seconds
Started Aug 15 06:20:14 PM PDT 24
Finished Aug 15 06:20:15 PM PDT 24
Peak memory 201896 kb
Host smart-01921018-abdd-435e-ae6d-be0781e29055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747139431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3747139431
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.30725150
Short name T421
Test name
Test status
Simulation time 202559348189 ps
CPU time 1039.85 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:37:30 PM PDT 24
Peak memory 210656 kb
Host smart-32594c32-aba9-4987-b67f-cc046cb15226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30725150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.30725150
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.204333479
Short name T644
Test name
Test status
Simulation time 4537602947 ps
CPU time 6.37 seconds
Started Aug 15 06:20:14 PM PDT 24
Finished Aug 15 06:20:20 PM PDT 24
Peak memory 202076 kb
Host smart-67660dfa-ba5f-4b97-93b4-a5d37f4ffcbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204333479 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.204333479
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2459899604
Short name T414
Test name
Test status
Simulation time 419927771 ps
CPU time 1.64 seconds
Started Aug 15 06:20:13 PM PDT 24
Finished Aug 15 06:20:14 PM PDT 24
Peak memory 201968 kb
Host smart-e6d31adb-cd5f-40e7-8796-65b3068dc762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459899604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2459899604
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1272065520
Short name T312
Test name
Test status
Simulation time 359680560293 ps
CPU time 644.95 seconds
Started Aug 15 06:20:09 PM PDT 24
Finished Aug 15 06:30:55 PM PDT 24
Peak memory 202120 kb
Host smart-3ff555fc-8137-4c23-858b-a1de9b8d1e39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272065520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1272065520
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3740878234
Short name T181
Test name
Test status
Simulation time 549064081764 ps
CPU time 84.76 seconds
Started Aug 15 06:20:13 PM PDT 24
Finished Aug 15 06:21:38 PM PDT 24
Peak memory 202140 kb
Host smart-478c0427-4212-4c5f-94db-853c837ea8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740878234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3740878234
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3979996944
Short name T333
Test name
Test status
Simulation time 494651127066 ps
CPU time 1176.94 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:39:47 PM PDT 24
Peak memory 202156 kb
Host smart-4f3c7f94-4680-4bbc-ad0d-8bfd5949fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979996944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3979996944
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.987103148
Short name T394
Test name
Test status
Simulation time 498208096875 ps
CPU time 1204.39 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:40:15 PM PDT 24
Peak memory 202180 kb
Host smart-764b6fd3-4515-41a9-9581-c0482a0dddec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=987103148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.987103148
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1383788234
Short name T273
Test name
Test status
Simulation time 327079010044 ps
CPU time 691.42 seconds
Started Aug 15 06:20:13 PM PDT 24
Finished Aug 15 06:31:45 PM PDT 24
Peak memory 202132 kb
Host smart-cad7f1b1-261b-4f37-bc8a-ccd599185b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383788234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1383788234
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1559742066
Short name T504
Test name
Test status
Simulation time 501048846621 ps
CPU time 1136.06 seconds
Started Aug 15 06:20:08 PM PDT 24
Finished Aug 15 06:39:05 PM PDT 24
Peak memory 202088 kb
Host smart-7dd97fe9-81c4-4aad-b1c6-d269206196ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559742066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1559742066
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.886983599
Short name T269
Test name
Test status
Simulation time 423852628212 ps
CPU time 954.11 seconds
Started Aug 15 06:20:08 PM PDT 24
Finished Aug 15 06:36:02 PM PDT 24
Peak memory 202132 kb
Host smart-282dfd23-9214-4255-b858-29589bf00e9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886983599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.886983599
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1040026367
Short name T447
Test name
Test status
Simulation time 586222373193 ps
CPU time 638.4 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:30:49 PM PDT 24
Peak memory 202088 kb
Host smart-da359510-92bd-40a6-8927-a7a81a94b5dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040026367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1040026367
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3704880966
Short name T437
Test name
Test status
Simulation time 87727822860 ps
CPU time 364.42 seconds
Started Aug 15 06:20:13 PM PDT 24
Finished Aug 15 06:26:17 PM PDT 24
Peak memory 202460 kb
Host smart-fa89ac46-ec52-4434-abdb-bf9d6cf568d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704880966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3704880966
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.676738403
Short name T510
Test name
Test status
Simulation time 25700843107 ps
CPU time 57.35 seconds
Started Aug 15 06:20:09 PM PDT 24
Finished Aug 15 06:21:07 PM PDT 24
Peak memory 201944 kb
Host smart-0fff8817-5470-4bc9-a97f-61b1b9f1974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676738403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.676738403
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1627457569
Short name T677
Test name
Test status
Simulation time 5620759069 ps
CPU time 3 seconds
Started Aug 15 06:20:10 PM PDT 24
Finished Aug 15 06:20:13 PM PDT 24
Peak memory 201904 kb
Host smart-8687869a-4087-4084-819e-76feb4a0f5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627457569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1627457569
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3219764037
Short name T554
Test name
Test status
Simulation time 5939006995 ps
CPU time 7.64 seconds
Started Aug 15 06:20:09 PM PDT 24
Finished Aug 15 06:20:17 PM PDT 24
Peak memory 201948 kb
Host smart-33f1943a-ae59-46f6-b53d-80a6cf5bb201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219764037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3219764037
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3927826551
Short name T668
Test name
Test status
Simulation time 198756773927 ps
CPU time 432.71 seconds
Started Aug 15 06:20:12 PM PDT 24
Finished Aug 15 06:27:25 PM PDT 24
Peak memory 202144 kb
Host smart-0148e750-f169-45fc-b013-f587d42e8de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927826551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3927826551
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3852156419
Short name T198
Test name
Test status
Simulation time 26065886771 ps
CPU time 18.26 seconds
Started Aug 15 06:20:12 PM PDT 24
Finished Aug 15 06:20:31 PM PDT 24
Peak memory 211784 kb
Host smart-de96fa92-a7df-4bc1-a5b9-861b9b01fe8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852156419 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3852156419
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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