Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5728	1			T2	60		T5	20		T8	14
testmodes[AdcCtrlTestmodeNormal]	4709	1			T1	1		T2	50		T3	3
testmodes[AdcCtrlTestmodeLowpower]	5021	1			T2	58		T4	16		T10	48
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2940	1			T2	22		T5	19		T8	12
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1502	1			T2	19		T8	1		T10	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1167	1			T2	18		T10	18		T31	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1455	1			T2	18		T8	1		T10	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1672	1			T2	15		T3	2		T6	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1256	1			T2	17		T10	12		T16	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1211	1			T2	20		T10	21		T31	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1206	1			T2	16		T10	9		T16	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2351	1			T2	22		T4	15		T10	18