Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20125

1

T1

11

T2

168

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3209

1

T3

2

T7

30

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17566

1

T2

168

T3

2

T4

16

auto[1]

5768

1

T1

11

T3

1

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	52	1			T28	1		T131	1		T207	12
values[1]	655	1			T29	33		T30	12		T49	1
values[2]	507	1			T7	9		T9	4		T16	3
values[3]	636	1			T140	1		T132	23		T134	16
values[4]	688	1			T3	1		T7	8		T114	25
values[5]	678	1			T1	11		T3	1		T113	1
values[6]	669	1			T30	43		T156	10		T133	11
values[7]	602	1			T40	2		T101	1		T208	8
values[8]	542	1			T49	11		T101	1		T209	14
values[9]	3701	1			T3	1		T6	26		T7	13
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	877	1			T7	9		T16	3		T28	1
values[1]	535	1			T9	4		T140	1		T56	2
values[2]	589	1			T7	8		T132	23		T134	16
values[3]	718	1			T3	1		T113	1		T114	25
values[4]	821	1			T1	11		T3	1		T30	43
values[5]	563	1			T40	2		T134	19		T148	15
values[6]	2907	1			T6	26		T12	14		T13	50
values[7]	464	1			T7	13		T49	11		T101	1
values[8]	1095	1			T3	1		T11	1		T32	2
values[9]	155	1			T210	12		T151	24		T146	1
minimum	14610	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T28	1		T30	8		T57	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	1		T16	3		T29	35
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	4		T140	1		T109	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T56	1		T130	5		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T134	6		T157	1		T211	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	1		T132	18		T212	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	1		T17	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T113	1		T114	2		T132	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	3		T156	1		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	1		T30	20		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T40	2		T134	9		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T148	8		T150	12		T214	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1716	1			T6	2		T12	14		T13	50
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T101	1		T133	1		T148	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T49	5		T131	1		T149	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T7	1		T101	1		T215	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T32	2		T140	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	397	1			T3	1		T11	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T210	5		T151	12		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T216	1		T217	11		T218	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T219	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T30	4		T57	11		T207	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	8		T29	19		T99	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T109	1		T132	9		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T56	1		T130	1		T133	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T134	10		T220	12		T221	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	7		T132	5		T212	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	1		T134	10		T222	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T114	23		T223	3		T222	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	8		T156	9		T109	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	23		T56	1		T224	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T134	10		T213	5		T225	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T148	7		T150	10		T151	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T6	24		T14	23		T39	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T133	12		T148	2		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	6		T149	10		T150	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	12		T139	6		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T56	3		T103	12		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T135	12		T142	18		T224	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T210	7		T151	12		T228	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T217	11		T229	2		T230	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T219	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T28	1		T131	1		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T207	6		T18	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T30	8		T57	11		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	21		T49	1		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	4		T109	2		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T16	3		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T140	1		T134	6		T135	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T132	18		T214	3		T161	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T141	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	1		T114	2		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	3		T17	1		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T113	1		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T156	1		T133	1		T139	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T30	20		T148	8		T150	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T40	2		T208	1		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T101	1		T223	18		T232	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T49	5		T209	14		T149	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T101	1		T133	1		T148	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1802	1			T6	2		T12	14		T13	50
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	441	1			T3	1		T7	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T231	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T207	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T30	4		T57	11		T207	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T29	12		T99	10		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T109	1		T132	9		T223	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	8		T29	7		T56	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T134	10		T135	12		T210	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T132	5		T161	5		T212	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T134	10		T222	6		T161	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	7		T114	23		T223	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	8		T17	1		T109	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T56	1		T224	2		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T156	9		T133	10		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T30	23		T148	7		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T208	7		T134	10		T213	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T223	12		T234	4		T146	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	6		T149	10		T150	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T133	12		T148	2		T139	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T6	24		T14	23		T39	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T7	12		T135	12		T142	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T28	1		T30	5		T57	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	9		T16	3		T29	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	3		T140	1		T109	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T56	2		T130	4		T133	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T134	11		T157	1		T211	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	8		T132	6		T212	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T17	2		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T113	1		T114	25		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	9		T156	10		T109	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	1		T30	25		T56	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T40	2		T134	11		T213	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T148	8		T150	11		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T6	26		T12	1		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T101	1		T133	13		T148	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T49	7		T131	1		T149	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T7	13		T101	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T32	2		T140	1		T56	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T3	1		T11	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T210	8		T151	13		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T216	1		T217	12		T218	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14605	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T219	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T30	7		T57	10		T207	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	33		T136	8		T207	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T109	1		T132	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T130	2		T214	2		T235	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T134	5		T155	10		T221	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T132	17		T212	11		T236	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T237	17		T138	11		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T132	10		T223	3		T222	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	2		T139	8		T235	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T30	18		T233	12		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T134	8		T238	19		T225	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T148	7		T150	11		T214	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T12	13		T13	47		T34	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T148	11		T223	17		T225	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T49	4		T149	8		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T215	8		T139	4		T239	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T227	11		T152	7		T240	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T135	10		T241	25		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T210	4		T151	11		T228	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T217	10		T230	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T28	1		T131	1		T231	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T207	7		T18	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T30	5		T57	12		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T29	13		T49	1		T99	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	3		T109	2		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	9		T16	3		T29	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	1		T134	11		T135	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T132	6		T214	1		T161	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	1		T141	1		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	8		T114	25		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	9		T17	2		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	1		T113	1		T56	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T156	10		T133	11		T139	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T30	25		T148	8		T150	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	2		T208	8		T134	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T101	1		T223	13		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T49	7		T209	1		T149	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T101	1		T133	13		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T6	26		T12	1		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	474	1			T3	1		T7	13		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T242	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T207	5		T18	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	7		T57	10		T207	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T29	20		T136	8		T37	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	1		T109	1		T132	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	13		T130	2		T235	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T134	5		T135	14		T155	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T132	17		T214	2		T161	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T138	11		T222	10		T161	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T223	3		T222	6		T210	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	2		T237	17		T235	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T132	10		T233	12		T155	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T139	8		T160	9		T225	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	18		T148	7		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T134	8		T233	2		T238	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T223	17		T232	7		T234	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	4		T209	13		T149	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T148	11		T139	4		T225	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T12	13		T13	47		T34	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T135	10		T241	25		T142	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20001

1

T1

11

T2

168

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3333

1

T3

1

T7

21

T9

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17695

1

T1

11

T2

168

T3

1

auto[1]

5639

1

T3

2

T6

26

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	94	1			T162	12		T94	3		T170	16
values[1]	576	1			T113	1		T44	6		T104	1
values[2]	796	1			T9	4		T30	20		T56	2
values[3]	687	1			T101	1		T140	1		T208	13
values[4]	2919	1			T3	1		T6	26		T7	8
values[5]	546	1			T49	1		T99	11		T17	2
values[6]	686	1			T7	13		T11	1		T32	2
values[7]	604	1			T29	21		T40	2		T156	10
values[8]	794	1			T1	11		T3	2		T140	1
values[9]	1028	1			T7	9		T114	12		T16	3
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	823	1			T113	1		T44	6		T104	1
values[1]	825	1			T9	4		T30	20		T101	1
values[2]	615	1			T114	13		T101	1		T140	1
values[3]	2876	1			T3	1		T6	26		T7	8
values[4]	627	1			T11	1		T49	1		T17	2
values[5]	704	1			T7	13		T32	2		T40	2
values[6]	601	1			T1	11		T3	1		T29	21
values[7]	844	1			T3	1		T56	6		T141	1
values[8]	697	1			T7	9		T114	12		T16	3
values[9]	98	1			T30	23		T243	1		T146	12
minimum	14624	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T113	1		T104	1		T207	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T44	6		T223	4		T18	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T30	8		T212	1		T225	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	4		T101	1		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T114	1		T132	39		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T101	1		T140	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1688	1			T3	1		T6	2		T12	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	1		T99	1		T148	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	1		T17	1		T209	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	1		T207	4		T241	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	2		T57	11		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	1		T32	2		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	3		T3	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T29	14		T156	1		T148	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T56	2		T141	1		T227	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	1		T103	1		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	1		T114	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T16	3		T29	21		T49	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T30	12		T243	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T146	1		T245	1		T246	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T247	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T207	6		T223	1		T161	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T223	3		T235	11		T154	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T30	12		T225	2		T226	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T56	1		T149	10		T139	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T114	12		T132	14		T133	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T208	12		T134	10		T221	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T6	24		T14	23		T39	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T7	7		T99	10		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T17	1		T160	10		T144	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T207	2		T210	10		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T57	11		T109	1		T223	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	12		T109	1		T130	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T1	8		T37	11		T212	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T29	7		T156	9		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	4		T227	13		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T103	12		T134	10		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	8		T114	11		T30	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	12		T49	6		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T30	11		T244	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T146	11		T246	2		T248	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T247	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T162	3		T94	1		T170	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T249	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T113	1		T104	1		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	6		T223	4		T18	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T30	8		T132	10		T207	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	4		T56	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T132	29		T133	1		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T101	1		T140	1		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1668	1			T3	1		T6	2		T12	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	1		T101	1		T134	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T49	1		T17	1		T209	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T99	1		T241	16		T215	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T57	11		T109	2		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T11	1		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T40	2		T149	1		T237	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	14		T156	1		T148	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	3		T3	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T3	1		T103	1		T134	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	1		T114	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T16	3		T29	21		T49	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T162	9		T94	2		T170	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T223	1		T161	12		T213	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T223	3		T154	11		T164	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	12		T132	9		T207	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T56	1		T149	10		T222	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T132	5		T133	16		T224	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T208	12		T139	8		T250	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T6	24		T14	23		T39	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T7	7		T134	10		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T17	1		T208	7		T150	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T99	10		T210	10		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	11		T109	1		T223	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	12		T109	1		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T37	11		T251	19		T252	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	7		T156	9		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	8		T56	4		T233	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T103	12		T134	10		T224	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	8		T114	11		T30	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T29	12		T49	6		T133	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2