Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20001

1

T1

11

T2

168

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3333

1

T3

1

T7

21

T9

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17695

1

T1

11

T2

168

T3

1

auto[1]

5639

1

T3

2

T6

26

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	277	1			T114	12		T29	33		T30	23
values[0]	20	1			T94	3		T322	1		T310	11
values[1]	648	1			T113	1		T44	6		T104	1
values[2]	816	1			T9	4		T30	20		T56	2
values[3]	656	1			T101	1		T140	1		T208	13
values[4]	2902	1			T3	1		T6	26		T7	8
values[5]	587	1			T49	1		T99	11		T17	2
values[6]	656	1			T7	13		T11	1		T32	2
values[7]	637	1			T29	21		T40	2		T140	1
values[8]	763	1			T1	11		T3	2		T56	6
values[9]	768	1			T7	9		T16	3		T28	1
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	618	1			T113	1		T44	6		T104	1
values[1]	827	1			T9	4		T30	20		T101	1
values[2]	627	1			T114	13		T101	1		T140	1
values[3]	2851	1			T3	1		T6	26		T7	8
values[4]	616	1			T11	1		T49	1		T17	2
values[5]	706	1			T7	13		T32	2		T40	2
values[6]	635	1			T1	11		T3	1		T29	21
values[7]	816	1			T3	1		T56	6		T141	1
values[8]	732	1			T7	9		T114	12		T16	3
values[9]	51	1			T146	12		T245	1		T246	7
minimum	14855	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T113	1		T104	1		T207	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T44	6		T235	15		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T30	8		T212	1		T225	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	4		T101	1		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T114	1		T132	39		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T101	1		T140	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1681	1			T3	1		T6	2		T12	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	1		T99	1		T148	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T49	1		T17	1		T209	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T140	1		T241	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T40	2		T57	11		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T32	2		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	3		T3	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T29	14		T156	1		T148	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T56	2		T141	1		T227	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	1		T103	1		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	1		T114	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T16	3		T29	21		T49	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T146	1		T245	1		T246	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14580	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T223	4		T18	4		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T207	6		T223	1		T161	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T235	11		T154	11		T292	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	12		T225	2		T226	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T56	1		T149	10		T139	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T114	12		T132	14		T133	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T208	12		T134	10		T221	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T6	24		T14	23		T39	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T7	7		T99	10		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T17	1		T208	7		T160	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T210	10		T151	12		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T57	11		T109	1		T223	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	12		T109	1		T130	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T1	8		T37	11		T212	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T29	7		T156	9		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T56	4		T227	13		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T103	12		T134	10		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	8		T114	11		T30	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	12		T49	6		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T146	11		T246	2		T248	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	2		T8	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T223	3		T164	14		T317	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T114	1		T30	12		T154	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T29	21		T285	13		T253	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T94	1		T322	1		T310	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T249	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T113	1		T104	1		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T44	6		T223	4		T18	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T30	8		T207	6		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	4		T56	1		T149	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T132	39		T133	1		T214	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T101	1		T140	1		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T3	1		T6	2		T12	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	1		T101	1		T134	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	1		T17	1		T209	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T99	1		T241	16		T215	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T57	11		T109	2		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	1		T11	1		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	2		T140	1		T237	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T29	14		T156	1		T148	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	3		T3	1		T56	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T3	1		T103	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	1		T28	1		T30	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T16	3		T49	5		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T114	11		T30	11		T154	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T29	12		T248	6		T262	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T94	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T223	1		T161	12		T213	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T223	3		T154	11		T164	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T30	12		T207	6		T225	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T56	1		T149	10		T222	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T132	14		T133	16		T224	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T208	12		T139	8		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T6	24		T14	23		T39	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T7	7		T134	10		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T17	1		T208	7		T150	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T99	10		T210	10		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T57	11		T109	1		T223	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	12		T109	1		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T37	11		T212	10		T251	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	7		T156	9		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	8		T56	4		T133	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T103	12		T224	16		T139	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	8		T30	4		T227	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T49	6		T133	10		T134	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T113	1		T104	1		T207	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T44	6		T235	12		T154	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T30	13		T212	1		T225	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	3		T101	1		T56	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T114	13		T132	17		T133	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T101	1		T140	1		T208	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T3	1		T6	26		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	8		T99	11		T148	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T49	1		T17	2		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	1		T140	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T40	2		T57	12		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	13		T32	2		T109	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	9		T3	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	8		T156	10		T148	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T56	6		T141	1		T227	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	1		T103	13		T134	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	9		T114	12		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	3		T29	13		T49	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T146	12		T245	1		T246	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14660	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T223	4		T18	3		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T207	5		T161	13		T151	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T235	14		T164	12		T292	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T30	7		T225	4		T232	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T149	8		T214	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T132	36		T214	2		T152	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T134	5		T241	10		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T12	13		T13	47		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T148	7		T207	3		T150	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T209	13		T160	9		T239	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T241	15		T215	8		T210	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T57	10		T109	1		T223	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T130	2		T150	9		T142	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T1	2		T37	11		T212	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T29	13		T148	11		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T227	11		T138	11		T233	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T134	8		T135	10		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T30	18		T139	4		T226	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T29	20		T49	4		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T246	4		T248	2		T323	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T254	20		T310	10		T324	28
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T223	3		T18	1		T164	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T114	12		T30	12		T154	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T29	13		T285	1		T253	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T94	3		T322	1		T310	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T249	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T113	1		T104	1		T223	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T44	6		T223	4		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T30	13		T207	7		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T9	3		T56	2		T149	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T132	17		T133	17		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T101	1		T140	1		T208	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T3	1		T6	26		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	8		T101	1		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	1		T17	2		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T99	11		T241	1		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T57	12		T109	2		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	13		T11	1		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T40	2		T140	1		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	8		T156	10		T148	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	9		T3	1		T56	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	1		T103	13		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	9		T28	1		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T16	3		T49	7		T133	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T30	11		T226	6		T274	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T29	20		T285	12		T253	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T310	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T161	13		T151	14		T233	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T223	3		T18	1		T164	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T30	7		T207	5		T225	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	1		T149	8		T214	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T132	36		T214	2		T152	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T241	10		T139	8		T253	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T12	13		T13	47		T34	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T134	5		T148	7		T207	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T209	13		T150	12		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T241	15		T215	8		T210	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T57	10		T109	1		T223	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T130	2		T142	11		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T237	17		T37	11		T212	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T29	13		T148	11		T135	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	2		T138	11		T233	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T224	11		T139	11		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T30	7		T227	11		T139	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T49	4		T134	8		T135	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13