Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19817

1

T2

168

T3

3

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3517

1

T1

11

T7

30

T9

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17683

1

T2

168

T3

2

T4

16

auto[1]

5651

1

T1

11

T3

1

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T148	15		T325	9		T180	1
values[0]	52	1			T301	19		T89	2		T318	5
values[1]	737	1			T3	1		T30	20		T40	2
values[2]	518	1			T7	21		T113	1		T56	2
values[3]	810	1			T11	1		T49	11		T141	1
values[4]	659	1			T114	12		T101	1		T141	1
values[5]	2972	1			T6	26		T12	14		T13	50
values[6]	629	1			T7	9		T30	12		T99	11
values[7]	737	1			T114	13		T29	54		T209	14
values[8]	452	1			T3	1		T16	3		T30	23
values[9]	1139	1			T1	11		T3	1		T9	4
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	915	1			T113	1		T30	20		T49	1
values[1]	499	1			T3	1		T7	21		T11	1
values[2]	869	1			T114	12		T49	11		T44	6
values[3]	2947	1			T6	26		T12	14		T13	50
values[4]	522	1			T17	2		T140	1		T56	4
values[5]	785	1			T7	9		T30	12		T99	11
values[6]	687	1			T114	13		T29	21		T208	13
values[7]	462	1			T3	1		T16	3		T29	33
values[8]	847	1			T3	1		T9	4		T28	1
values[9]	170	1			T1	11		T133	13		T157	1
minimum	14631	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T49	1		T132	18		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T113	1		T30	8		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T56	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T7	2		T11	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	5		T235	15		T210	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T114	1		T44	6		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1701	1			T6	2		T12	14		T13	50
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T101	1		T141	1		T130	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T140	1		T56	1		T109	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	1		T132	10		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T30	8		T140	1		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	1		T99	1		T209	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T114	1		T29	14		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T208	1		T131	1		T132	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T3	1		T29	21		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T16	3		T30	12		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	1		T28	1		T223	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T9	4		T101	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T326	1		T316	1		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T1	3		T133	1		T157	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14505	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T327	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T132	5		T223	3		T154	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T30	12		T156	9		T227	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T56	1		T103	12		T207	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T7	19		T212	10		T154	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T49	6		T235	11		T210	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T114	11		T133	16		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T6	24		T14	23		T39	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T130	1		T220	12		T192	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T56	3		T109	2		T224	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T17	1		T132	9		T148	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T30	4		T208	7		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	8		T99	10		T57	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T114	12		T29	7		T224	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T208	12		T135	12		T139	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T29	12		T213	5		T153	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T30	11		T223	1		T139	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T223	12		T151	28		T146	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T56	1		T148	7		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T306	1		T328	5		T256	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T1	8		T133	12		T94	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T327	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T180	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T148	8		T325	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T329	9		T330	1		T331	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T301	12		T89	1		T318	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	1		T40	2		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	8		T227	12		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T56	1		T103	1		T207	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	2		T113	1		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T49	5		T141	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	1		T42	1		T44	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T134	6		T150	10		T235	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T114	1		T101	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1726	1			T6	2		T12	14		T13	50
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	1		T132	10		T148	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T30	8		T140	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T99	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T114	1		T29	35		T214	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T209	14		T208	1		T57	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T3	1		T104	1		T222	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T16	3		T30	12		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	1		T28	1		T223	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T1	3		T9	4		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T148	7		T325	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T329	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T301	7		T89	1		T318	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T132	5		T223	3		T154	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	12		T227	13		T134	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T56	1		T103	12		T207	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	19		T156	9		T37	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	6		T207	2		T210	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T130	1		T133	16		T210	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T134	10		T150	7		T235	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T114	11		T136	10		T162	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T6	24		T14	23		T39	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T17	1		T132	9		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T30	4		T208	7		T224	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	8		T99	10		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T114	12		T29	19		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T208	12		T57	11		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T222	7		T213	5		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T30	11		T223	1		T236	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T223	12		T151	28		T153	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T1	8		T56	1		T133	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9] , minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T49	1		T132	6		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T113	1		T30	13		T156	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	1		T56	2		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	21		T11	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	7		T235	12		T210	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T114	12		T44	6		T133	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T6	26		T12	1		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T101	1		T141	1		T130	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	1		T56	4		T109	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T17	2		T132	10		T148	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T30	5		T140	1		T208	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	9		T99	11		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T114	13		T29	8		T224	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T208	13		T131	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	1		T29	13		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T16	3		T30	12		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	1		T28	1		T223	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	3		T101	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T326	1		T316	1		T306	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T1	9		T133	13		T157	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14606	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T327	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T132	17		T223	3		T138	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T30	7		T227	11		T134	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T207	8		T150	12		T142	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T212	11		T292	12		T332	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	4		T235	14		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T136	8		T169	12		T210	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T12	13		T13	47		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T130	2		T269	15		T232	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T109	1		T224	11		T234	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T132	9		T148	11		T161	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T30	7		T237	17		T139	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T209	13		T57	10		T150	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T29	13		T222	6		T255	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T132	10		T135	14		T139	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T29	20		T214	8		T255	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T30	11		T215	8		T139	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T223	17		T151	25		T146	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	1		T148	7		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T1	2		T94	13		T263	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T327	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T180	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T148	8		T325	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T329	13		T330	1		T331	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T301	8		T89	2		T318	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	1		T40	2		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	13		T227	14		T134	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T56	2		T103	13		T207	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	21		T113	1		T156	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T49	7		T141	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	1		T42	1		T44	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T134	11		T150	8		T235	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T114	12		T101	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T6	26		T12	1		T13	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T17	2		T132	10		T148	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T30	5		T140	1		T208	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	9		T99	11		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T114	13		T29	21		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T209	1		T208	13		T57	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T3	1		T104	1		T222	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	3		T30	12		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T3	1		T28	1		T223	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T1	9		T9	3		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T148	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T329	8		T331	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T301	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T132	17		T223	3		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	7		T227	11		T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T207	5		T150	12		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T37	11		T233	12		T212	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T49	4		T207	3		T18	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T130	2		T169	12		T210	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T134	5		T150	9		T235	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T136	8		T269	15		T232	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T12	13		T13	47		T34	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T132	9		T148	11		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T30	7		T237	17		T233	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T150	11		T161	19		T236	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T29	33		T214	8		T139	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T209	13		T57	10		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T222	6		T255	5		T226	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	11		T215	8		T236	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T223	17		T151	25		T146	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T1	2		T9	1		T135	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13