Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20390

1

T2

168

T3

1

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

2944

1

T1

11

T3

2

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17493

1

T1

11

T2

168

T3

2

auto[1]

5841

1

T3

1

T6

26

T7

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	218	1			T114	13		T209	14		T223	30
values[0]	25	1			T310	12		T305	4		T333	7
values[1]	749	1			T113	1		T28	1		T49	11
values[2]	784	1			T7	8		T101	1		T132	23
values[3]	700	1			T30	23		T103	13		T136	19
values[4]	741	1			T9	4		T109	2		T150	22
values[5]	628	1			T30	12		T99	11		T17	2
values[6]	510	1			T7	9		T114	12		T30	20
values[7]	637	1			T1	11		T3	2		T29	33
values[8]	2908	1			T3	1		T6	26		T12	14
values[9]	830	1			T7	13		T11	1		T16	3
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	588	1			T49	11		T101	1		T56	2
values[1]	818	1			T7	8		T30	23		T101	1
values[2]	740	1			T9	4		T103	13		T150	17
values[3]	659	1			T17	2		T140	1		T104	1
values[4]	596	1			T30	12		T99	11		T156	10
values[5]	498	1			T1	11		T3	1		T7	9
values[6]	3117	1			T3	1		T6	26		T12	14
values[7]	460	1			T3	1		T16	3		T29	21
values[8]	827	1			T7	13		T11	1		T114	13
values[9]	73	1			T223	30		T245	1		T334	2
minimum	14958	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T56	1		T132	18		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	5		T101	1		T208	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T148	12		T235	15		T160	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T7	1		T30	12		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T103	1		T169	13		T139	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	4		T150	10		T152	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T104	1		T149	9		T150	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	1		T140	1		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T99	1		T44	6		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	8		T156	1		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T7	1		T30	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T1	3		T114	1		T130	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1779	1			T6	2		T12	14		T13	50
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T49	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T16	3		T29	14		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	1		T56	1		T109	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	1		T114	1		T209	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	1		T141	1		T237	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T223	18		T302	1		T295	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T245	1		T334	2		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14629	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T113	1		T222	7		T210	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T56	1		T132	5		T133	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T49	6		T208	19		T142	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T148	2		T235	11		T160	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	7		T30	11		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T103	12		T139	6		T161	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T150	7		T225	2		T308	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T149	10		T150	10		T224	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T17	1		T109	1		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T99	10		T207	2		T210	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T30	4		T156	9		T150	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	8		T30	12		T235	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	8		T114	11		T130	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T6	24		T14	23		T39	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T57	11		T207	6		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T29	7		T133	10		T224	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T56	1		T109	1		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	12		T114	12		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T139	8		T145	16		T236	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T223	12		T302	8		T295	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	2		T8	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T222	7		T210	10		T236	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T114	1		T209	14		T223	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T178	1		T268	12		T336	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T310	12		T333	7		T249	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T305	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T28	1		T56	1		T227	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T113	1		T49	5		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T132	18		T148	12		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	1		T101	1		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T103	1		T169	13		T139	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	12		T136	9		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T150	12		T214	9		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	4		T109	1		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T99	1		T44	6		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	8		T17	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	1		T30	8		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T114	1		T42	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	1		T29	21		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	3		T3	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1650	1			T6	2		T12	14		T13	50
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T56	1		T57	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T16	3		T29	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T141	1		T132	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T114	12		T223	12		T228	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T337	11		T338	11		T339	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T249	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T56	1		T227	13		T133	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T49	6		T208	19		T142	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T132	5		T148	2		T135	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	7		T134	10		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T103	12		T139	6		T161	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	11		T136	10		T150	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T150	10		T224	16		T250	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T109	1		T225	10		T308	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T99	10		T149	10		T207	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	4		T17	1		T156	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	8		T30	12		T235	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T114	11		T133	16		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T29	12		T223	3		T151	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	8		T130	1		T223	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T6	24		T14	23		T39	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T56	1		T57	11		T109	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	12		T29	7		T224	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T132	9		T139	8		T233	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	2		T132	6		T133	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	7		T101	1		T208	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T148	3		T235	12		T160	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T7	8		T30	12		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T103	13		T169	1		T139	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	3		T150	8		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T104	1		T149	11		T150	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	2		T140	1		T109	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T99	11		T44	6		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	5		T156	10		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T7	9		T30	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	9		T114	12		T130	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T6	26		T12	1		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T49	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T16	3		T29	8		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	1		T56	2		T109	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T7	13		T114	13		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T141	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T223	13		T302	9		T295	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T245	1		T334	2		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14751	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T113	1		T222	8		T210	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T132	17		T135	10		T151	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T49	4		T132	10		T214	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T148	11		T235	14		T160	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T30	11		T134	5		T135	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T169	12		T139	4		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	1		T150	9		T152	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T149	8		T150	11		T214	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T138	11		T225	10		T232	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T207	3		T210	4		T161	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T30	7		T150	12		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T30	7		T241	10		T235	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T1	2		T130	2		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1439	1			T12	13		T13	47		T29	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T57	10		T207	5		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T29	13		T253	4		T94	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T109	1		T132	9		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T209	13		T294	12		T261	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T237	17		T139	8		T269	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T223	17		T295	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T227	11		T134	8		T241	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T222	6		T210	17		T340	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T114	13		T209	1		T223	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T178	1		T268	1		T336	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T310	1		T333	1		T249	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T305	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T28	1		T56	2		T227	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T113	1		T49	7		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T132	6		T148	3		T135	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	8		T101	1		T134	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T103	13		T169	1		T139	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T30	12		T136	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T150	11		T214	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	3		T109	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T99	11		T44	6		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	5		T17	2		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	9		T30	13		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T114	12		T42	1		T133	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T29	13		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	9		T3	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T6	26		T12	1		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T56	2		T57	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T7	13		T16	3		T29	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	1		T141	1		T132	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T209	13		T223	17		T228	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T268	11		T310	10		T298	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T310	11		T333	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T305	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T227	11		T134	8		T241	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T49	4		T132	10		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T132	17		T148	11		T135	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T134	5		T135	14		T214	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T169	12		T139	4		T161	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T30	11		T136	8		T150	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T150	11		T214	8		T215	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	1		T138	11		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T149	8		T207	3		T161	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	7		T150	12		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T30	7		T241	10		T235	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T251	7		T246	4		T341	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T29	20		T223	3		T160	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T1	2		T130	2		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T12	13		T13	47		T34	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T57	10		T109	1		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T29	13		T294	12		T261	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T132	9		T237	17		T139	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13