Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20164

1

T2

168

T3

2

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3170

1

T1

11

T3

1

T9

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17500

1

T1

11

T2

168

T3

3

auto[1]

5834

1

T6

26

T7

8

T11

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	324	1			T208	8		T135	23		T151	24
values[0]	14	1			T11	1		T276	13		-	-
values[1]	523	1			T16	3		T56	2		T104	1
values[2]	3228	1			T1	11		T6	26		T12	14
values[3]	584	1			T7	9		T113	1		T32	2
values[4]	729	1			T3	2		T141	1		T103	13
values[5]	719	1			T30	23		T101	1		T141	1
values[6]	676	1			T114	13		T30	20		T156	10
values[7]	594	1			T40	2		T209	14		T227	25
values[8]	542	1			T3	1		T9	4		T49	11
values[9]	797	1			T7	21		T114	12		T29	21
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	631	1			T1	11		T140	1		T56	2
values[1]	3081	1			T6	26		T12	14		T13	50
values[2]	616	1			T7	9		T49	1		T42	1
values[3]	716	1			T3	2		T141	1		T103	13
values[4]	814	1			T114	13		T30	43		T101	1
values[5]	538	1			T156	10		T227	25		T133	11
values[6]	622	1			T40	2		T140	1		T209	14
values[7]	542	1			T3	1		T9	4		T49	11
values[8]	847	1			T7	21		T114	12		T29	21
values[9]	131	1			T44	6		T135	23		T151	24
minimum	14796	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T56	1		T104	1		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	3		T140	1		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1697	1			T6	2		T12	14		T13	50
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T32	2		T134	1		T150	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	1		T49	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T272	1		T241	11		T169	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	1		T141	1		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	1		T103	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T114	1		T141	1		T57	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T30	20		T101	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T156	1		T227	12		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T137	1		T223	1		T222	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	2		T130	5		T132	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T140	1		T209	14		T132	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	1		T49	5		T18	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	4		T99	1		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T7	2		T29	14		T30	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T114	1		T17	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T151	12		T290	6		T185	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T44	6		T135	11		T273	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14566	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T213	1		T255	6		T276	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T56	1		T133	16		T134	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	8		T208	12		T149	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T6	24		T14	23		T39	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T134	10		T150	10		T235	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	8		T150	7		T145	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T139	6		T233	7		T293	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T250	8		T236	1		T164	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T103	12		T148	2		T150	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T114	12		T57	11		T223	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	23		T139	10		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T156	9		T227	13		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T223	1		T222	13		T235	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T130	1		T132	5		T148	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T132	9		T134	10		T136	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T49	6		T225	2		T145	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T99	10		T56	1		T222	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	19		T29	7		T30	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T114	11		T17	1		T208	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T151	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T135	12		T273	2		T228	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	2		T8	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T213	5		T295	9		T278	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T151	12		T232	8		T236	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T208	1		T135	11		T273	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T11	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T276	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	3		T56	1		T104	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T149	9		T214	6		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1727	1			T6	2		T12	14		T13	50
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T1	3		T140	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T113	1		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T32	2		T237	18		T241	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T141	1		T214	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T103	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T141	1		T57	11		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T30	12		T101	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T114	1		T156	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	8		T137	1		T277	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T40	2		T227	12		T148	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T209	14		T132	10		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T49	5		T130	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	4		T99	1		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T7	2		T29	14		T30	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T114	1		T17	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T151	12		T236	9		T182	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T208	7		T135	12		T273	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T56	1		T133	16		T134	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T149	10		T213	5		T154	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T6	24		T14	23		T39	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	8		T208	12		T134	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	8		T150	7		T224	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T139	6		T161	12		T274	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T250	8		T236	1		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T103	12		T148	2		T150	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T57	11		T223	12		T142	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T30	11		T139	10		T225	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T114	12		T156	9		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T30	12		T222	13		T235	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T227	13		T148	7		T210	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T132	9		T134	10		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T49	6		T130	1		T132	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T99	10		T222	7		T151	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	19		T29	7		T30	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T114	11		T17	1		T56	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T56	2		T104	1		T133	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	9		T140	1		T208	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T6	26		T12	1		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T32	2		T134	11		T150	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	9		T49	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T272	1		T241	1		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T141	1		T250	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T103	13		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T114	13		T141	1		T57	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	25		T101	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T156	10		T227	14		T133	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T137	1		T223	2		T222	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	2		T130	4		T132	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T140	1		T209	1		T132	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T49	7		T18	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	3		T99	11		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T7	21		T29	8		T30	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T114	12		T17	2		T208	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T151	13		T290	1		T185	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T44	6		T135	13		T273	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14660	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T213	6		T255	1		T276	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T134	5		T135	14		T207	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	2		T149	8		T214	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T12	13		T13	47		T29	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T150	11		T237	17		T241	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T150	9		T214	2		T145	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T241	10		T169	12		T139	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T164	13		T280	19		T281	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T148	11		T150	12		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T57	10		T223	17		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T30	18		T139	11		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T227	11		T210	17		T255	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T222	8		T235	14		T161	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	2		T132	17		T148	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T209	13		T132	9		T134	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T49	4		T18	1		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	1		T132	10		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T29	13		T30	7		T109	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T210	4		T255	3		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T151	11		T290	5		T185	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T135	10		T228	13		T259	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T138	11		T221	15		T262	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T255	5		T276	12		T295	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T151	13		T232	1		T236	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T208	8		T135	13		T273	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T11	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	3		T56	2		T104	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T149	11		T214	1		T213	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T6	26		T12	1		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	9		T140	1		T208	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	9		T113	1		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T32	2		T237	1		T241	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	1		T141	1		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T103	13		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T141	1		T57	12		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	12		T101	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T114	13		T156	10		T133	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T30	13		T137	1		T277	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	2		T227	14		T148	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T209	1		T132	10		T134	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	1		T49	7		T130	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	3		T99	11		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T7	21		T29	8		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T114	12		T17	2		T56	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T151	11		T232	7		T236	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T135	10		T20	1		T94	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T276	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T134	5		T135	14		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T149	8		T214	5		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T12	13		T13	47		T29	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	2		T150	11		T235	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T150	9		T145	4		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T237	17		T241	25		T139	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T214	2		T282	11		T164	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T148	11		T150	12		T169	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T57	10		T223	17		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	11		T139	11		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T255	11		T162	2		T297	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T30	7		T222	8		T235	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T227	11		T148	7		T210	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T209	13		T132	9		T134	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T49	4		T130	2		T132	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T9	1		T132	10		T222	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T29	13		T30	7		T109	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T210	4		T255	3		T292	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13