Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20225

1

T2

168

T3

2

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3109

1

T1

11

T3

1

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17177

1

T2

167

T3

1

T4

16

auto[1]

6157

1

T1

11

T2

1

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	334	1			T2	1		T10	5		T16	3
values[0]	10	1			T113	1		T140	1		T216	1
values[1]	684	1			T7	9		T9	4		T11	1
values[2]	2993	1			T6	26		T12	14		T13	50
values[3]	610	1			T7	8		T30	12		T99	11
values[4]	675	1			T30	20		T141	1		T133	13
values[5]	652	1			T1	11		T3	1		T16	3
values[6]	649	1			T7	13		T28	1		T40	2
values[7]	537	1			T3	1		T101	1		T209	14
values[8]	782	1			T3	1		T30	23		T49	11
values[9]	1105	1			T114	12		T29	33		T49	1
minimum	14303	1			T2	167		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	872	1			T7	9		T9	4		T11	1
values[1]	2986	1			T6	26		T12	14		T13	50
values[2]	623	1			T7	8		T30	20		T99	11
values[3]	663	1			T141	1		T132	19		T133	17
values[4]	556	1			T1	11		T3	1		T16	3
values[5]	756	1			T7	13		T209	14		T104	1
values[6]	508	1			T3	1		T40	2		T101	1
values[7]	820	1			T3	1		T30	23		T49	11
values[8]	781	1			T114	12		T29	33		T49	1
values[9]	162	1			T101	1		T139	22		T257	1
minimum	14607	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	1		T9	4		T29	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	1		T113	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1709	1			T6	2		T12	14		T13	50
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T56	1		T149	1		T214	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T136	9		T223	18		T143	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	1		T30	8		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T132	10		T207	6		T214	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T141	1		T133	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	1		T16	3		T227	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	3		T28	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T7	1		T209	14		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T135	11		T243	1		T253	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T101	1		T56	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	1		T40	2		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T3	1		T30	12		T49	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T208	1		T132	18		T215	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T114	1		T29	21		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T49	1		T109	2		T132	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T101	1		T257	1		T317	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T139	12		T318	1		T248	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T289	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	8		T29	7		T17	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T149	10		T150	7		T210	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T6	24		T14	23		T39	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	3		T235	11		T210	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T136	10		T223	12		T160	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	7		T30	12		T99	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T132	9		T207	6		T225	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	16		T150	7		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T227	13		T135	12		T318	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T1	8		T133	10		T89	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	12		T130	1		T223	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T135	12		T226	2		T163	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T56	1		T109	1		T233	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T151	16		T247	10		T342	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T30	11		T49	6		T57	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T208	7		T132	5		T139	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T114	11		T29	12		T134	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T109	1		T134	10		T139	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T317	5		T259	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T139	10		T318	4		T248	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T289	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T2	1		T10	5		T16	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T343	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T140	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T113	1		T216	1		T315	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T9	4		T29	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	1		T131	1		T149	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T6	2		T12	14		T13	50
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T56	1		T149	1		T214	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T30	8		T141	1		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	1		T99	1		T103	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T207	6		T223	18		T214	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T30	8		T141	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T3	1		T16	3		T227	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	3		T140	1		T44	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	1		T109	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T28	1		T40	2		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T101	1		T209	14		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T3	1		T272	1		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T3	1		T30	12		T49	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T132	18		T215	9		T139	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T114	1		T29	21		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T49	1		T208	1		T109	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14202	1			T2	167		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T317	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T343	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	8		T29	7		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T149	10		T150	7		T210	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T6	24		T14	23		T39	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T56	3		T235	11		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T30	4		T132	9		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	7		T99	10		T103	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T207	6		T223	12		T160	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	12		T133	12		T233	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T227	13		T135	12		T225	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T1	8		T133	16		T150	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	12		T109	1		T223	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T133	10		T135	12		T163	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T130	1		T222	6		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T247	10		T342	15		T344	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T30	11		T49	6		T56	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T132	5		T139	6		T235	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T114	11		T29	12		T134	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T208	7		T109	1		T134	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T7	9		T9	3		T29	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	1		T113	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T6	26		T12	1		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T56	4		T149	1		T214	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T136	11		T223	13		T143	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	8		T30	13		T99	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T132	10		T207	7		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T141	1		T133	17		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	1		T16	3		T227	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	9		T28	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T7	13		T209	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T135	13		T243	1		T253	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T101	1		T56	2		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	1		T40	2		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	1		T30	12		T49	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T208	8		T132	6		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T114	12		T29	13		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T49	1		T109	2		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T101	1		T257	1		T317	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T139	11		T318	5		T248	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T289	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	1		T29	13		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T149	8		T150	9		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T12	13		T13	47		T30	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T214	5		T235	14		T210	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T136	8		T223	17		T160	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T30	7		T224	11		T210	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T132	9		T207	5		T214	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T150	12		T151	9		T232	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T227	11		T135	14		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T1	2		T237	17		T285	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T209	13		T130	2		T223	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T135	10		T253	13		T226	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T233	2		T162	2		T94	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T151	14		T255	11		T247	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T30	11		T49	4		T57	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T132	17		T215	8		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T29	20		T134	8		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T109	1		T132	10		T134	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T317	14		T259	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T139	11		T248	2		T296	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T289	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T2	1		T10	5		T16	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T343	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T140	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T113	1		T216	1		T315	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	9		T9	3		T29	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	1		T131	1		T149	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T6	26		T12	1		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T56	4		T149	1		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T30	5		T141	1		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	8		T99	11		T103	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T207	7		T223	13		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T30	13		T141	1		T133	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T16	3		T227	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	9		T140	1		T44	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	13		T109	2		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T28	1		T40	2		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T101	1		T209	1		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	1		T272	1		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T30	12		T49	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T132	6		T215	1		T139	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T114	12		T29	13		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T49	1		T208	8		T109	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14303	1			T2	167		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T317	14		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T343	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T345	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	1		T29	13		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T149	8		T150	9		T160	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T12	13		T13	47		T34	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T214	5		T235	14		T210	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T30	7		T132	9		T136	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T224	11		T210	4		T301	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T207	5		T223	17		T214	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	7		T152	7		T233	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T227	11		T135	14		T214	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T1	2		T150	12		T237	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T223	3		T145	17		T234	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T135	10		T240	17		T268	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T209	13		T130	2		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T255	11		T247	9		T346	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T30	11		T49	4		T57	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T132	17		T215	8		T139	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T29	20		T134	8		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T109	1		T132	10		T134	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13